1 /* 2 * Faraday FOTG210 USB OTG controller 3 * 4 * Copyright (C) 2013 Faraday Technology Corporation 5 * Author: Yuan-Hsin Chen <yhchen@faraday-tech.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13 #include <linux/kernel.h> 14 15 #define FOTG210_MAX_NUM_EP 5 /* ep0...ep4 */ 16 #define FOTG210_MAX_FIFO_NUM 4 /* fifo0...fifo4 */ 17 18 /* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */ 19 #define FOTG210_GMIR 0xC4 20 #define GMIR_INT_POLARITY 0x8 /*Active High*/ 21 #define GMIR_MHC_INT 0x4 22 #define GMIR_MOTG_INT 0x2 23 #define GMIR_MDEV_INT 0x1 24 25 /* Device Main Control Register(0x100) */ 26 #define FOTG210_DMCR 0x100 27 #define DMCR_HS_EN (1 << 6) 28 #define DMCR_CHIP_EN (1 << 5) 29 #define DMCR_SFRST (1 << 4) 30 #define DMCR_GOSUSP (1 << 3) 31 #define DMCR_GLINT_EN (1 << 2) 32 #define DMCR_HALF_SPEED (1 << 1) 33 #define DMCR_CAP_RMWAKUP (1 << 0) 34 35 /* Device Address Register(0x104) */ 36 #define FOTG210_DAR 0x104 37 #define DAR_AFT_CONF (1 << 7) 38 39 /* Device Test Register(0x108) */ 40 #define FOTG210_DTR 0x108 41 #define DTR_TST_CLRFF (1 << 0) 42 43 /* PHY Test Mode Selector register(0x114) */ 44 #define FOTG210_PHYTMSR 0x114 45 #define PHYTMSR_TST_PKT (1 << 4) 46 #define PHYTMSR_TST_SE0NAK (1 << 3) 47 #define PHYTMSR_TST_KSTA (1 << 2) 48 #define PHYTMSR_TST_JSTA (1 << 1) 49 #define PHYTMSR_UNPLUG (1 << 0) 50 51 /* Cx configuration and FIFO Empty Status register(0x120) */ 52 #define FOTG210_DCFESR 0x120 53 #define DCFESR_FIFO_EMPTY(fifo) (1 << 8 << (fifo)) 54 #define DCFESR_CX_EMP (1 << 5) 55 #define DCFESR_CX_CLR (1 << 3) 56 #define DCFESR_CX_STL (1 << 2) 57 #define DCFESR_TST_PKDONE (1 << 1) 58 #define DCFESR_CX_DONE (1 << 0) 59 60 /* Device IDLE Counter Register(0x124) */ 61 #define FOTG210_DICR 0x124 62 63 /* Device Mask of Interrupt Group Register (0x130) */ 64 #define FOTG210_DMIGR 0x130 65 #define DMIGR_MINT_G0 (1 << 0) 66 67 /* Device Mask of Interrupt Source Group 0(0x134) */ 68 #define FOTG210_DMISGR0 0x134 69 #define DMISGR0_MCX_COMEND (1 << 3) 70 #define DMISGR0_MCX_OUT_INT (1 << 2) 71 #define DMISGR0_MCX_IN_INT (1 << 1) 72 #define DMISGR0_MCX_SETUP_INT (1 << 0) 73 74 /* Device Mask of Interrupt Source Group 1 Register(0x138)*/ 75 #define FOTG210_DMISGR1 0x138 76 #define DMISGR1_MF3_IN_INT (1 << 19) 77 #define DMISGR1_MF2_IN_INT (1 << 18) 78 #define DMISGR1_MF1_IN_INT (1 << 17) 79 #define DMISGR1_MF0_IN_INT (1 << 16) 80 #define DMISGR1_MF_IN_INT(fifo) (1 << (16 + (fifo))) 81 #define DMISGR1_MF3_SPK_INT (1 << 7) 82 #define DMISGR1_MF3_OUT_INT (1 << 6) 83 #define DMISGR1_MF2_SPK_INT (1 << 5) 84 #define DMISGR1_MF2_OUT_INT (1 << 4) 85 #define DMISGR1_MF1_SPK_INT (1 << 3) 86 #define DMISGR1_MF1_OUT_INT (1 << 2) 87 #define DMISGR1_MF0_SPK_INT (1 << 1) 88 #define DMISGR1_MF0_OUT_INT (1 << 0) 89 #define DMISGR1_MF_OUTSPK_INT(fifo) (0x3 << (fifo) * 2) 90 91 /* Device Mask of Interrupt Source Group 2 Register (0x13C) */ 92 #define FOTG210_DMISGR2 0x13C 93 #define DMISGR2_MDMA_ERROR (1 << 8) 94 #define DMISGR2_MDMA_CMPLT (1 << 7) 95 96 /* Device Interrupt group Register (0x140) */ 97 #define FOTG210_DIGR 0x140 98 #define DIGR_INT_G2 (1 << 2) 99 #define DIGR_INT_G1 (1 << 1) 100 #define DIGR_INT_G0 (1 << 0) 101 102 /* Device Interrupt Source Group 0 Register (0x144) */ 103 #define FOTG210_DISGR0 0x144 104 #define DISGR0_CX_COMABT_INT (1 << 5) 105 #define DISGR0_CX_COMFAIL_INT (1 << 4) 106 #define DISGR0_CX_COMEND_INT (1 << 3) 107 #define DISGR0_CX_OUT_INT (1 << 2) 108 #define DISGR0_CX_IN_INT (1 << 1) 109 #define DISGR0_CX_SETUP_INT (1 << 0) 110 111 /* Device Interrupt Source Group 1 Register (0x148) */ 112 #define FOTG210_DISGR1 0x148 113 #define DISGR1_OUT_INT(fifo) (1 << ((fifo) * 2)) 114 #define DISGR1_SPK_INT(fifo) (1 << 1 << ((fifo) * 2)) 115 #define DISGR1_IN_INT(fifo) (1 << 16 << (fifo)) 116 117 /* Device Interrupt Source Group 2 Register (0x14C) */ 118 #define FOTG210_DISGR2 0x14C 119 #define DISGR2_DMA_ERROR (1 << 8) 120 #define DISGR2_DMA_CMPLT (1 << 7) 121 #define DISGR2_RX0BYTE_INT (1 << 6) 122 #define DISGR2_TX0BYTE_INT (1 << 5) 123 #define DISGR2_ISO_SEQ_ABORT_INT (1 << 4) 124 #define DISGR2_ISO_SEQ_ERR_INT (1 << 3) 125 #define DISGR2_RESM_INT (1 << 2) 126 #define DISGR2_SUSP_INT (1 << 1) 127 #define DISGR2_USBRST_INT (1 << 0) 128 129 /* Device Receive Zero-Length Data Packet Register (0x150)*/ 130 #define FOTG210_RX0BYTE 0x150 131 #define RX0BYTE_EP8 (1 << 7) 132 #define RX0BYTE_EP7 (1 << 6) 133 #define RX0BYTE_EP6 (1 << 5) 134 #define RX0BYTE_EP5 (1 << 4) 135 #define RX0BYTE_EP4 (1 << 3) 136 #define RX0BYTE_EP3 (1 << 2) 137 #define RX0BYTE_EP2 (1 << 1) 138 #define RX0BYTE_EP1 (1 << 0) 139 140 /* Device Transfer Zero-Length Data Packet Register (0x154)*/ 141 #define FOTG210_TX0BYTE 0x154 142 #define TX0BYTE_EP8 (1 << 7) 143 #define TX0BYTE_EP7 (1 << 6) 144 #define TX0BYTE_EP6 (1 << 5) 145 #define TX0BYTE_EP5 (1 << 4) 146 #define TX0BYTE_EP4 (1 << 3) 147 #define TX0BYTE_EP3 (1 << 2) 148 #define TX0BYTE_EP2 (1 << 1) 149 #define TX0BYTE_EP1 (1 << 0) 150 151 /* Device IN Endpoint x MaxPacketSize Register(0x160+4*(x-1)) */ 152 #define FOTG210_INEPMPSR(ep) (0x160 + 4 * ((ep) - 1)) 153 #define INOUTEPMPSR_MPS(mps) ((mps) & 0x2FF) 154 #define INOUTEPMPSR_STL_EP (1 << 11) 155 #define INOUTEPMPSR_RESET_TSEQ (1 << 12) 156 157 /* Device OUT Endpoint x MaxPacketSize Register(0x180+4*(x-1)) */ 158 #define FOTG210_OUTEPMPSR(ep) (0x180 + 4 * ((ep) - 1)) 159 160 /* Device Endpoint 1~4 Map Register (0x1A0) */ 161 #define FOTG210_EPMAP 0x1A0 162 #define EPMAP_FIFONO(ep, dir) \ 163 ((((ep) - 1) << ((ep) - 1) * 8) << ((dir) ? 0 : 4)) 164 #define EPMAP_FIFONOMSK(ep, dir) \ 165 ((3 << ((ep) - 1) * 8) << ((dir) ? 0 : 4)) 166 167 /* Device FIFO Map Register (0x1A8) */ 168 #define FOTG210_FIFOMAP 0x1A8 169 #define FIFOMAP_DIROUT(fifo) (0x0 << 4 << (fifo) * 8) 170 #define FIFOMAP_DIRIN(fifo) (0x1 << 4 << (fifo) * 8) 171 #define FIFOMAP_BIDIR(fifo) (0x2 << 4 << (fifo) * 8) 172 #define FIFOMAP_NA(fifo) (0x3 << 4 << (fifo) * 8) 173 #define FIFOMAP_EPNO(ep) ((ep) << ((ep) - 1) * 8) 174 #define FIFOMAP_EPNOMSK(ep) (0xF << ((ep) - 1) * 8) 175 176 /* Device FIFO Confuguration Register (0x1AC) */ 177 #define FOTG210_FIFOCF 0x1AC 178 #define FIFOCF_TYPE(type, fifo) ((type) << (fifo) * 8) 179 #define FIFOCF_BLK_SIN(fifo) (0x0 << (fifo) * 8 << 2) 180 #define FIFOCF_BLK_DUB(fifo) (0x1 << (fifo) * 8 << 2) 181 #define FIFOCF_BLK_TRI(fifo) (0x2 << (fifo) * 8 << 2) 182 #define FIFOCF_BLKSZ_512(fifo) (0x0 << (fifo) * 8 << 4) 183 #define FIFOCF_BLKSZ_1024(fifo) (0x1 << (fifo) * 8 << 4) 184 #define FIFOCF_FIFO_EN(fifo) (0x1 << (fifo) * 8 << 5) 185 186 /* Device FIFO n Instruction and Byte Count Register (0x1B0+4*n) */ 187 #define FOTG210_FIBCR(fifo) (0x1B0 + (fifo) * 4) 188 #define FIBCR_BCFX 0x7FF 189 #define FIBCR_FFRST (1 << 12) 190 191 /* Device DMA Target FIFO Number Register (0x1C0) */ 192 #define FOTG210_DMATFNR 0x1C0 193 #define DMATFNR_ACC_CXF (1 << 4) 194 #define DMATFNR_ACC_F3 (1 << 3) 195 #define DMATFNR_ACC_F2 (1 << 2) 196 #define DMATFNR_ACC_F1 (1 << 1) 197 #define DMATFNR_ACC_F0 (1 << 0) 198 #define DMATFNR_ACC_FN(fifo) (1 << (fifo)) 199 #define DMATFNR_DISDMA 0 200 201 /* Device DMA Controller Parameter setting 1 Register (0x1C8) */ 202 #define FOTG210_DMACPSR1 0x1C8 203 #define DMACPSR1_DMA_LEN(len) (((len) & 0xFFFF) << 8) 204 #define DMACPSR1_DMA_ABORT (1 << 3) 205 #define DMACPSR1_DMA_TYPE(dir_in) (((dir_in) ? 1 : 0) << 1) 206 #define DMACPSR1_DMA_START (1 << 0) 207 208 /* Device DMA Controller Parameter setting 2 Register (0x1CC) */ 209 #define FOTG210_DMACPSR2 0x1CC 210 211 /* Device DMA Controller Parameter setting 3 Register (0x1CC) */ 212 #define FOTG210_CXPORT 0x1D0 213 214 struct fotg210_request { 215 struct usb_request req; 216 struct list_head queue; 217 }; 218 219 struct fotg210_ep { 220 struct usb_ep ep; 221 struct fotg210_udc *fotg210; 222 223 struct list_head queue; 224 unsigned stall:1; 225 unsigned wedged:1; 226 unsigned use_dma:1; 227 228 unsigned char epnum; 229 unsigned char type; 230 unsigned char dir_in; 231 unsigned int maxp; 232 const struct usb_endpoint_descriptor *desc; 233 }; 234 235 struct fotg210_udc { 236 spinlock_t lock; /* protect the struct */ 237 void __iomem *reg; 238 239 unsigned long irq_trigger; 240 241 struct usb_gadget gadget; 242 struct usb_gadget_driver *driver; 243 244 struct fotg210_ep *ep[FOTG210_MAX_NUM_EP]; 245 246 struct usb_request *ep0_req; /* for internal request */ 247 __le16 ep0_data; 248 u8 ep0_dir; /* 0/0x80 out/in */ 249 250 u8 reenum; /* if re-enumeration */ 251 }; 252 253 #define gadget_to_fotg210(g) container_of((g), struct fotg210_udc, gadget) 254