1 /*
2 * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * Author: Li Yang <leoli@freescale.com>
6 * Jiang Bo <tanya.jiang@freescale.com>
7 *
8 * Description:
9 * Freescale high-speed USB SOC DR module device controller driver.
10 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
11 * The driver is previously named as mpc_udc. Based on bare board
12 * code from Dave Liu and Shlomi Gridish.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19
20 #undef VERBOSE
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/ioport.h>
25 #include <linux/types.h>
26 #include <linux/errno.h>
27 #include <linux/err.h>
28 #include <linux/slab.h>
29 #include <linux/init.h>
30 #include <linux/list.h>
31 #include <linux/interrupt.h>
32 #include <linux/proc_fs.h>
33 #include <linux/mm.h>
34 #include <linux/moduleparam.h>
35 #include <linux/device.h>
36 #include <linux/usb/ch9.h>
37 #include <linux/usb/gadget.h>
38 #include <linux/usb/otg.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/platform_device.h>
41 #include <linux/fsl_devices.h>
42 #include <linux/dmapool.h>
43 #include <linux/delay.h>
44 #include <linux/of_device.h>
45
46 #include <asm/byteorder.h>
47 #include <asm/io.h>
48 #include <asm/unaligned.h>
49 #include <asm/dma.h>
50
51 #include "fsl_usb2_udc.h"
52
53 #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
54 #define DRIVER_AUTHOR "Li Yang/Jiang Bo"
55 #define DRIVER_VERSION "Apr 20, 2007"
56
57 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
58
59 static const char driver_name[] = "fsl-usb2-udc";
60 static const char driver_desc[] = DRIVER_DESC;
61
62 static struct usb_dr_device __iomem *dr_regs;
63
64 static struct usb_sys_interface __iomem *usb_sys_regs;
65
66 /* it is initialized in probe() */
67 static struct fsl_udc *udc_controller = NULL;
68
69 static const struct usb_endpoint_descriptor
70 fsl_ep0_desc = {
71 .bLength = USB_DT_ENDPOINT_SIZE,
72 .bDescriptorType = USB_DT_ENDPOINT,
73 .bEndpointAddress = 0,
74 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
75 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
76 };
77
78 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
79
80 #ifdef CONFIG_PPC32
81 /*
82 * On some SoCs, the USB controller registers can be big or little endian,
83 * depending on the version of the chip. In order to be able to run the
84 * same kernel binary on 2 different versions of an SoC, the BE/LE decision
85 * must be made at run time. _fsl_readl and fsl_writel are pointers to the
86 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
87 * call through those pointers. Platform code for SoCs that have BE USB
88 * registers should set pdata->big_endian_mmio flag.
89 *
90 * This also applies to controller-to-cpu accessors for the USB descriptors,
91 * since their endianness is also SoC dependant. Platform code for SoCs that
92 * have BE USB descriptors should set pdata->big_endian_desc flag.
93 */
_fsl_readl_be(const unsigned __iomem * p)94 static u32 _fsl_readl_be(const unsigned __iomem *p)
95 {
96 return in_be32(p);
97 }
98
_fsl_readl_le(const unsigned __iomem * p)99 static u32 _fsl_readl_le(const unsigned __iomem *p)
100 {
101 return in_le32(p);
102 }
103
_fsl_writel_be(u32 v,unsigned __iomem * p)104 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
105 {
106 out_be32(p, v);
107 }
108
_fsl_writel_le(u32 v,unsigned __iomem * p)109 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
110 {
111 out_le32(p, v);
112 }
113
114 static u32 (*_fsl_readl)(const unsigned __iomem *p);
115 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
116
117 #define fsl_readl(p) (*_fsl_readl)((p))
118 #define fsl_writel(v, p) (*_fsl_writel)((v), (p))
119
fsl_set_accessors(struct fsl_usb2_platform_data * pdata)120 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
121 {
122 if (pdata->big_endian_mmio) {
123 _fsl_readl = _fsl_readl_be;
124 _fsl_writel = _fsl_writel_be;
125 } else {
126 _fsl_readl = _fsl_readl_le;
127 _fsl_writel = _fsl_writel_le;
128 }
129 }
130
cpu_to_hc32(const u32 x)131 static inline u32 cpu_to_hc32(const u32 x)
132 {
133 return udc_controller->pdata->big_endian_desc
134 ? (__force u32)cpu_to_be32(x)
135 : (__force u32)cpu_to_le32(x);
136 }
137
hc32_to_cpu(const u32 x)138 static inline u32 hc32_to_cpu(const u32 x)
139 {
140 return udc_controller->pdata->big_endian_desc
141 ? be32_to_cpu((__force __be32)x)
142 : le32_to_cpu((__force __le32)x);
143 }
144 #else /* !CONFIG_PPC32 */
fsl_set_accessors(struct fsl_usb2_platform_data * pdata)145 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
146
147 #define fsl_readl(addr) readl(addr)
148 #define fsl_writel(val32, addr) writel(val32, addr)
149 #define cpu_to_hc32(x) cpu_to_le32(x)
150 #define hc32_to_cpu(x) le32_to_cpu(x)
151 #endif /* CONFIG_PPC32 */
152
153 /********************************************************************
154 * Internal Used Function
155 ********************************************************************/
156 /*-----------------------------------------------------------------
157 * done() - retire a request; caller blocked irqs
158 * @status : request status to be set, only works when
159 * request is still in progress.
160 *--------------------------------------------------------------*/
done(struct fsl_ep * ep,struct fsl_req * req,int status)161 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
162 __releases(ep->udc->lock)
163 __acquires(ep->udc->lock)
164 {
165 struct fsl_udc *udc = NULL;
166 unsigned char stopped = ep->stopped;
167 struct ep_td_struct *curr_td, *next_td;
168 int j;
169
170 udc = (struct fsl_udc *)ep->udc;
171 /* Removed the req from fsl_ep->queue */
172 list_del_init(&req->queue);
173
174 /* req.status should be set as -EINPROGRESS in ep_queue() */
175 if (req->req.status == -EINPROGRESS)
176 req->req.status = status;
177 else
178 status = req->req.status;
179
180 /* Free dtd for the request */
181 next_td = req->head;
182 for (j = 0; j < req->dtd_count; j++) {
183 curr_td = next_td;
184 if (j != req->dtd_count - 1) {
185 next_td = curr_td->next_td_virt;
186 }
187 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
188 }
189
190 usb_gadget_unmap_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
191
192 if (status && (status != -ESHUTDOWN))
193 VDBG("complete %s req %p stat %d len %u/%u",
194 ep->ep.name, &req->req, status,
195 req->req.actual, req->req.length);
196
197 ep->stopped = 1;
198
199 spin_unlock(&ep->udc->lock);
200
201 usb_gadget_giveback_request(&ep->ep, &req->req);
202
203 spin_lock(&ep->udc->lock);
204 ep->stopped = stopped;
205 }
206
207 /*-----------------------------------------------------------------
208 * nuke(): delete all requests related to this ep
209 * called with spinlock held
210 *--------------------------------------------------------------*/
nuke(struct fsl_ep * ep,int status)211 static void nuke(struct fsl_ep *ep, int status)
212 {
213 ep->stopped = 1;
214
215 /* Flush fifo */
216 fsl_ep_fifo_flush(&ep->ep);
217
218 /* Whether this eq has request linked */
219 while (!list_empty(&ep->queue)) {
220 struct fsl_req *req = NULL;
221
222 req = list_entry(ep->queue.next, struct fsl_req, queue);
223 done(ep, req, status);
224 }
225 }
226
227 /*------------------------------------------------------------------
228 Internal Hardware related function
229 ------------------------------------------------------------------*/
230
dr_controller_setup(struct fsl_udc * udc)231 static int dr_controller_setup(struct fsl_udc *udc)
232 {
233 unsigned int tmp, portctrl, ep_num;
234 unsigned int max_no_of_ep;
235 unsigned int ctrl;
236 unsigned long timeout;
237
238 #define FSL_UDC_RESET_TIMEOUT 1000
239
240 /* Config PHY interface */
241 portctrl = fsl_readl(&dr_regs->portsc1);
242 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
243 switch (udc->phy_mode) {
244 case FSL_USB2_PHY_ULPI:
245 if (udc->pdata->have_sysif_regs) {
246 if (udc->pdata->controller_ver) {
247 /* controller version 1.6 or above */
248 ctrl = __raw_readl(&usb_sys_regs->control);
249 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
250 ctrl |= USB_CTRL_USB_EN;
251 __raw_writel(ctrl, &usb_sys_regs->control);
252 }
253 }
254 portctrl |= PORTSCX_PTS_ULPI;
255 break;
256 case FSL_USB2_PHY_UTMI_WIDE:
257 portctrl |= PORTSCX_PTW_16BIT;
258 /* fall through */
259 case FSL_USB2_PHY_UTMI:
260 if (udc->pdata->have_sysif_regs) {
261 if (udc->pdata->controller_ver) {
262 /* controller version 1.6 or above */
263 ctrl = __raw_readl(&usb_sys_regs->control);
264 ctrl |= (USB_CTRL_UTMI_PHY_EN |
265 USB_CTRL_USB_EN);
266 __raw_writel(ctrl, &usb_sys_regs->control);
267 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
268 PHY CLK to become stable - 10ms*/
269 }
270 }
271 portctrl |= PORTSCX_PTS_UTMI;
272 break;
273 case FSL_USB2_PHY_SERIAL:
274 portctrl |= PORTSCX_PTS_FSLS;
275 break;
276 default:
277 return -EINVAL;
278 }
279 fsl_writel(portctrl, &dr_regs->portsc1);
280
281 /* Stop and reset the usb controller */
282 tmp = fsl_readl(&dr_regs->usbcmd);
283 tmp &= ~USB_CMD_RUN_STOP;
284 fsl_writel(tmp, &dr_regs->usbcmd);
285
286 tmp = fsl_readl(&dr_regs->usbcmd);
287 tmp |= USB_CMD_CTRL_RESET;
288 fsl_writel(tmp, &dr_regs->usbcmd);
289
290 /* Wait for reset to complete */
291 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
292 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
293 if (time_after(jiffies, timeout)) {
294 ERR("udc reset timeout!\n");
295 return -ETIMEDOUT;
296 }
297 cpu_relax();
298 }
299
300 /* Set the controller as device mode */
301 tmp = fsl_readl(&dr_regs->usbmode);
302 tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
303 tmp |= USB_MODE_CTRL_MODE_DEVICE;
304 /* Disable Setup Lockout */
305 tmp |= USB_MODE_SETUP_LOCK_OFF;
306 if (udc->pdata->es)
307 tmp |= USB_MODE_ES;
308 fsl_writel(tmp, &dr_regs->usbmode);
309
310 /* Clear the setup status */
311 fsl_writel(0, &dr_regs->usbsts);
312
313 tmp = udc->ep_qh_dma;
314 tmp &= USB_EP_LIST_ADDRESS_MASK;
315 fsl_writel(tmp, &dr_regs->endpointlistaddr);
316
317 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
318 udc->ep_qh, (int)tmp,
319 fsl_readl(&dr_regs->endpointlistaddr));
320
321 max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
322 for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
323 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
324 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
325 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
326 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
327 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
328 }
329 /* Config control enable i/o output, cpu endian register */
330 #ifndef CONFIG_ARCH_MXC
331 if (udc->pdata->have_sysif_regs) {
332 ctrl = __raw_readl(&usb_sys_regs->control);
333 ctrl |= USB_CTRL_IOENB;
334 __raw_writel(ctrl, &usb_sys_regs->control);
335 }
336 #endif
337
338 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
339 /* Turn on cache snooping hardware, since some PowerPC platforms
340 * wholly rely on hardware to deal with cache coherent. */
341
342 if (udc->pdata->have_sysif_regs) {
343 /* Setup Snooping for all the 4GB space */
344 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
345 __raw_writel(tmp, &usb_sys_regs->snoop1);
346 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
347 __raw_writel(tmp, &usb_sys_regs->snoop2);
348 }
349 #endif
350
351 return 0;
352 }
353
354 /* Enable DR irq and set controller to run state */
dr_controller_run(struct fsl_udc * udc)355 static void dr_controller_run(struct fsl_udc *udc)
356 {
357 u32 temp;
358
359 /* Enable DR irq reg */
360 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
361 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
362 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
363
364 fsl_writel(temp, &dr_regs->usbintr);
365
366 /* Clear stopped bit */
367 udc->stopped = 0;
368
369 /* Set the controller as device mode */
370 temp = fsl_readl(&dr_regs->usbmode);
371 temp |= USB_MODE_CTRL_MODE_DEVICE;
372 fsl_writel(temp, &dr_regs->usbmode);
373
374 /* Set controller to Run */
375 temp = fsl_readl(&dr_regs->usbcmd);
376 temp |= USB_CMD_RUN_STOP;
377 fsl_writel(temp, &dr_regs->usbcmd);
378 }
379
dr_controller_stop(struct fsl_udc * udc)380 static void dr_controller_stop(struct fsl_udc *udc)
381 {
382 unsigned int tmp;
383
384 pr_debug("%s\n", __func__);
385
386 /* if we're in OTG mode, and the Host is currently using the port,
387 * stop now and don't rip the controller out from under the
388 * ehci driver
389 */
390 if (udc->gadget.is_otg) {
391 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
392 pr_debug("udc: Leaving early\n");
393 return;
394 }
395 }
396
397 /* disable all INTR */
398 fsl_writel(0, &dr_regs->usbintr);
399
400 /* Set stopped bit for isr */
401 udc->stopped = 1;
402
403 /* disable IO output */
404 /* usb_sys_regs->control = 0; */
405
406 /* set controller to Stop */
407 tmp = fsl_readl(&dr_regs->usbcmd);
408 tmp &= ~USB_CMD_RUN_STOP;
409 fsl_writel(tmp, &dr_regs->usbcmd);
410 }
411
dr_ep_setup(unsigned char ep_num,unsigned char dir,unsigned char ep_type)412 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
413 unsigned char ep_type)
414 {
415 unsigned int tmp_epctrl = 0;
416
417 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
418 if (dir) {
419 if (ep_num)
420 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
421 tmp_epctrl |= EPCTRL_TX_ENABLE;
422 tmp_epctrl &= ~EPCTRL_TX_TYPE;
423 tmp_epctrl |= ((unsigned int)(ep_type)
424 << EPCTRL_TX_EP_TYPE_SHIFT);
425 } else {
426 if (ep_num)
427 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
428 tmp_epctrl |= EPCTRL_RX_ENABLE;
429 tmp_epctrl &= ~EPCTRL_RX_TYPE;
430 tmp_epctrl |= ((unsigned int)(ep_type)
431 << EPCTRL_RX_EP_TYPE_SHIFT);
432 }
433
434 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
435 }
436
437 static void
dr_ep_change_stall(unsigned char ep_num,unsigned char dir,int value)438 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
439 {
440 u32 tmp_epctrl = 0;
441
442 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
443
444 if (value) {
445 /* set the stall bit */
446 if (dir)
447 tmp_epctrl |= EPCTRL_TX_EP_STALL;
448 else
449 tmp_epctrl |= EPCTRL_RX_EP_STALL;
450 } else {
451 /* clear the stall bit and reset data toggle */
452 if (dir) {
453 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
454 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
455 } else {
456 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
457 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
458 }
459 }
460 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
461 }
462
463 /* Get stall status of a specific ep
464 Return: 0: not stalled; 1:stalled */
dr_ep_get_stall(unsigned char ep_num,unsigned char dir)465 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
466 {
467 u32 epctrl;
468
469 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
470 if (dir)
471 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
472 else
473 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
474 }
475
476 /********************************************************************
477 Internal Structure Build up functions
478 ********************************************************************/
479
480 /*------------------------------------------------------------------
481 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
482 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
483 * @mult: Mult field
484 ------------------------------------------------------------------*/
struct_ep_qh_setup(struct fsl_udc * udc,unsigned char ep_num,unsigned char dir,unsigned char ep_type,unsigned int max_pkt_len,unsigned int zlt,unsigned char mult)485 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
486 unsigned char dir, unsigned char ep_type,
487 unsigned int max_pkt_len,
488 unsigned int zlt, unsigned char mult)
489 {
490 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
491 unsigned int tmp = 0;
492
493 /* set the Endpoint Capabilites in QH */
494 switch (ep_type) {
495 case USB_ENDPOINT_XFER_CONTROL:
496 /* Interrupt On Setup (IOS). for control ep */
497 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
498 | EP_QUEUE_HEAD_IOS;
499 break;
500 case USB_ENDPOINT_XFER_ISOC:
501 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
502 | (mult << EP_QUEUE_HEAD_MULT_POS);
503 break;
504 case USB_ENDPOINT_XFER_BULK:
505 case USB_ENDPOINT_XFER_INT:
506 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
507 break;
508 default:
509 VDBG("error ep type is %d", ep_type);
510 return;
511 }
512 if (zlt)
513 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
514
515 p_QH->max_pkt_length = cpu_to_hc32(tmp);
516 p_QH->next_dtd_ptr = 1;
517 p_QH->size_ioc_int_sts = 0;
518 }
519
520 /* Setup qh structure and ep register for ep0. */
ep0_setup(struct fsl_udc * udc)521 static void ep0_setup(struct fsl_udc *udc)
522 {
523 /* the initialization of an ep includes: fields in QH, Regs,
524 * fsl_ep struct */
525 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
526 USB_MAX_CTRL_PAYLOAD, 0, 0);
527 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
528 USB_MAX_CTRL_PAYLOAD, 0, 0);
529 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
530 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
531
532 return;
533
534 }
535
536 /***********************************************************************
537 Endpoint Management Functions
538 ***********************************************************************/
539
540 /*-------------------------------------------------------------------------
541 * when configurations are set, or when interface settings change
542 * for example the do_set_interface() in gadget layer,
543 * the driver will enable or disable the relevant endpoints
544 * ep0 doesn't use this routine. It is always enabled.
545 -------------------------------------------------------------------------*/
fsl_ep_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)546 static int fsl_ep_enable(struct usb_ep *_ep,
547 const struct usb_endpoint_descriptor *desc)
548 {
549 struct fsl_udc *udc = NULL;
550 struct fsl_ep *ep = NULL;
551 unsigned short max = 0;
552 unsigned char mult = 0, zlt;
553 int retval = -EINVAL;
554 unsigned long flags = 0;
555
556 ep = container_of(_ep, struct fsl_ep, ep);
557
558 /* catch various bogus parameters */
559 if (!_ep || !desc
560 || (desc->bDescriptorType != USB_DT_ENDPOINT))
561 return -EINVAL;
562
563 udc = ep->udc;
564
565 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
566 return -ESHUTDOWN;
567
568 max = usb_endpoint_maxp(desc);
569
570 /* Disable automatic zlp generation. Driver is responsible to indicate
571 * explicitly through req->req.zero. This is needed to enable multi-td
572 * request. */
573 zlt = 1;
574
575 /* Assume the max packet size from gadget is always correct */
576 switch (desc->bmAttributes & 0x03) {
577 case USB_ENDPOINT_XFER_CONTROL:
578 case USB_ENDPOINT_XFER_BULK:
579 case USB_ENDPOINT_XFER_INT:
580 /* mult = 0. Execute N Transactions as demonstrated by
581 * the USB variable length packet protocol where N is
582 * computed using the Maximum Packet Length (dQH) and
583 * the Total Bytes field (dTD) */
584 mult = 0;
585 break;
586 case USB_ENDPOINT_XFER_ISOC:
587 /* Calculate transactions needed for high bandwidth iso */
588 mult = usb_endpoint_maxp_mult(desc);
589 /* 3 transactions at most */
590 if (mult > 3)
591 goto en_done;
592 break;
593 default:
594 goto en_done;
595 }
596
597 spin_lock_irqsave(&udc->lock, flags);
598 ep->ep.maxpacket = max;
599 ep->ep.desc = desc;
600 ep->stopped = 0;
601
602 /* Controller related setup */
603 /* Init EPx Queue Head (Ep Capabilites field in QH
604 * according to max, zlt, mult) */
605 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
606 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
607 ? USB_SEND : USB_RECV),
608 (unsigned char) (desc->bmAttributes
609 & USB_ENDPOINT_XFERTYPE_MASK),
610 max, zlt, mult);
611
612 /* Init endpoint ctrl register */
613 dr_ep_setup((unsigned char) ep_index(ep),
614 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
615 ? USB_SEND : USB_RECV),
616 (unsigned char) (desc->bmAttributes
617 & USB_ENDPOINT_XFERTYPE_MASK));
618
619 spin_unlock_irqrestore(&udc->lock, flags);
620 retval = 0;
621
622 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
623 ep->ep.desc->bEndpointAddress & 0x0f,
624 (desc->bEndpointAddress & USB_DIR_IN)
625 ? "in" : "out", max);
626 en_done:
627 return retval;
628 }
629
630 /*---------------------------------------------------------------------
631 * @ep : the ep being unconfigured. May not be ep0
632 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
633 *---------------------------------------------------------------------*/
fsl_ep_disable(struct usb_ep * _ep)634 static int fsl_ep_disable(struct usb_ep *_ep)
635 {
636 struct fsl_udc *udc = NULL;
637 struct fsl_ep *ep = NULL;
638 unsigned long flags = 0;
639 u32 epctrl;
640 int ep_num;
641
642 ep = container_of(_ep, struct fsl_ep, ep);
643 if (!_ep || !ep->ep.desc) {
644 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
645 return -EINVAL;
646 }
647
648 /* disable ep on controller */
649 ep_num = ep_index(ep);
650 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
651 if (ep_is_in(ep)) {
652 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
653 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
654 } else {
655 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
656 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
657 }
658 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
659
660 udc = (struct fsl_udc *)ep->udc;
661 spin_lock_irqsave(&udc->lock, flags);
662
663 /* nuke all pending requests (does flush) */
664 nuke(ep, -ESHUTDOWN);
665
666 ep->ep.desc = NULL;
667 ep->stopped = 1;
668 spin_unlock_irqrestore(&udc->lock, flags);
669
670 VDBG("disabled %s OK", _ep->name);
671 return 0;
672 }
673
674 /*---------------------------------------------------------------------
675 * allocate a request object used by this endpoint
676 * the main operation is to insert the req->queue to the eq->queue
677 * Returns the request, or null if one could not be allocated
678 *---------------------------------------------------------------------*/
679 static struct usb_request *
fsl_alloc_request(struct usb_ep * _ep,gfp_t gfp_flags)680 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
681 {
682 struct fsl_req *req = NULL;
683
684 req = kzalloc(sizeof *req, gfp_flags);
685 if (!req)
686 return NULL;
687
688 req->req.dma = DMA_ADDR_INVALID;
689 INIT_LIST_HEAD(&req->queue);
690
691 return &req->req;
692 }
693
fsl_free_request(struct usb_ep * _ep,struct usb_request * _req)694 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
695 {
696 struct fsl_req *req = NULL;
697
698 req = container_of(_req, struct fsl_req, req);
699
700 if (_req)
701 kfree(req);
702 }
703
704 /* Actually add a dTD chain to an empty dQH and let go */
fsl_prime_ep(struct fsl_ep * ep,struct ep_td_struct * td)705 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
706 {
707 struct ep_queue_head *qh = get_qh_by_ep(ep);
708
709 /* Write dQH next pointer and terminate bit to 0 */
710 qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
711 & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
712
713 /* Clear active and halt bit */
714 qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
715 | EP_QUEUE_HEAD_STATUS_HALT));
716
717 /* Ensure that updates to the QH will occur before priming. */
718 wmb();
719
720 /* Prime endpoint by writing correct bit to ENDPTPRIME */
721 fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
722 : (1 << (ep_index(ep))), &dr_regs->endpointprime);
723 }
724
725 /* Add dTD chain to the dQH of an EP */
fsl_queue_td(struct fsl_ep * ep,struct fsl_req * req)726 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
727 {
728 u32 temp, bitmask, tmp_stat;
729
730 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
731 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
732
733 bitmask = ep_is_in(ep)
734 ? (1 << (ep_index(ep) + 16))
735 : (1 << (ep_index(ep)));
736
737 /* check if the pipe is empty */
738 if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
739 /* Add td to the end */
740 struct fsl_req *lastreq;
741 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
742 lastreq->tail->next_td_ptr =
743 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
744 /* Ensure dTD's next dtd pointer to be updated */
745 wmb();
746 /* Read prime bit, if 1 goto done */
747 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
748 return;
749
750 do {
751 /* Set ATDTW bit in USBCMD */
752 temp = fsl_readl(&dr_regs->usbcmd);
753 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
754
755 /* Read correct status bit */
756 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
757
758 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
759
760 /* Write ATDTW bit to 0 */
761 temp = fsl_readl(&dr_regs->usbcmd);
762 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
763
764 if (tmp_stat)
765 return;
766 }
767
768 fsl_prime_ep(ep, req->head);
769 }
770
771 /* Fill in the dTD structure
772 * @req: request that the transfer belongs to
773 * @length: return actually data length of the dTD
774 * @dma: return dma address of the dTD
775 * @is_last: return flag if it is the last dTD of the request
776 * return: pointer to the built dTD */
fsl_build_dtd(struct fsl_req * req,unsigned * length,dma_addr_t * dma,int * is_last,gfp_t gfp_flags)777 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
778 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
779 {
780 u32 swap_temp;
781 struct ep_td_struct *dtd;
782
783 /* how big will this transfer be? */
784 *length = min(req->req.length - req->req.actual,
785 (unsigned)EP_MAX_LENGTH_TRANSFER);
786
787 dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
788 if (dtd == NULL)
789 return dtd;
790
791 dtd->td_dma = *dma;
792 /* Clear reserved field */
793 swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
794 swap_temp &= ~DTD_RESERVED_FIELDS;
795 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
796
797 /* Init all of buffer page pointers */
798 swap_temp = (u32) (req->req.dma + req->req.actual);
799 dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
800 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
801 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
802 dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
803 dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
804
805 req->req.actual += *length;
806
807 /* zlp is needed if req->req.zero is set */
808 if (req->req.zero) {
809 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
810 *is_last = 1;
811 else
812 *is_last = 0;
813 } else if (req->req.length == req->req.actual)
814 *is_last = 1;
815 else
816 *is_last = 0;
817
818 if ((*is_last) == 0)
819 VDBG("multi-dtd request!");
820 /* Fill in the transfer size; set active bit */
821 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
822
823 /* Enable interrupt for the last dtd of a request */
824 if (*is_last && !req->req.no_interrupt)
825 swap_temp |= DTD_IOC;
826
827 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
828
829 mb();
830
831 VDBG("length = %d address= 0x%x", *length, (int)*dma);
832
833 return dtd;
834 }
835
836 /* Generate dtd chain for a request */
fsl_req_to_dtd(struct fsl_req * req,gfp_t gfp_flags)837 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
838 {
839 unsigned count;
840 int is_last;
841 int is_first =1;
842 struct ep_td_struct *last_dtd = NULL, *dtd;
843 dma_addr_t dma;
844
845 do {
846 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
847 if (dtd == NULL)
848 return -ENOMEM;
849
850 if (is_first) {
851 is_first = 0;
852 req->head = dtd;
853 } else {
854 last_dtd->next_td_ptr = cpu_to_hc32(dma);
855 last_dtd->next_td_virt = dtd;
856 }
857 last_dtd = dtd;
858
859 req->dtd_count++;
860 } while (!is_last);
861
862 dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
863
864 req->tail = dtd;
865
866 return 0;
867 }
868
869 /* queues (submits) an I/O request to an endpoint */
870 static int
fsl_ep_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)871 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
872 {
873 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
874 struct fsl_req *req = container_of(_req, struct fsl_req, req);
875 struct fsl_udc *udc;
876 unsigned long flags;
877 int ret;
878
879 /* catch various bogus parameters */
880 if (!_req || !req->req.complete || !req->req.buf
881 || !list_empty(&req->queue)) {
882 VDBG("%s, bad params", __func__);
883 return -EINVAL;
884 }
885 if (unlikely(!_ep || !ep->ep.desc)) {
886 VDBG("%s, bad ep", __func__);
887 return -EINVAL;
888 }
889 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
890 if (req->req.length > ep->ep.maxpacket)
891 return -EMSGSIZE;
892 }
893
894 udc = ep->udc;
895 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
896 return -ESHUTDOWN;
897
898 req->ep = ep;
899
900 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
901 if (ret)
902 return ret;
903
904 req->req.status = -EINPROGRESS;
905 req->req.actual = 0;
906 req->dtd_count = 0;
907
908 /* build dtds and push them to device queue */
909 if (!fsl_req_to_dtd(req, gfp_flags)) {
910 spin_lock_irqsave(&udc->lock, flags);
911 fsl_queue_td(ep, req);
912 } else {
913 return -ENOMEM;
914 }
915
916 /* irq handler advances the queue */
917 if (req != NULL)
918 list_add_tail(&req->queue, &ep->queue);
919 spin_unlock_irqrestore(&udc->lock, flags);
920
921 return 0;
922 }
923
924 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
fsl_ep_dequeue(struct usb_ep * _ep,struct usb_request * _req)925 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
926 {
927 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
928 struct fsl_req *req;
929 unsigned long flags;
930 int ep_num, stopped, ret = 0;
931 u32 epctrl;
932
933 if (!_ep || !_req)
934 return -EINVAL;
935
936 spin_lock_irqsave(&ep->udc->lock, flags);
937 stopped = ep->stopped;
938
939 /* Stop the ep before we deal with the queue */
940 ep->stopped = 1;
941 ep_num = ep_index(ep);
942 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
943 if (ep_is_in(ep))
944 epctrl &= ~EPCTRL_TX_ENABLE;
945 else
946 epctrl &= ~EPCTRL_RX_ENABLE;
947 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
948
949 /* make sure it's actually queued on this endpoint */
950 list_for_each_entry(req, &ep->queue, queue) {
951 if (&req->req == _req)
952 break;
953 }
954 if (&req->req != _req) {
955 ret = -EINVAL;
956 goto out;
957 }
958
959 /* The request is in progress, or completed but not dequeued */
960 if (ep->queue.next == &req->queue) {
961 _req->status = -ECONNRESET;
962 fsl_ep_fifo_flush(_ep); /* flush current transfer */
963
964 /* The request isn't the last request in this ep queue */
965 if (req->queue.next != &ep->queue) {
966 struct fsl_req *next_req;
967
968 next_req = list_entry(req->queue.next, struct fsl_req,
969 queue);
970
971 /* prime with dTD of next request */
972 fsl_prime_ep(ep, next_req->head);
973 }
974 /* The request hasn't been processed, patch up the TD chain */
975 } else {
976 struct fsl_req *prev_req;
977
978 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
979 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
980 }
981
982 done(ep, req, -ECONNRESET);
983
984 /* Enable EP */
985 out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
986 if (ep_is_in(ep))
987 epctrl |= EPCTRL_TX_ENABLE;
988 else
989 epctrl |= EPCTRL_RX_ENABLE;
990 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
991 ep->stopped = stopped;
992
993 spin_unlock_irqrestore(&ep->udc->lock, flags);
994 return ret;
995 }
996
997 /*-------------------------------------------------------------------------*/
998
999 /*-----------------------------------------------------------------
1000 * modify the endpoint halt feature
1001 * @ep: the non-isochronous endpoint being stalled
1002 * @value: 1--set halt 0--clear halt
1003 * Returns zero, or a negative error code.
1004 *----------------------------------------------------------------*/
fsl_ep_set_halt(struct usb_ep * _ep,int value)1005 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1006 {
1007 struct fsl_ep *ep = NULL;
1008 unsigned long flags = 0;
1009 int status = -EOPNOTSUPP; /* operation not supported */
1010 unsigned char ep_dir = 0, ep_num = 0;
1011 struct fsl_udc *udc = NULL;
1012
1013 ep = container_of(_ep, struct fsl_ep, ep);
1014 udc = ep->udc;
1015 if (!_ep || !ep->ep.desc) {
1016 status = -EINVAL;
1017 goto out;
1018 }
1019
1020 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
1021 status = -EOPNOTSUPP;
1022 goto out;
1023 }
1024
1025 /* Attempt to halt IN ep will fail if any transfer requests
1026 * are still queue */
1027 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1028 status = -EAGAIN;
1029 goto out;
1030 }
1031
1032 status = 0;
1033 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1034 ep_num = (unsigned char)(ep_index(ep));
1035 spin_lock_irqsave(&ep->udc->lock, flags);
1036 dr_ep_change_stall(ep_num, ep_dir, value);
1037 spin_unlock_irqrestore(&ep->udc->lock, flags);
1038
1039 if (ep_index(ep) == 0) {
1040 udc->ep0_state = WAIT_FOR_SETUP;
1041 udc->ep0_dir = 0;
1042 }
1043 out:
1044 VDBG(" %s %s halt stat %d", ep->ep.name,
1045 value ? "set" : "clear", status);
1046
1047 return status;
1048 }
1049
fsl_ep_fifo_status(struct usb_ep * _ep)1050 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1051 {
1052 struct fsl_ep *ep;
1053 struct fsl_udc *udc;
1054 int size = 0;
1055 u32 bitmask;
1056 struct ep_queue_head *qh;
1057
1058 ep = container_of(_ep, struct fsl_ep, ep);
1059 if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
1060 return -ENODEV;
1061
1062 udc = (struct fsl_udc *)ep->udc;
1063
1064 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1065 return -ESHUTDOWN;
1066
1067 qh = get_qh_by_ep(ep);
1068
1069 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1070 (1 << (ep_index(ep)));
1071
1072 if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1073 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1074 >> DTD_LENGTH_BIT_POS;
1075
1076 pr_debug("%s %u\n", __func__, size);
1077 return size;
1078 }
1079
fsl_ep_fifo_flush(struct usb_ep * _ep)1080 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1081 {
1082 struct fsl_ep *ep;
1083 int ep_num, ep_dir;
1084 u32 bits;
1085 unsigned long timeout;
1086 #define FSL_UDC_FLUSH_TIMEOUT 1000
1087
1088 if (!_ep) {
1089 return;
1090 } else {
1091 ep = container_of(_ep, struct fsl_ep, ep);
1092 if (!ep->ep.desc)
1093 return;
1094 }
1095 ep_num = ep_index(ep);
1096 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1097
1098 if (ep_num == 0)
1099 bits = (1 << 16) | 1;
1100 else if (ep_dir == USB_SEND)
1101 bits = 1 << (16 + ep_num);
1102 else
1103 bits = 1 << ep_num;
1104
1105 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1106 do {
1107 fsl_writel(bits, &dr_regs->endptflush);
1108
1109 /* Wait until flush complete */
1110 while (fsl_readl(&dr_regs->endptflush)) {
1111 if (time_after(jiffies, timeout)) {
1112 ERR("ep flush timeout\n");
1113 return;
1114 }
1115 cpu_relax();
1116 }
1117 /* See if we need to flush again */
1118 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1119 }
1120
1121 static const struct usb_ep_ops fsl_ep_ops = {
1122 .enable = fsl_ep_enable,
1123 .disable = fsl_ep_disable,
1124
1125 .alloc_request = fsl_alloc_request,
1126 .free_request = fsl_free_request,
1127
1128 .queue = fsl_ep_queue,
1129 .dequeue = fsl_ep_dequeue,
1130
1131 .set_halt = fsl_ep_set_halt,
1132 .fifo_status = fsl_ep_fifo_status,
1133 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1134 };
1135
1136 /*-------------------------------------------------------------------------
1137 Gadget Driver Layer Operations
1138 -------------------------------------------------------------------------*/
1139
1140 /*----------------------------------------------------------------------
1141 * Get the current frame number (from DR frame_index Reg )
1142 *----------------------------------------------------------------------*/
fsl_get_frame(struct usb_gadget * gadget)1143 static int fsl_get_frame(struct usb_gadget *gadget)
1144 {
1145 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1146 }
1147
1148 /*-----------------------------------------------------------------------
1149 * Tries to wake up the host connected to this gadget
1150 -----------------------------------------------------------------------*/
fsl_wakeup(struct usb_gadget * gadget)1151 static int fsl_wakeup(struct usb_gadget *gadget)
1152 {
1153 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1154 u32 portsc;
1155
1156 /* Remote wakeup feature not enabled by host */
1157 if (!udc->remote_wakeup)
1158 return -ENOTSUPP;
1159
1160 portsc = fsl_readl(&dr_regs->portsc1);
1161 /* not suspended? */
1162 if (!(portsc & PORTSCX_PORT_SUSPEND))
1163 return 0;
1164 /* trigger force resume */
1165 portsc |= PORTSCX_PORT_FORCE_RESUME;
1166 fsl_writel(portsc, &dr_regs->portsc1);
1167 return 0;
1168 }
1169
can_pullup(struct fsl_udc * udc)1170 static int can_pullup(struct fsl_udc *udc)
1171 {
1172 return udc->driver && udc->softconnect && udc->vbus_active;
1173 }
1174
1175 /* Notify controller that VBUS is powered, Called by whatever
1176 detects VBUS sessions */
fsl_vbus_session(struct usb_gadget * gadget,int is_active)1177 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1178 {
1179 struct fsl_udc *udc;
1180 unsigned long flags;
1181
1182 udc = container_of(gadget, struct fsl_udc, gadget);
1183 spin_lock_irqsave(&udc->lock, flags);
1184 VDBG("VBUS %s", is_active ? "on" : "off");
1185 udc->vbus_active = (is_active != 0);
1186 if (can_pullup(udc))
1187 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1188 &dr_regs->usbcmd);
1189 else
1190 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1191 &dr_regs->usbcmd);
1192 spin_unlock_irqrestore(&udc->lock, flags);
1193 return 0;
1194 }
1195
1196 /* constrain controller's VBUS power usage
1197 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1198 * reporting how much power the device may consume. For example, this
1199 * could affect how quickly batteries are recharged.
1200 *
1201 * Returns zero on success, else negative errno.
1202 */
fsl_vbus_draw(struct usb_gadget * gadget,unsigned mA)1203 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1204 {
1205 struct fsl_udc *udc;
1206
1207 udc = container_of(gadget, struct fsl_udc, gadget);
1208 if (!IS_ERR_OR_NULL(udc->transceiver))
1209 return usb_phy_set_power(udc->transceiver, mA);
1210 return -ENOTSUPP;
1211 }
1212
1213 /* Change Data+ pullup status
1214 * this func is used by usb_gadget_connect/disconnet
1215 */
fsl_pullup(struct usb_gadget * gadget,int is_on)1216 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1217 {
1218 struct fsl_udc *udc;
1219
1220 udc = container_of(gadget, struct fsl_udc, gadget);
1221
1222 if (!udc->vbus_active)
1223 return -EOPNOTSUPP;
1224
1225 udc->softconnect = (is_on != 0);
1226 if (can_pullup(udc))
1227 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1228 &dr_regs->usbcmd);
1229 else
1230 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1231 &dr_regs->usbcmd);
1232
1233 return 0;
1234 }
1235
1236 static int fsl_udc_start(struct usb_gadget *g,
1237 struct usb_gadget_driver *driver);
1238 static int fsl_udc_stop(struct usb_gadget *g);
1239
1240 static const struct usb_gadget_ops fsl_gadget_ops = {
1241 .get_frame = fsl_get_frame,
1242 .wakeup = fsl_wakeup,
1243 /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1244 .vbus_session = fsl_vbus_session,
1245 .vbus_draw = fsl_vbus_draw,
1246 .pullup = fsl_pullup,
1247 .udc_start = fsl_udc_start,
1248 .udc_stop = fsl_udc_stop,
1249 };
1250
1251 /*
1252 * Empty complete function used by this driver to fill in the req->complete
1253 * field when creating a request since the complete field is mandatory.
1254 */
fsl_noop_complete(struct usb_ep * ep,struct usb_request * req)1255 static void fsl_noop_complete(struct usb_ep *ep, struct usb_request *req) { }
1256
1257 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1258 on new transaction */
ep0stall(struct fsl_udc * udc)1259 static void ep0stall(struct fsl_udc *udc)
1260 {
1261 u32 tmp;
1262
1263 /* must set tx and rx to stall at the same time */
1264 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1265 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1266 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1267 udc->ep0_state = WAIT_FOR_SETUP;
1268 udc->ep0_dir = 0;
1269 }
1270
1271 /* Prime a status phase for ep0 */
ep0_prime_status(struct fsl_udc * udc,int direction)1272 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1273 {
1274 struct fsl_req *req = udc->status_req;
1275 struct fsl_ep *ep;
1276 int ret;
1277
1278 if (direction == EP_DIR_IN)
1279 udc->ep0_dir = USB_DIR_IN;
1280 else
1281 udc->ep0_dir = USB_DIR_OUT;
1282
1283 ep = &udc->eps[0];
1284 if (udc->ep0_state != DATA_STATE_XMIT)
1285 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1286
1287 req->ep = ep;
1288 req->req.length = 0;
1289 req->req.status = -EINPROGRESS;
1290 req->req.actual = 0;
1291 req->req.complete = fsl_noop_complete;
1292 req->dtd_count = 0;
1293
1294 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1295 if (ret)
1296 return ret;
1297
1298 if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1299 fsl_queue_td(ep, req);
1300 else
1301 return -ENOMEM;
1302
1303 list_add_tail(&req->queue, &ep->queue);
1304
1305 return 0;
1306 }
1307
udc_reset_ep_queue(struct fsl_udc * udc,u8 pipe)1308 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1309 {
1310 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1311
1312 if (ep->ep.name)
1313 nuke(ep, -ESHUTDOWN);
1314 }
1315
1316 /*
1317 * ch9 Set address
1318 */
ch9setaddress(struct fsl_udc * udc,u16 value,u16 index,u16 length)1319 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1320 {
1321 /* Save the new address to device struct */
1322 udc->device_address = (u8) value;
1323 /* Update usb state */
1324 udc->usb_state = USB_STATE_ADDRESS;
1325 /* Status phase */
1326 if (ep0_prime_status(udc, EP_DIR_IN))
1327 ep0stall(udc);
1328 }
1329
1330 /*
1331 * ch9 Get status
1332 */
ch9getstatus(struct fsl_udc * udc,u8 request_type,u16 value,u16 index,u16 length)1333 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1334 u16 index, u16 length)
1335 {
1336 u16 tmp = 0; /* Status, cpu endian */
1337 struct fsl_req *req;
1338 struct fsl_ep *ep;
1339 int ret;
1340
1341 ep = &udc->eps[0];
1342
1343 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1344 /* Get device status */
1345 tmp = udc->gadget.is_selfpowered;
1346 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1347 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1348 /* Get interface status */
1349 /* We don't have interface information in udc driver */
1350 tmp = 0;
1351 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1352 /* Get endpoint status */
1353 struct fsl_ep *target_ep;
1354
1355 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1356
1357 /* stall if endpoint doesn't exist */
1358 if (!target_ep->ep.desc)
1359 goto stall;
1360 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1361 << USB_ENDPOINT_HALT;
1362 }
1363
1364 udc->ep0_dir = USB_DIR_IN;
1365 /* Borrow the per device status_req */
1366 req = udc->status_req;
1367 /* Fill in the reqest structure */
1368 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1369
1370 req->ep = ep;
1371 req->req.length = 2;
1372 req->req.status = -EINPROGRESS;
1373 req->req.actual = 0;
1374 req->req.complete = fsl_noop_complete;
1375 req->dtd_count = 0;
1376
1377 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1378 if (ret)
1379 goto stall;
1380
1381 /* prime the data phase */
1382 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1383 fsl_queue_td(ep, req);
1384 else /* no mem */
1385 goto stall;
1386
1387 list_add_tail(&req->queue, &ep->queue);
1388 udc->ep0_state = DATA_STATE_XMIT;
1389 if (ep0_prime_status(udc, EP_DIR_OUT))
1390 ep0stall(udc);
1391
1392 return;
1393 stall:
1394 ep0stall(udc);
1395 }
1396
setup_received_irq(struct fsl_udc * udc,struct usb_ctrlrequest * setup)1397 static void setup_received_irq(struct fsl_udc *udc,
1398 struct usb_ctrlrequest *setup)
1399 __releases(udc->lock)
1400 __acquires(udc->lock)
1401 {
1402 u16 wValue = le16_to_cpu(setup->wValue);
1403 u16 wIndex = le16_to_cpu(setup->wIndex);
1404 u16 wLength = le16_to_cpu(setup->wLength);
1405
1406 udc_reset_ep_queue(udc, 0);
1407
1408 /* We process some stardard setup requests here */
1409 switch (setup->bRequest) {
1410 case USB_REQ_GET_STATUS:
1411 /* Data+Status phase from udc */
1412 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1413 != (USB_DIR_IN | USB_TYPE_STANDARD))
1414 break;
1415 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1416 return;
1417
1418 case USB_REQ_SET_ADDRESS:
1419 /* Status phase from udc */
1420 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1421 | USB_RECIP_DEVICE))
1422 break;
1423 ch9setaddress(udc, wValue, wIndex, wLength);
1424 return;
1425
1426 case USB_REQ_CLEAR_FEATURE:
1427 case USB_REQ_SET_FEATURE:
1428 /* Status phase from udc */
1429 {
1430 int rc = -EOPNOTSUPP;
1431 u16 ptc = 0;
1432
1433 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1434 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1435 int pipe = get_pipe_by_windex(wIndex);
1436 struct fsl_ep *ep;
1437
1438 if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
1439 break;
1440 ep = get_ep_by_pipe(udc, pipe);
1441
1442 spin_unlock(&udc->lock);
1443 rc = fsl_ep_set_halt(&ep->ep,
1444 (setup->bRequest == USB_REQ_SET_FEATURE)
1445 ? 1 : 0);
1446 spin_lock(&udc->lock);
1447
1448 } else if ((setup->bRequestType & (USB_RECIP_MASK
1449 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1450 | USB_TYPE_STANDARD)) {
1451 /* Note: The driver has not include OTG support yet.
1452 * This will be set when OTG support is added */
1453 if (wValue == USB_DEVICE_TEST_MODE)
1454 ptc = wIndex >> 8;
1455 else if (gadget_is_otg(&udc->gadget)) {
1456 if (setup->bRequest ==
1457 USB_DEVICE_B_HNP_ENABLE)
1458 udc->gadget.b_hnp_enable = 1;
1459 else if (setup->bRequest ==
1460 USB_DEVICE_A_HNP_SUPPORT)
1461 udc->gadget.a_hnp_support = 1;
1462 else if (setup->bRequest ==
1463 USB_DEVICE_A_ALT_HNP_SUPPORT)
1464 udc->gadget.a_alt_hnp_support = 1;
1465 }
1466 rc = 0;
1467 } else
1468 break;
1469
1470 if (rc == 0) {
1471 if (ep0_prime_status(udc, EP_DIR_IN))
1472 ep0stall(udc);
1473 }
1474 if (ptc) {
1475 u32 tmp;
1476
1477 mdelay(10);
1478 tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1479 fsl_writel(tmp, &dr_regs->portsc1);
1480 printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1481 }
1482
1483 return;
1484 }
1485
1486 default:
1487 break;
1488 }
1489
1490 /* Requests handled by gadget */
1491 if (wLength) {
1492 /* Data phase from gadget, status phase from udc */
1493 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1494 ? USB_DIR_IN : USB_DIR_OUT;
1495 spin_unlock(&udc->lock);
1496 if (udc->driver->setup(&udc->gadget,
1497 &udc->local_setup_buff) < 0)
1498 ep0stall(udc);
1499 spin_lock(&udc->lock);
1500 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1501 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1502 /*
1503 * If the data stage is IN, send status prime immediately.
1504 * See 2.0 Spec chapter 8.5.3.3 for detail.
1505 */
1506 if (udc->ep0_state == DATA_STATE_XMIT)
1507 if (ep0_prime_status(udc, EP_DIR_OUT))
1508 ep0stall(udc);
1509
1510 } else {
1511 /* No data phase, IN status from gadget */
1512 udc->ep0_dir = USB_DIR_IN;
1513 spin_unlock(&udc->lock);
1514 if (udc->driver->setup(&udc->gadget,
1515 &udc->local_setup_buff) < 0)
1516 ep0stall(udc);
1517 spin_lock(&udc->lock);
1518 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1519 }
1520 }
1521
1522 /* Process request for Data or Status phase of ep0
1523 * prime status phase if needed */
ep0_req_complete(struct fsl_udc * udc,struct fsl_ep * ep0,struct fsl_req * req)1524 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1525 struct fsl_req *req)
1526 {
1527 if (udc->usb_state == USB_STATE_ADDRESS) {
1528 /* Set the new address */
1529 u32 new_address = (u32) udc->device_address;
1530 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1531 &dr_regs->deviceaddr);
1532 }
1533
1534 done(ep0, req, 0);
1535
1536 switch (udc->ep0_state) {
1537 case DATA_STATE_XMIT:
1538 /* already primed at setup_received_irq */
1539 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1540 break;
1541 case DATA_STATE_RECV:
1542 /* send status phase */
1543 if (ep0_prime_status(udc, EP_DIR_IN))
1544 ep0stall(udc);
1545 break;
1546 case WAIT_FOR_OUT_STATUS:
1547 udc->ep0_state = WAIT_FOR_SETUP;
1548 break;
1549 case WAIT_FOR_SETUP:
1550 ERR("Unexpect ep0 packets\n");
1551 break;
1552 default:
1553 ep0stall(udc);
1554 break;
1555 }
1556 }
1557
1558 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1559 * being corrupted by another incoming setup packet */
tripwire_handler(struct fsl_udc * udc,u8 ep_num,u8 * buffer_ptr)1560 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1561 {
1562 u32 temp;
1563 struct ep_queue_head *qh;
1564 struct fsl_usb2_platform_data *pdata = udc->pdata;
1565
1566 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1567
1568 /* Clear bit in ENDPTSETUPSTAT */
1569 temp = fsl_readl(&dr_regs->endptsetupstat);
1570 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1571
1572 /* while a hazard exists when setup package arrives */
1573 do {
1574 /* Set Setup Tripwire */
1575 temp = fsl_readl(&dr_regs->usbcmd);
1576 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1577
1578 /* Copy the setup packet to local buffer */
1579 if (pdata->le_setup_buf) {
1580 u32 *p = (u32 *)buffer_ptr;
1581 u32 *s = (u32 *)qh->setup_buffer;
1582
1583 /* Convert little endian setup buffer to CPU endian */
1584 *p++ = le32_to_cpu(*s++);
1585 *p = le32_to_cpu(*s);
1586 } else {
1587 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1588 }
1589 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1590
1591 /* Clear Setup Tripwire */
1592 temp = fsl_readl(&dr_regs->usbcmd);
1593 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1594 }
1595
1596 /* process-ep_req(): free the completed Tds for this req */
process_ep_req(struct fsl_udc * udc,int pipe,struct fsl_req * curr_req)1597 static int process_ep_req(struct fsl_udc *udc, int pipe,
1598 struct fsl_req *curr_req)
1599 {
1600 struct ep_td_struct *curr_td;
1601 int td_complete, actual, remaining_length, j, tmp;
1602 int status = 0;
1603 int errors = 0;
1604 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1605 int direction = pipe % 2;
1606
1607 curr_td = curr_req->head;
1608 td_complete = 0;
1609 actual = curr_req->req.length;
1610
1611 for (j = 0; j < curr_req->dtd_count; j++) {
1612 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1613 & DTD_PACKET_SIZE)
1614 >> DTD_LENGTH_BIT_POS;
1615 actual -= remaining_length;
1616
1617 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1618 if (errors & DTD_ERROR_MASK) {
1619 if (errors & DTD_STATUS_HALTED) {
1620 ERR("dTD error %08x QH=%d\n", errors, pipe);
1621 /* Clear the errors and Halt condition */
1622 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1623 tmp &= ~errors;
1624 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1625 status = -EPIPE;
1626 /* FIXME: continue with next queued TD? */
1627
1628 break;
1629 }
1630 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1631 VDBG("Transfer overflow");
1632 status = -EPROTO;
1633 break;
1634 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1635 VDBG("ISO error");
1636 status = -EILSEQ;
1637 break;
1638 } else
1639 ERR("Unknown error has occurred (0x%x)!\n",
1640 errors);
1641
1642 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1643 & DTD_STATUS_ACTIVE) {
1644 VDBG("Request not complete");
1645 status = REQ_UNCOMPLETE;
1646 return status;
1647 } else if (remaining_length) {
1648 if (direction) {
1649 VDBG("Transmit dTD remaining length not zero");
1650 status = -EPROTO;
1651 break;
1652 } else {
1653 td_complete++;
1654 break;
1655 }
1656 } else {
1657 td_complete++;
1658 VDBG("dTD transmitted successful");
1659 }
1660
1661 if (j != curr_req->dtd_count - 1)
1662 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1663 }
1664
1665 if (status)
1666 return status;
1667
1668 curr_req->req.actual = actual;
1669
1670 return 0;
1671 }
1672
1673 /* Process a DTD completion interrupt */
dtd_complete_irq(struct fsl_udc * udc)1674 static void dtd_complete_irq(struct fsl_udc *udc)
1675 {
1676 u32 bit_pos;
1677 int i, ep_num, direction, bit_mask, status;
1678 struct fsl_ep *curr_ep;
1679 struct fsl_req *curr_req, *temp_req;
1680
1681 /* Clear the bits in the register */
1682 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1683 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1684
1685 if (!bit_pos)
1686 return;
1687
1688 for (i = 0; i < udc->max_ep; i++) {
1689 ep_num = i >> 1;
1690 direction = i % 2;
1691
1692 bit_mask = 1 << (ep_num + 16 * direction);
1693
1694 if (!(bit_pos & bit_mask))
1695 continue;
1696
1697 curr_ep = get_ep_by_pipe(udc, i);
1698
1699 /* If the ep is configured */
1700 if (!curr_ep->ep.name) {
1701 WARNING("Invalid EP?");
1702 continue;
1703 }
1704
1705 /* process the req queue until an uncomplete request */
1706 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1707 queue) {
1708 status = process_ep_req(udc, i, curr_req);
1709
1710 VDBG("status of process_ep_req= %d, ep = %d",
1711 status, ep_num);
1712 if (status == REQ_UNCOMPLETE)
1713 break;
1714 /* write back status to req */
1715 curr_req->req.status = status;
1716
1717 if (ep_num == 0) {
1718 ep0_req_complete(udc, curr_ep, curr_req);
1719 break;
1720 } else
1721 done(curr_ep, curr_req, status);
1722 }
1723 }
1724 }
1725
portscx_device_speed(u32 reg)1726 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1727 {
1728 switch (reg & PORTSCX_PORT_SPEED_MASK) {
1729 case PORTSCX_PORT_SPEED_HIGH:
1730 return USB_SPEED_HIGH;
1731 case PORTSCX_PORT_SPEED_FULL:
1732 return USB_SPEED_FULL;
1733 case PORTSCX_PORT_SPEED_LOW:
1734 return USB_SPEED_LOW;
1735 default:
1736 return USB_SPEED_UNKNOWN;
1737 }
1738 }
1739
1740 /* Process a port change interrupt */
port_change_irq(struct fsl_udc * udc)1741 static void port_change_irq(struct fsl_udc *udc)
1742 {
1743 if (udc->bus_reset)
1744 udc->bus_reset = 0;
1745
1746 /* Bus resetting is finished */
1747 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1748 /* Get the speed */
1749 udc->gadget.speed =
1750 portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1751
1752 /* Update USB state */
1753 if (!udc->resume_state)
1754 udc->usb_state = USB_STATE_DEFAULT;
1755 }
1756
1757 /* Process suspend interrupt */
suspend_irq(struct fsl_udc * udc)1758 static void suspend_irq(struct fsl_udc *udc)
1759 {
1760 udc->resume_state = udc->usb_state;
1761 udc->usb_state = USB_STATE_SUSPENDED;
1762
1763 /* report suspend to the driver, serial.c does not support this */
1764 if (udc->driver->suspend)
1765 udc->driver->suspend(&udc->gadget);
1766 }
1767
bus_resume(struct fsl_udc * udc)1768 static void bus_resume(struct fsl_udc *udc)
1769 {
1770 udc->usb_state = udc->resume_state;
1771 udc->resume_state = 0;
1772
1773 /* report resume to the driver, serial.c does not support this */
1774 if (udc->driver->resume)
1775 udc->driver->resume(&udc->gadget);
1776 }
1777
1778 /* Clear up all ep queues */
reset_queues(struct fsl_udc * udc,bool bus_reset)1779 static int reset_queues(struct fsl_udc *udc, bool bus_reset)
1780 {
1781 u8 pipe;
1782
1783 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1784 udc_reset_ep_queue(udc, pipe);
1785
1786 /* report disconnect; the driver is already quiesced */
1787 spin_unlock(&udc->lock);
1788 if (bus_reset)
1789 usb_gadget_udc_reset(&udc->gadget, udc->driver);
1790 else
1791 udc->driver->disconnect(&udc->gadget);
1792 spin_lock(&udc->lock);
1793
1794 return 0;
1795 }
1796
1797 /* Process reset interrupt */
reset_irq(struct fsl_udc * udc)1798 static void reset_irq(struct fsl_udc *udc)
1799 {
1800 u32 temp;
1801 unsigned long timeout;
1802
1803 /* Clear the device address */
1804 temp = fsl_readl(&dr_regs->deviceaddr);
1805 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1806
1807 udc->device_address = 0;
1808
1809 /* Clear usb state */
1810 udc->resume_state = 0;
1811 udc->ep0_dir = 0;
1812 udc->ep0_state = WAIT_FOR_SETUP;
1813 udc->remote_wakeup = 0; /* default to 0 on reset */
1814 udc->gadget.b_hnp_enable = 0;
1815 udc->gadget.a_hnp_support = 0;
1816 udc->gadget.a_alt_hnp_support = 0;
1817
1818 /* Clear all the setup token semaphores */
1819 temp = fsl_readl(&dr_regs->endptsetupstat);
1820 fsl_writel(temp, &dr_regs->endptsetupstat);
1821
1822 /* Clear all the endpoint complete status bits */
1823 temp = fsl_readl(&dr_regs->endptcomplete);
1824 fsl_writel(temp, &dr_regs->endptcomplete);
1825
1826 timeout = jiffies + 100;
1827 while (fsl_readl(&dr_regs->endpointprime)) {
1828 /* Wait until all endptprime bits cleared */
1829 if (time_after(jiffies, timeout)) {
1830 ERR("Timeout for reset\n");
1831 break;
1832 }
1833 cpu_relax();
1834 }
1835
1836 /* Write 1s to the flush register */
1837 fsl_writel(0xffffffff, &dr_regs->endptflush);
1838
1839 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1840 VDBG("Bus reset");
1841 /* Bus is reseting */
1842 udc->bus_reset = 1;
1843 /* Reset all the queues, include XD, dTD, EP queue
1844 * head and TR Queue */
1845 reset_queues(udc, true);
1846 udc->usb_state = USB_STATE_DEFAULT;
1847 } else {
1848 VDBG("Controller reset");
1849 /* initialize usb hw reg except for regs for EP, not
1850 * touch usbintr reg */
1851 dr_controller_setup(udc);
1852
1853 /* Reset all internal used Queues */
1854 reset_queues(udc, false);
1855
1856 ep0_setup(udc);
1857
1858 /* Enable DR IRQ reg, Set Run bit, change udc state */
1859 dr_controller_run(udc);
1860 udc->usb_state = USB_STATE_ATTACHED;
1861 }
1862 }
1863
1864 /*
1865 * USB device controller interrupt handler
1866 */
fsl_udc_irq(int irq,void * _udc)1867 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1868 {
1869 struct fsl_udc *udc = _udc;
1870 u32 irq_src;
1871 irqreturn_t status = IRQ_NONE;
1872 unsigned long flags;
1873
1874 /* Disable ISR for OTG host mode */
1875 if (udc->stopped)
1876 return IRQ_NONE;
1877 spin_lock_irqsave(&udc->lock, flags);
1878 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1879 /* Clear notification bits */
1880 fsl_writel(irq_src, &dr_regs->usbsts);
1881
1882 /* VDBG("irq_src [0x%8x]", irq_src); */
1883
1884 /* Need to resume? */
1885 if (udc->usb_state == USB_STATE_SUSPENDED)
1886 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1887 bus_resume(udc);
1888
1889 /* USB Interrupt */
1890 if (irq_src & USB_STS_INT) {
1891 VDBG("Packet int");
1892 /* Setup package, we only support ep0 as control ep */
1893 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1894 tripwire_handler(udc, 0,
1895 (u8 *) (&udc->local_setup_buff));
1896 setup_received_irq(udc, &udc->local_setup_buff);
1897 status = IRQ_HANDLED;
1898 }
1899
1900 /* completion of dtd */
1901 if (fsl_readl(&dr_regs->endptcomplete)) {
1902 dtd_complete_irq(udc);
1903 status = IRQ_HANDLED;
1904 }
1905 }
1906
1907 /* SOF (for ISO transfer) */
1908 if (irq_src & USB_STS_SOF) {
1909 status = IRQ_HANDLED;
1910 }
1911
1912 /* Port Change */
1913 if (irq_src & USB_STS_PORT_CHANGE) {
1914 port_change_irq(udc);
1915 status = IRQ_HANDLED;
1916 }
1917
1918 /* Reset Received */
1919 if (irq_src & USB_STS_RESET) {
1920 VDBG("reset int");
1921 reset_irq(udc);
1922 status = IRQ_HANDLED;
1923 }
1924
1925 /* Sleep Enable (Suspend) */
1926 if (irq_src & USB_STS_SUSPEND) {
1927 suspend_irq(udc);
1928 status = IRQ_HANDLED;
1929 }
1930
1931 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1932 VDBG("Error IRQ %x", irq_src);
1933 }
1934
1935 spin_unlock_irqrestore(&udc->lock, flags);
1936 return status;
1937 }
1938
1939 /*----------------------------------------------------------------*
1940 * Hook to gadget drivers
1941 * Called by initialization code of gadget drivers
1942 *----------------------------------------------------------------*/
fsl_udc_start(struct usb_gadget * g,struct usb_gadget_driver * driver)1943 static int fsl_udc_start(struct usb_gadget *g,
1944 struct usb_gadget_driver *driver)
1945 {
1946 int retval = 0;
1947 unsigned long flags = 0;
1948
1949 /* lock is needed but whether should use this lock or another */
1950 spin_lock_irqsave(&udc_controller->lock, flags);
1951
1952 driver->driver.bus = NULL;
1953 /* hook up the driver */
1954 udc_controller->driver = driver;
1955 spin_unlock_irqrestore(&udc_controller->lock, flags);
1956 g->is_selfpowered = 1;
1957
1958 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1959 /* Suspend the controller until OTG enable it */
1960 udc_controller->stopped = 1;
1961 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1962
1963 /* connect to bus through transceiver */
1964 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1965 retval = otg_set_peripheral(
1966 udc_controller->transceiver->otg,
1967 &udc_controller->gadget);
1968 if (retval < 0) {
1969 ERR("can't bind to transceiver\n");
1970 udc_controller->driver = NULL;
1971 return retval;
1972 }
1973 }
1974 } else {
1975 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1976 dr_controller_run(udc_controller);
1977 udc_controller->usb_state = USB_STATE_ATTACHED;
1978 udc_controller->ep0_state = WAIT_FOR_SETUP;
1979 udc_controller->ep0_dir = 0;
1980 }
1981
1982 return retval;
1983 }
1984
1985 /* Disconnect from gadget driver */
fsl_udc_stop(struct usb_gadget * g)1986 static int fsl_udc_stop(struct usb_gadget *g)
1987 {
1988 struct fsl_ep *loop_ep;
1989 unsigned long flags;
1990
1991 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
1992 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
1993
1994 /* stop DR, disable intr */
1995 dr_controller_stop(udc_controller);
1996
1997 /* in fact, no needed */
1998 udc_controller->usb_state = USB_STATE_ATTACHED;
1999 udc_controller->ep0_state = WAIT_FOR_SETUP;
2000 udc_controller->ep0_dir = 0;
2001
2002 /* stand operation */
2003 spin_lock_irqsave(&udc_controller->lock, flags);
2004 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2005 nuke(&udc_controller->eps[0], -ESHUTDOWN);
2006 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2007 ep.ep_list)
2008 nuke(loop_ep, -ESHUTDOWN);
2009 spin_unlock_irqrestore(&udc_controller->lock, flags);
2010
2011 udc_controller->driver = NULL;
2012
2013 return 0;
2014 }
2015
2016 /*-------------------------------------------------------------------------
2017 PROC File System Support
2018 -------------------------------------------------------------------------*/
2019 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2020
2021 #include <linux/seq_file.h>
2022
2023 static const char proc_filename[] = "driver/fsl_usb2_udc";
2024
fsl_proc_read(struct seq_file * m,void * v)2025 static int fsl_proc_read(struct seq_file *m, void *v)
2026 {
2027 unsigned long flags;
2028 int i;
2029 u32 tmp_reg;
2030 struct fsl_ep *ep = NULL;
2031 struct fsl_req *req;
2032
2033 struct fsl_udc *udc = udc_controller;
2034
2035 spin_lock_irqsave(&udc->lock, flags);
2036
2037 /* ------basic driver information ---- */
2038 seq_printf(m,
2039 DRIVER_DESC "\n"
2040 "%s version: %s\n"
2041 "Gadget driver: %s\n\n",
2042 driver_name, DRIVER_VERSION,
2043 udc->driver ? udc->driver->driver.name : "(none)");
2044
2045 /* ------ DR Registers ----- */
2046 tmp_reg = fsl_readl(&dr_regs->usbcmd);
2047 seq_printf(m,
2048 "USBCMD reg:\n"
2049 "SetupTW: %d\n"
2050 "Run/Stop: %s\n\n",
2051 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2052 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2053
2054 tmp_reg = fsl_readl(&dr_regs->usbsts);
2055 seq_printf(m,
2056 "USB Status Reg:\n"
2057 "Dr Suspend: %d Reset Received: %d System Error: %s "
2058 "USB Error Interrupt: %s\n\n",
2059 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2060 (tmp_reg & USB_STS_RESET) ? 1 : 0,
2061 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2062 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2063
2064 tmp_reg = fsl_readl(&dr_regs->usbintr);
2065 seq_printf(m,
2066 "USB Interrupt Enable Reg:\n"
2067 "Sleep Enable: %d SOF Received Enable: %d "
2068 "Reset Enable: %d\n"
2069 "System Error Enable: %d "
2070 "Port Change Dectected Enable: %d\n"
2071 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2072 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2073 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2074 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2075 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2076 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2077 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2078 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2079
2080 tmp_reg = fsl_readl(&dr_regs->frindex);
2081 seq_printf(m,
2082 "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2083 (tmp_reg & USB_FRINDEX_MASKS));
2084
2085 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2086 seq_printf(m,
2087 "USB Device Address Reg: Device Addr is 0x%x\n\n",
2088 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2089
2090 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2091 seq_printf(m,
2092 "USB Endpoint List Address Reg: "
2093 "Device Addr is 0x%x\n\n",
2094 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2095
2096 tmp_reg = fsl_readl(&dr_regs->portsc1);
2097 seq_printf(m,
2098 "USB Port Status&Control Reg:\n"
2099 "Port Transceiver Type : %s Port Speed: %s\n"
2100 "PHY Low Power Suspend: %s Port Reset: %s "
2101 "Port Suspend Mode: %s\n"
2102 "Over-current Change: %s "
2103 "Port Enable/Disable Change: %s\n"
2104 "Port Enabled/Disabled: %s "
2105 "Current Connect Status: %s\n\n", ( {
2106 const char *s;
2107 switch (tmp_reg & PORTSCX_PTS_FSLS) {
2108 case PORTSCX_PTS_UTMI:
2109 s = "UTMI"; break;
2110 case PORTSCX_PTS_ULPI:
2111 s = "ULPI "; break;
2112 case PORTSCX_PTS_FSLS:
2113 s = "FS/LS Serial"; break;
2114 default:
2115 s = "None"; break;
2116 }
2117 s;} ),
2118 usb_speed_string(portscx_device_speed(tmp_reg)),
2119 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2120 "Normal PHY mode" : "Low power mode",
2121 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2122 "Not in Reset",
2123 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2124 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2125 "No",
2126 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2127 "Not change",
2128 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2129 "Not correct",
2130 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2131 "Attached" : "Not-Att");
2132
2133 tmp_reg = fsl_readl(&dr_regs->usbmode);
2134 seq_printf(m,
2135 "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2136 const char *s;
2137 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2138 case USB_MODE_CTRL_MODE_IDLE:
2139 s = "Idle"; break;
2140 case USB_MODE_CTRL_MODE_DEVICE:
2141 s = "Device Controller"; break;
2142 case USB_MODE_CTRL_MODE_HOST:
2143 s = "Host Controller"; break;
2144 default:
2145 s = "None"; break;
2146 }
2147 s;
2148 } ));
2149
2150 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2151 seq_printf(m,
2152 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2153 (tmp_reg & EP_SETUP_STATUS_MASK));
2154
2155 for (i = 0; i < udc->max_ep / 2; i++) {
2156 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2157 seq_printf(m, "EP Ctrl Reg [0x%x]: = [0x%x]\n", i, tmp_reg);
2158 }
2159 tmp_reg = fsl_readl(&dr_regs->endpointprime);
2160 seq_printf(m, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2161
2162 #ifndef CONFIG_ARCH_MXC
2163 if (udc->pdata->have_sysif_regs) {
2164 tmp_reg = usb_sys_regs->snoop1;
2165 seq_printf(m, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2166
2167 tmp_reg = usb_sys_regs->control;
2168 seq_printf(m, "General Control Reg : = [0x%x]\n\n", tmp_reg);
2169 }
2170 #endif
2171
2172 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2173 ep = &udc->eps[0];
2174 seq_printf(m, "For %s Maxpkt is 0x%x index is 0x%x\n",
2175 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2176
2177 if (list_empty(&ep->queue)) {
2178 seq_puts(m, "its req queue is empty\n\n");
2179 } else {
2180 list_for_each_entry(req, &ep->queue, queue) {
2181 seq_printf(m,
2182 "req %p actual 0x%x length 0x%x buf %p\n",
2183 &req->req, req->req.actual,
2184 req->req.length, req->req.buf);
2185 }
2186 }
2187 /* other gadget->eplist ep */
2188 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2189 if (ep->ep.desc) {
2190 seq_printf(m,
2191 "\nFor %s Maxpkt is 0x%x "
2192 "index is 0x%x\n",
2193 ep->ep.name, ep_maxpacket(ep),
2194 ep_index(ep));
2195
2196 if (list_empty(&ep->queue)) {
2197 seq_puts(m, "its req queue is empty\n\n");
2198 } else {
2199 list_for_each_entry(req, &ep->queue, queue) {
2200 seq_printf(m,
2201 "req %p actual 0x%x length "
2202 "0x%x buf %p\n",
2203 &req->req, req->req.actual,
2204 req->req.length, req->req.buf);
2205 } /* end for each_entry of ep req */
2206 } /* end for else */
2207 } /* end for if(ep->queue) */
2208 } /* end (ep->desc) */
2209
2210 spin_unlock_irqrestore(&udc->lock, flags);
2211 return 0;
2212 }
2213
2214 /*
2215 * seq_file wrappers for procfile show routines.
2216 */
fsl_proc_open(struct inode * inode,struct file * file)2217 static int fsl_proc_open(struct inode *inode, struct file *file)
2218 {
2219 return single_open(file, fsl_proc_read, NULL);
2220 }
2221
2222 static const struct file_operations fsl_proc_fops = {
2223 .open = fsl_proc_open,
2224 .read = seq_read,
2225 .llseek = seq_lseek,
2226 .release = single_release,
2227 };
2228
2229 #define create_proc_file() proc_create(proc_filename, 0, NULL, &fsl_proc_fops)
2230 #define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2231
2232 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2233
2234 #define create_proc_file() do {} while (0)
2235 #define remove_proc_file() do {} while (0)
2236
2237 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2238
2239 /*-------------------------------------------------------------------------*/
2240
2241 /* Release udc structures */
fsl_udc_release(struct device * dev)2242 static void fsl_udc_release(struct device *dev)
2243 {
2244 complete(udc_controller->done);
2245 dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2246 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2247 kfree(udc_controller);
2248 }
2249
2250 /******************************************************************
2251 Internal structure setup functions
2252 *******************************************************************/
2253 /*------------------------------------------------------------------
2254 * init resource for globle controller
2255 * Return the udc handle on success or NULL on failure
2256 ------------------------------------------------------------------*/
struct_udc_setup(struct fsl_udc * udc,struct platform_device * pdev)2257 static int struct_udc_setup(struct fsl_udc *udc,
2258 struct platform_device *pdev)
2259 {
2260 struct fsl_usb2_platform_data *pdata;
2261 size_t size;
2262
2263 pdata = dev_get_platdata(&pdev->dev);
2264 udc->phy_mode = pdata->phy_mode;
2265
2266 udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2267 if (!udc->eps)
2268 return -1;
2269
2270 /* initialized QHs, take care of alignment */
2271 size = udc->max_ep * sizeof(struct ep_queue_head);
2272 if (size < QH_ALIGNMENT)
2273 size = QH_ALIGNMENT;
2274 else if ((size % QH_ALIGNMENT) != 0) {
2275 size += QH_ALIGNMENT + 1;
2276 size &= ~(QH_ALIGNMENT - 1);
2277 }
2278 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2279 &udc->ep_qh_dma, GFP_KERNEL);
2280 if (!udc->ep_qh) {
2281 ERR("malloc QHs for udc failed\n");
2282 kfree(udc->eps);
2283 return -1;
2284 }
2285
2286 udc->ep_qh_size = size;
2287
2288 /* Initialize ep0 status request structure */
2289 /* FIXME: fsl_alloc_request() ignores ep argument */
2290 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2291 struct fsl_req, req);
2292 /* allocate a small amount of memory to get valid address */
2293 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2294
2295 udc->resume_state = USB_STATE_NOTATTACHED;
2296 udc->usb_state = USB_STATE_POWERED;
2297 udc->ep0_dir = 0;
2298 udc->remote_wakeup = 0; /* default to 0 on reset */
2299
2300 return 0;
2301 }
2302
2303 /*----------------------------------------------------------------
2304 * Setup the fsl_ep struct for eps
2305 * Link fsl_ep->ep to gadget->ep_list
2306 * ep0out is not used so do nothing here
2307 * ep0in should be taken care
2308 *--------------------------------------------------------------*/
struct_ep_setup(struct fsl_udc * udc,unsigned char index,char * name,int link)2309 static int struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2310 char *name, int link)
2311 {
2312 struct fsl_ep *ep = &udc->eps[index];
2313
2314 ep->udc = udc;
2315 strcpy(ep->name, name);
2316 ep->ep.name = ep->name;
2317
2318 ep->ep.ops = &fsl_ep_ops;
2319 ep->stopped = 0;
2320
2321 if (index == 0) {
2322 ep->ep.caps.type_control = true;
2323 } else {
2324 ep->ep.caps.type_iso = true;
2325 ep->ep.caps.type_bulk = true;
2326 ep->ep.caps.type_int = true;
2327 }
2328
2329 if (index & 1)
2330 ep->ep.caps.dir_in = true;
2331 else
2332 ep->ep.caps.dir_out = true;
2333
2334 /* for ep0: maxP defined in desc
2335 * for other eps, maxP is set by epautoconfig() called by gadget layer
2336 */
2337 usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
2338
2339 /* the queue lists any req for this ep */
2340 INIT_LIST_HEAD(&ep->queue);
2341
2342 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2343 if (link)
2344 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2345 ep->gadget = &udc->gadget;
2346 ep->qh = &udc->ep_qh[index];
2347
2348 return 0;
2349 }
2350
2351 /* Driver probe function
2352 * all initialization operations implemented here except enabling usb_intr reg
2353 * board setup should have been done in the platform code
2354 */
fsl_udc_probe(struct platform_device * pdev)2355 static int fsl_udc_probe(struct platform_device *pdev)
2356 {
2357 struct fsl_usb2_platform_data *pdata;
2358 struct resource *res;
2359 int ret = -ENODEV;
2360 unsigned int i;
2361 u32 dccparams;
2362
2363 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2364 if (udc_controller == NULL)
2365 return -ENOMEM;
2366
2367 pdata = dev_get_platdata(&pdev->dev);
2368 udc_controller->pdata = pdata;
2369 spin_lock_init(&udc_controller->lock);
2370 udc_controller->stopped = 1;
2371
2372 #ifdef CONFIG_USB_OTG
2373 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2374 udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
2375 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2376 ERR("Can't find OTG driver!\n");
2377 ret = -ENODEV;
2378 goto err_kfree;
2379 }
2380 }
2381 #endif
2382
2383 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2384 if (!res) {
2385 ret = -ENXIO;
2386 goto err_kfree;
2387 }
2388
2389 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2390 if (!request_mem_region(res->start, resource_size(res),
2391 driver_name)) {
2392 ERR("request mem region for %s failed\n", pdev->name);
2393 ret = -EBUSY;
2394 goto err_kfree;
2395 }
2396 }
2397
2398 dr_regs = ioremap(res->start, resource_size(res));
2399 if (!dr_regs) {
2400 ret = -ENOMEM;
2401 goto err_release_mem_region;
2402 }
2403
2404 pdata->regs = (void __iomem *)dr_regs;
2405
2406 /*
2407 * do platform specific init: check the clock, grab/config pins, etc.
2408 */
2409 if (pdata->init && pdata->init(pdev)) {
2410 ret = -ENODEV;
2411 goto err_iounmap_noclk;
2412 }
2413
2414 /* Set accessors only after pdata->init() ! */
2415 fsl_set_accessors(pdata);
2416
2417 #ifndef CONFIG_ARCH_MXC
2418 if (pdata->have_sysif_regs)
2419 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2420 #endif
2421
2422 /* Initialize USB clocks */
2423 ret = fsl_udc_clk_init(pdev);
2424 if (ret < 0)
2425 goto err_iounmap_noclk;
2426
2427 /* Read Device Controller Capability Parameters register */
2428 dccparams = fsl_readl(&dr_regs->dccparams);
2429 if (!(dccparams & DCCPARAMS_DC)) {
2430 ERR("This SOC doesn't support device role\n");
2431 ret = -ENODEV;
2432 goto err_iounmap;
2433 }
2434 /* Get max device endpoints */
2435 /* DEN is bidirectional ep number, max_ep doubles the number */
2436 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2437
2438 udc_controller->irq = platform_get_irq(pdev, 0);
2439 if (!udc_controller->irq) {
2440 ret = -ENODEV;
2441 goto err_iounmap;
2442 }
2443
2444 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2445 driver_name, udc_controller);
2446 if (ret != 0) {
2447 ERR("cannot request irq %d err %d\n",
2448 udc_controller->irq, ret);
2449 goto err_iounmap;
2450 }
2451
2452 /* Initialize the udc structure including QH member and other member */
2453 if (struct_udc_setup(udc_controller, pdev)) {
2454 ERR("Can't initialize udc data structure\n");
2455 ret = -ENOMEM;
2456 goto err_free_irq;
2457 }
2458
2459 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2460 /* initialize usb hw reg except for regs for EP,
2461 * leave usbintr reg untouched */
2462 dr_controller_setup(udc_controller);
2463 }
2464
2465 ret = fsl_udc_clk_finalize(pdev);
2466 if (ret)
2467 goto err_free_irq;
2468
2469 /* Setup gadget structure */
2470 udc_controller->gadget.ops = &fsl_gadget_ops;
2471 udc_controller->gadget.max_speed = USB_SPEED_HIGH;
2472 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2473 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2474 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2475 udc_controller->gadget.name = driver_name;
2476
2477 /* Setup gadget.dev and register with kernel */
2478 dev_set_name(&udc_controller->gadget.dev, "gadget");
2479 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
2480
2481 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
2482 udc_controller->gadget.is_otg = 1;
2483
2484 /* setup QH and epctrl for ep0 */
2485 ep0_setup(udc_controller);
2486
2487 /* setup udc->eps[] for ep0 */
2488 struct_ep_setup(udc_controller, 0, "ep0", 0);
2489 /* for ep0: the desc defined here;
2490 * for other eps, gadget layer called ep_enable with defined desc
2491 */
2492 udc_controller->eps[0].ep.desc = &fsl_ep0_desc;
2493 usb_ep_set_maxpacket_limit(&udc_controller->eps[0].ep,
2494 USB_MAX_CTRL_PAYLOAD);
2495
2496 /* setup the udc->eps[] for non-control endpoints and link
2497 * to gadget.ep_list */
2498 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2499 char name[14];
2500
2501 sprintf(name, "ep%dout", i);
2502 struct_ep_setup(udc_controller, i * 2, name, 1);
2503 sprintf(name, "ep%din", i);
2504 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2505 }
2506
2507 /* use dma_pool for TD management */
2508 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2509 sizeof(struct ep_td_struct),
2510 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2511 if (udc_controller->td_pool == NULL) {
2512 ret = -ENOMEM;
2513 goto err_free_irq;
2514 }
2515
2516 ret = usb_add_gadget_udc_release(&pdev->dev, &udc_controller->gadget,
2517 fsl_udc_release);
2518 if (ret)
2519 goto err_del_udc;
2520
2521 create_proc_file();
2522 return 0;
2523
2524 err_del_udc:
2525 dma_pool_destroy(udc_controller->td_pool);
2526 err_free_irq:
2527 free_irq(udc_controller->irq, udc_controller);
2528 err_iounmap:
2529 if (pdata->exit)
2530 pdata->exit(pdev);
2531 fsl_udc_clk_release();
2532 err_iounmap_noclk:
2533 iounmap(dr_regs);
2534 err_release_mem_region:
2535 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2536 release_mem_region(res->start, resource_size(res));
2537 err_kfree:
2538 kfree(udc_controller);
2539 udc_controller = NULL;
2540 return ret;
2541 }
2542
2543 /* Driver removal function
2544 * Free resources and finish pending transactions
2545 */
fsl_udc_remove(struct platform_device * pdev)2546 static int fsl_udc_remove(struct platform_device *pdev)
2547 {
2548 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2549 struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
2550
2551 DECLARE_COMPLETION_ONSTACK(done);
2552
2553 if (!udc_controller)
2554 return -ENODEV;
2555
2556 udc_controller->done = &done;
2557 usb_del_gadget_udc(&udc_controller->gadget);
2558
2559 fsl_udc_clk_release();
2560
2561 /* DR has been stopped in usb_gadget_unregister_driver() */
2562 remove_proc_file();
2563
2564 /* Free allocated memory */
2565 kfree(udc_controller->status_req->req.buf);
2566 kfree(udc_controller->status_req);
2567 kfree(udc_controller->eps);
2568
2569 dma_pool_destroy(udc_controller->td_pool);
2570 free_irq(udc_controller->irq, udc_controller);
2571 iounmap(dr_regs);
2572 if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
2573 release_mem_region(res->start, resource_size(res));
2574
2575 /* free udc --wait for the release() finished */
2576 wait_for_completion(&done);
2577
2578 /*
2579 * do platform specific un-initialization:
2580 * release iomux pins, etc.
2581 */
2582 if (pdata->exit)
2583 pdata->exit(pdev);
2584
2585 return 0;
2586 }
2587
2588 /*-----------------------------------------------------------------
2589 * Modify Power management attributes
2590 * Used by OTG statemachine to disable gadget temporarily
2591 -----------------------------------------------------------------*/
fsl_udc_suspend(struct platform_device * pdev,pm_message_t state)2592 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2593 {
2594 dr_controller_stop(udc_controller);
2595 return 0;
2596 }
2597
2598 /*-----------------------------------------------------------------
2599 * Invoked on USB resume. May be called in_interrupt.
2600 * Here we start the DR controller and enable the irq
2601 *-----------------------------------------------------------------*/
fsl_udc_resume(struct platform_device * pdev)2602 static int fsl_udc_resume(struct platform_device *pdev)
2603 {
2604 /* Enable DR irq reg and set controller Run */
2605 if (udc_controller->stopped) {
2606 dr_controller_setup(udc_controller);
2607 dr_controller_run(udc_controller);
2608 }
2609 udc_controller->usb_state = USB_STATE_ATTACHED;
2610 udc_controller->ep0_state = WAIT_FOR_SETUP;
2611 udc_controller->ep0_dir = 0;
2612 return 0;
2613 }
2614
fsl_udc_otg_suspend(struct device * dev,pm_message_t state)2615 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2616 {
2617 struct fsl_udc *udc = udc_controller;
2618 u32 mode, usbcmd;
2619
2620 mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2621
2622 pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2623
2624 /*
2625 * If the controller is already stopped, then this must be a
2626 * PM suspend. Remember this fact, so that we will leave the
2627 * controller stopped at PM resume time.
2628 */
2629 if (udc->stopped) {
2630 pr_debug("gadget already stopped, leaving early\n");
2631 udc->already_stopped = 1;
2632 return 0;
2633 }
2634
2635 if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2636 pr_debug("gadget not in device mode, leaving early\n");
2637 return 0;
2638 }
2639
2640 /* stop the controller */
2641 usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2642 fsl_writel(usbcmd, &dr_regs->usbcmd);
2643
2644 udc->stopped = 1;
2645
2646 pr_info("USB Gadget suspended\n");
2647
2648 return 0;
2649 }
2650
fsl_udc_otg_resume(struct device * dev)2651 static int fsl_udc_otg_resume(struct device *dev)
2652 {
2653 pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
2654 udc_controller->stopped, udc_controller->already_stopped);
2655
2656 /*
2657 * If the controller was stopped at suspend time, then
2658 * don't resume it now.
2659 */
2660 if (udc_controller->already_stopped) {
2661 udc_controller->already_stopped = 0;
2662 pr_debug("gadget was already stopped, leaving early\n");
2663 return 0;
2664 }
2665
2666 pr_info("USB Gadget resume\n");
2667
2668 return fsl_udc_resume(NULL);
2669 }
2670 /*-------------------------------------------------------------------------
2671 Register entry point for the peripheral controller driver
2672 --------------------------------------------------------------------------*/
2673 static const struct platform_device_id fsl_udc_devtype[] = {
2674 {
2675 .name = "imx-udc-mx27",
2676 }, {
2677 .name = "imx-udc-mx51",
2678 }, {
2679 .name = "fsl-usb2-udc",
2680 }, {
2681 /* sentinel */
2682 }
2683 };
2684 MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
2685 static struct platform_driver udc_driver = {
2686 .remove = fsl_udc_remove,
2687 /* Just for FSL i.mx SoC currently */
2688 .id_table = fsl_udc_devtype,
2689 /* these suspend and resume are not usb suspend and resume */
2690 .suspend = fsl_udc_suspend,
2691 .resume = fsl_udc_resume,
2692 .driver = {
2693 .name = driver_name,
2694 /* udc suspend/resume called from OTG driver */
2695 .suspend = fsl_udc_otg_suspend,
2696 .resume = fsl_udc_otg_resume,
2697 },
2698 };
2699
2700 module_platform_driver_probe(udc_driver, fsl_udc_probe);
2701
2702 MODULE_DESCRIPTION(DRIVER_DESC);
2703 MODULE_AUTHOR(DRIVER_AUTHOR);
2704 MODULE_LICENSE("GPL");
2705 MODULE_ALIAS("platform:fsl-usb2-udc");
2706