1 /*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23
24 #include <linux/slab.h>
25 #include <asm/unaligned.h>
26
27 #include "xhci.h"
28 #include "xhci-trace.h"
29
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
32 PORT_RC | PORT_PLC | PORT_PE)
33
34 /* USB 3 BOS descriptor and a capability descriptors, combined.
35 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
36 */
37 static u8 usb_bos_descriptor [] = {
38 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
39 USB_DT_BOS, /* __u8 bDescriptorType */
40 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
41 0x1, /* __u8 bNumDeviceCaps */
42 /* First device capability, SuperSpeed */
43 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
44 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
45 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
46 0x00, /* bmAttributes, LTM off by default */
47 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
48 0x03, /* bFunctionalitySupport,
49 USB 3.0 speed only */
50 0x00, /* bU1DevExitLat, set later. */
51 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
52 /* Second device capability, SuperSpeedPlus */
53 0x1c, /* bLength 28, will be adjusted later */
54 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
55 USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
56 0x00, /* bReserved 0 */
57 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
58 0x01, 0x00, /* wFunctionalitySupport */
59 0x00, 0x00, /* wReserved 0 */
60 /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
61 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
62 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
63 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
64 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
65 };
66
xhci_create_usb3_bos_desc(struct xhci_hcd * xhci,char * buf,u16 wLength)67 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
68 u16 wLength)
69 {
70 int i, ssa_count;
71 u32 temp;
72 u16 desc_size, ssp_cap_size, ssa_size = 0;
73 bool usb3_1 = false;
74
75 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
76 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
77
78 /* does xhci support USB 3.1 Enhanced SuperSpeed */
79 if (xhci->usb3_rhub.min_rev >= 0x01) {
80 /* does xhci provide a PSI table for SSA speed attributes? */
81 if (xhci->usb3_rhub.psi_count) {
82 /* two SSA entries for each unique PSI ID, RX and TX */
83 ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
84 ssa_size = ssa_count * sizeof(u32);
85 ssp_cap_size -= 16; /* skip copying the default SSA */
86 }
87 desc_size += ssp_cap_size;
88 usb3_1 = true;
89 }
90 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
91
92 if (usb3_1) {
93 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
94 buf[4] += 1;
95 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
96 }
97
98 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
99 return wLength;
100
101 /* Indicate whether the host has LTM support. */
102 temp = readl(&xhci->cap_regs->hcc_params);
103 if (HCC_LTC(temp))
104 buf[8] |= USB_LTM_SUPPORT;
105
106 /* Set the U1 and U2 exit latencies. */
107 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
108 temp = readl(&xhci->cap_regs->hcs_params3);
109 buf[12] = HCS_U1_LATENCY(temp);
110 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
111 }
112
113 /* If PSI table exists, add the custom speed attributes from it */
114 if (usb3_1 && xhci->usb3_rhub.psi_count) {
115 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
116 int offset;
117
118 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
119
120 if (wLength < desc_size)
121 return wLength;
122 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
123
124 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
125 bm_attrib = (ssa_count - 1) & 0x1f;
126 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
127 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
128
129 if (wLength < desc_size + ssa_size)
130 return wLength;
131 /*
132 * Create the Sublink Speed Attributes (SSA) array.
133 * The xhci PSI field and USB 3.1 SSA fields are very similar,
134 * but link type bits 7:6 differ for values 01b and 10b.
135 * xhci has also only one PSI entry for a symmetric link when
136 * USB 3.1 requires two SSA entries (RX and TX) for every link
137 */
138 offset = desc_size;
139 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
140 psi = xhci->usb3_rhub.psi[i];
141 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
142 psi_exp = XHCI_EXT_PORT_PSIE(psi);
143 psi_mant = XHCI_EXT_PORT_PSIM(psi);
144
145 /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
146 for (; psi_exp < 3; psi_exp++)
147 psi_mant /= 1000;
148 if (psi_mant >= 10)
149 psi |= BIT(14);
150
151 if ((psi & PLT_MASK) == PLT_SYM) {
152 /* Symmetric, create SSA RX and TX from one PSI entry */
153 put_unaligned_le32(psi, &buf[offset]);
154 psi |= 1 << 7; /* turn entry to TX */
155 offset += 4;
156 if (offset >= desc_size + ssa_size)
157 return desc_size + ssa_size;
158 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
159 /* Asymetric RX, flip bits 7:6 for SSA */
160 psi ^= PLT_MASK;
161 }
162 put_unaligned_le32(psi, &buf[offset]);
163 offset += 4;
164 if (offset >= desc_size + ssa_size)
165 return desc_size + ssa_size;
166 }
167 }
168 /* ssa_size is 0 for other than usb 3.1 hosts */
169 return desc_size + ssa_size;
170 }
171
xhci_common_hub_descriptor(struct xhci_hcd * xhci,struct usb_hub_descriptor * desc,int ports)172 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
173 struct usb_hub_descriptor *desc, int ports)
174 {
175 u16 temp;
176
177 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
178 desc->bHubContrCurrent = 0;
179
180 desc->bNbrPorts = ports;
181 temp = 0;
182 /* Bits 1:0 - support per-port power switching, or power always on */
183 if (HCC_PPC(xhci->hcc_params))
184 temp |= HUB_CHAR_INDV_PORT_LPSM;
185 else
186 temp |= HUB_CHAR_NO_LPSM;
187 /* Bit 2 - root hubs are not part of a compound device */
188 /* Bits 4:3 - individual port over current protection */
189 temp |= HUB_CHAR_INDV_PORT_OCPM;
190 /* Bits 6:5 - no TTs in root ports */
191 /* Bit 7 - no port indicators */
192 desc->wHubCharacteristics = cpu_to_le16(temp);
193 }
194
195 /* Fill in the USB 2.0 roothub descriptor */
xhci_usb2_hub_descriptor(struct usb_hcd * hcd,struct xhci_hcd * xhci,struct usb_hub_descriptor * desc)196 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
197 struct usb_hub_descriptor *desc)
198 {
199 int ports;
200 u16 temp;
201 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
202 u32 portsc;
203 unsigned int i;
204
205 ports = xhci->num_usb2_ports;
206
207 xhci_common_hub_descriptor(xhci, desc, ports);
208 desc->bDescriptorType = USB_DT_HUB;
209 temp = 1 + (ports / 8);
210 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
211
212 /* The Device Removable bits are reported on a byte granularity.
213 * If the port doesn't exist within that byte, the bit is set to 0.
214 */
215 memset(port_removable, 0, sizeof(port_removable));
216 for (i = 0; i < ports; i++) {
217 portsc = readl(xhci->usb2_ports[i]);
218 /* If a device is removable, PORTSC reports a 0, same as in the
219 * hub descriptor DeviceRemovable bits.
220 */
221 if (portsc & PORT_DEV_REMOVE)
222 /* This math is hairy because bit 0 of DeviceRemovable
223 * is reserved, and bit 1 is for port 1, etc.
224 */
225 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
226 }
227
228 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
229 * ports on it. The USB 2.0 specification says that there are two
230 * variable length fields at the end of the hub descriptor:
231 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
232 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
233 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
234 * 0xFF, so we initialize the both arrays (DeviceRemovable and
235 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
236 * set of ports that actually exist.
237 */
238 memset(desc->u.hs.DeviceRemovable, 0xff,
239 sizeof(desc->u.hs.DeviceRemovable));
240 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
241 sizeof(desc->u.hs.PortPwrCtrlMask));
242
243 for (i = 0; i < (ports + 1 + 7) / 8; i++)
244 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
245 sizeof(__u8));
246 }
247
248 /* Fill in the USB 3.0 roothub descriptor */
xhci_usb3_hub_descriptor(struct usb_hcd * hcd,struct xhci_hcd * xhci,struct usb_hub_descriptor * desc)249 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
250 struct usb_hub_descriptor *desc)
251 {
252 int ports;
253 u16 port_removable;
254 u32 portsc;
255 unsigned int i;
256
257 ports = xhci->num_usb3_ports;
258 xhci_common_hub_descriptor(xhci, desc, ports);
259 desc->bDescriptorType = USB_DT_SS_HUB;
260 desc->bDescLength = USB_DT_SS_HUB_SIZE;
261
262 /* header decode latency should be zero for roothubs,
263 * see section 4.23.5.2.
264 */
265 desc->u.ss.bHubHdrDecLat = 0;
266 desc->u.ss.wHubDelay = 0;
267
268 port_removable = 0;
269 /* bit 0 is reserved, bit 1 is for port 1, etc. */
270 for (i = 0; i < ports; i++) {
271 portsc = readl(xhci->usb3_ports[i]);
272 if (portsc & PORT_DEV_REMOVE)
273 port_removable |= 1 << (i + 1);
274 }
275
276 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
277 }
278
xhci_hub_descriptor(struct usb_hcd * hcd,struct xhci_hcd * xhci,struct usb_hub_descriptor * desc)279 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
280 struct usb_hub_descriptor *desc)
281 {
282
283 if (hcd->speed >= HCD_USB3)
284 xhci_usb3_hub_descriptor(hcd, xhci, desc);
285 else
286 xhci_usb2_hub_descriptor(hcd, xhci, desc);
287
288 }
289
xhci_port_speed(unsigned int port_status)290 static unsigned int xhci_port_speed(unsigned int port_status)
291 {
292 if (DEV_LOWSPEED(port_status))
293 return USB_PORT_STAT_LOW_SPEED;
294 if (DEV_HIGHSPEED(port_status))
295 return USB_PORT_STAT_HIGH_SPEED;
296 /*
297 * FIXME: Yes, we should check for full speed, but the core uses that as
298 * a default in portspeed() in usb/core/hub.c (which is the only place
299 * USB_PORT_STAT_*_SPEED is used).
300 */
301 return 0;
302 }
303
304 /*
305 * These bits are Read Only (RO) and should be saved and written to the
306 * registers: 0, 3, 10:13, 30
307 * connect status, over-current status, port speed, and device removable.
308 * connect status and port speed are also sticky - meaning they're in
309 * the AUX well and they aren't changed by a hot, warm, or cold reset.
310 */
311 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
312 /*
313 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
314 * bits 5:8, 9, 14:15, 25:27
315 * link state, port power, port indicator state, "wake on" enable state
316 */
317 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
318 /*
319 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
320 * bit 4 (port reset)
321 */
322 #define XHCI_PORT_RW1S ((1<<4))
323 /*
324 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
325 * bits 1, 17, 18, 19, 20, 21, 22, 23
326 * port enable/disable, and
327 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
328 * over-current, reset, link state, and L1 change
329 */
330 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
331 /*
332 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
333 * latched in
334 */
335 #define XHCI_PORT_RW ((1<<16))
336 /*
337 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
338 * bits 2, 24, 28:31
339 */
340 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
341
342 /*
343 * Given a port state, this function returns a value that would result in the
344 * port being in the same state, if the value was written to the port status
345 * control register.
346 * Save Read Only (RO) bits and save read/write bits where
347 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
348 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
349 */
xhci_port_state_to_neutral(u32 state)350 u32 xhci_port_state_to_neutral(u32 state)
351 {
352 /* Save read-only status and port state */
353 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
354 }
355
356 /*
357 * find slot id based on port number.
358 * @port: The one-based port number from one of the two split roothubs.
359 */
xhci_find_slot_id_by_port(struct usb_hcd * hcd,struct xhci_hcd * xhci,u16 port)360 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
361 u16 port)
362 {
363 int slot_id;
364 int i;
365 enum usb_device_speed speed;
366
367 slot_id = 0;
368 for (i = 0; i < MAX_HC_SLOTS; i++) {
369 if (!xhci->devs[i] || !xhci->devs[i]->udev)
370 continue;
371 speed = xhci->devs[i]->udev->speed;
372 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
373 && xhci->devs[i]->fake_port == port) {
374 slot_id = i;
375 break;
376 }
377 }
378
379 return slot_id;
380 }
381
382 /*
383 * Stop device
384 * It issues stop endpoint command for EP 0 to 30. And wait the last command
385 * to complete.
386 * suspend will set to 1, if suspend bit need to set in command.
387 */
xhci_stop_device(struct xhci_hcd * xhci,int slot_id,int suspend)388 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
389 {
390 struct xhci_virt_device *virt_dev;
391 struct xhci_command *cmd;
392 unsigned long flags;
393 int ret;
394 int i;
395
396 ret = 0;
397 virt_dev = xhci->devs[slot_id];
398 if (!virt_dev)
399 return -ENODEV;
400
401 trace_xhci_stop_device(virt_dev);
402
403 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
404 if (!cmd)
405 return -ENOMEM;
406
407 spin_lock_irqsave(&xhci->lock, flags);
408 for (i = LAST_EP_INDEX; i > 0; i--) {
409 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
410 struct xhci_ep_ctx *ep_ctx;
411 struct xhci_command *command;
412
413 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
414
415 /* Check ep is running, required by AMD SNPS 3.1 xHC */
416 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
417 continue;
418
419 command = xhci_alloc_command(xhci, false, false,
420 GFP_NOWAIT);
421 if (!command) {
422 spin_unlock_irqrestore(&xhci->lock, flags);
423 ret = -ENOMEM;
424 goto cmd_cleanup;
425 }
426
427 ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
428 i, suspend);
429 if (ret) {
430 spin_unlock_irqrestore(&xhci->lock, flags);
431 xhci_free_command(xhci, command);
432 goto cmd_cleanup;
433 }
434 }
435 }
436 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
437 if (ret) {
438 spin_unlock_irqrestore(&xhci->lock, flags);
439 goto cmd_cleanup;
440 }
441
442 xhci_ring_cmd_db(xhci);
443 spin_unlock_irqrestore(&xhci->lock, flags);
444
445 /* Wait for last stop endpoint command to finish */
446 wait_for_completion(cmd->completion);
447
448 if (cmd->status == COMP_COMMAND_ABORTED ||
449 cmd->status == COMP_COMMAND_RING_STOPPED) {
450 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
451 ret = -ETIME;
452 }
453
454 cmd_cleanup:
455 xhci_free_command(xhci, cmd);
456 return ret;
457 }
458
459 /*
460 * Ring device, it rings the all doorbells unconditionally.
461 */
xhci_ring_device(struct xhci_hcd * xhci,int slot_id)462 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
463 {
464 int i, s;
465 struct xhci_virt_ep *ep;
466
467 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
468 ep = &xhci->devs[slot_id]->eps[i];
469
470 if (ep->ep_state & EP_HAS_STREAMS) {
471 for (s = 1; s < ep->stream_info->num_streams; s++)
472 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
473 } else if (ep->ring && ep->ring->dequeue) {
474 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
475 }
476 }
477
478 return;
479 }
480
xhci_disable_port(struct usb_hcd * hcd,struct xhci_hcd * xhci,u16 wIndex,__le32 __iomem * addr,u32 port_status)481 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
482 u16 wIndex, __le32 __iomem *addr, u32 port_status)
483 {
484 /* Don't allow the USB core to disable SuperSpeed ports. */
485 if (hcd->speed >= HCD_USB3) {
486 xhci_dbg(xhci, "Ignoring request to disable "
487 "SuperSpeed port.\n");
488 return;
489 }
490
491 if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
492 xhci_dbg(xhci,
493 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
494 return;
495 }
496
497 /* Write 1 to disable the port */
498 writel(port_status | PORT_PE, addr);
499 port_status = readl(addr);
500 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
501 wIndex, port_status);
502 }
503
xhci_clear_port_change_bit(struct xhci_hcd * xhci,u16 wValue,u16 wIndex,__le32 __iomem * addr,u32 port_status)504 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
505 u16 wIndex, __le32 __iomem *addr, u32 port_status)
506 {
507 char *port_change_bit;
508 u32 status;
509
510 switch (wValue) {
511 case USB_PORT_FEAT_C_RESET:
512 status = PORT_RC;
513 port_change_bit = "reset";
514 break;
515 case USB_PORT_FEAT_C_BH_PORT_RESET:
516 status = PORT_WRC;
517 port_change_bit = "warm(BH) reset";
518 break;
519 case USB_PORT_FEAT_C_CONNECTION:
520 status = PORT_CSC;
521 port_change_bit = "connect";
522 break;
523 case USB_PORT_FEAT_C_OVER_CURRENT:
524 status = PORT_OCC;
525 port_change_bit = "over-current";
526 break;
527 case USB_PORT_FEAT_C_ENABLE:
528 status = PORT_PEC;
529 port_change_bit = "enable/disable";
530 break;
531 case USB_PORT_FEAT_C_SUSPEND:
532 status = PORT_PLC;
533 port_change_bit = "suspend/resume";
534 break;
535 case USB_PORT_FEAT_C_PORT_LINK_STATE:
536 status = PORT_PLC;
537 port_change_bit = "link state";
538 break;
539 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
540 status = PORT_CEC;
541 port_change_bit = "config error";
542 break;
543 default:
544 /* Should never happen */
545 return;
546 }
547 /* Change bits are all write 1 to clear */
548 writel(port_status | status, addr);
549 port_status = readl(addr);
550 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
551 port_change_bit, wIndex, port_status);
552 }
553
xhci_get_ports(struct usb_hcd * hcd,__le32 __iomem *** port_array)554 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
555 {
556 int max_ports;
557 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
558
559 if (hcd->speed >= HCD_USB3) {
560 max_ports = xhci->num_usb3_ports;
561 *port_array = xhci->usb3_ports;
562 } else {
563 max_ports = xhci->num_usb2_ports;
564 *port_array = xhci->usb2_ports;
565 }
566
567 return max_ports;
568 }
569
xhci_get_port_io_addr(struct usb_hcd * hcd,int index)570 static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index)
571 {
572 __le32 __iomem **port_array;
573
574 xhci_get_ports(hcd, &port_array);
575 return port_array[index];
576 }
577
578 /*
579 * xhci_set_port_power() must be called with xhci->lock held.
580 * It will release and re-aquire the lock while calling ACPI
581 * method.
582 */
xhci_set_port_power(struct xhci_hcd * xhci,struct usb_hcd * hcd,u16 index,bool on,unsigned long * flags)583 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
584 u16 index, bool on, unsigned long *flags)
585 {
586 __le32 __iomem *addr;
587 u32 temp;
588
589 addr = xhci_get_port_io_addr(hcd, index);
590 temp = readl(addr);
591 temp = xhci_port_state_to_neutral(temp);
592 if (on) {
593 /* Power on */
594 writel(temp | PORT_POWER, addr);
595 temp = readl(addr);
596 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n",
597 index, temp);
598 } else {
599 /* Power off */
600 writel(temp & ~PORT_POWER, addr);
601 }
602
603 spin_unlock_irqrestore(&xhci->lock, *flags);
604 temp = usb_acpi_power_manageable(hcd->self.root_hub,
605 index);
606 if (temp)
607 usb_acpi_set_power_state(hcd->self.root_hub,
608 index, on);
609 spin_lock_irqsave(&xhci->lock, *flags);
610 }
611
xhci_port_set_test_mode(struct xhci_hcd * xhci,u16 test_mode,u16 wIndex)612 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
613 u16 test_mode, u16 wIndex)
614 {
615 u32 temp;
616 __le32 __iomem *addr;
617
618 /* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */
619 addr = xhci_get_port_io_addr(xhci->main_hcd, wIndex);
620 temp = readl(addr + PORTPMSC);
621 temp |= test_mode << PORT_TEST_MODE_SHIFT;
622 writel(temp, addr + PORTPMSC);
623 xhci->test_mode = test_mode;
624 if (test_mode == TEST_FORCE_EN)
625 xhci_start(xhci);
626 }
627
xhci_enter_test_mode(struct xhci_hcd * xhci,u16 test_mode,u16 wIndex,unsigned long * flags)628 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
629 u16 test_mode, u16 wIndex, unsigned long *flags)
630 {
631 int i, retval;
632
633 /* Disable all Device Slots */
634 xhci_dbg(xhci, "Disable all slots\n");
635 spin_unlock_irqrestore(&xhci->lock, *flags);
636 for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
637 if (!xhci->devs[i])
638 continue;
639
640 retval = xhci_disable_slot(xhci, i);
641 if (retval)
642 xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
643 i, retval);
644 }
645 spin_lock_irqsave(&xhci->lock, *flags);
646 /* Put all ports to the Disable state by clear PP */
647 xhci_dbg(xhci, "Disable all port (PP = 0)\n");
648 /* Power off USB3 ports*/
649 for (i = 0; i < xhci->num_usb3_ports; i++)
650 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
651 /* Power off USB2 ports*/
652 for (i = 0; i < xhci->num_usb2_ports; i++)
653 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
654 /* Stop the controller */
655 xhci_dbg(xhci, "Stop controller\n");
656 retval = xhci_halt(xhci);
657 if (retval)
658 return retval;
659 /* Disable runtime PM for test mode */
660 pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
661 /* Set PORTPMSC.PTC field to enter selected test mode */
662 /* Port is selected by wIndex. port_id = wIndex + 1 */
663 xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
664 test_mode, wIndex + 1);
665 xhci_port_set_test_mode(xhci, test_mode, wIndex);
666 return retval;
667 }
668
xhci_exit_test_mode(struct xhci_hcd * xhci)669 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
670 {
671 int retval;
672
673 if (!xhci->test_mode) {
674 xhci_err(xhci, "Not in test mode, do nothing.\n");
675 return 0;
676 }
677 if (xhci->test_mode == TEST_FORCE_EN &&
678 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
679 retval = xhci_halt(xhci);
680 if (retval)
681 return retval;
682 }
683 pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
684 xhci->test_mode = 0;
685 return xhci_reset(xhci);
686 }
687
xhci_set_link_state(struct xhci_hcd * xhci,__le32 __iomem ** port_array,int port_id,u32 link_state)688 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
689 int port_id, u32 link_state)
690 {
691 u32 temp;
692
693 temp = readl(port_array[port_id]);
694 temp = xhci_port_state_to_neutral(temp);
695 temp &= ~PORT_PLS_MASK;
696 temp |= PORT_LINK_STROBE | link_state;
697 writel(temp, port_array[port_id]);
698 }
699
xhci_set_remote_wake_mask(struct xhci_hcd * xhci,__le32 __iomem ** port_array,int port_id,u16 wake_mask)700 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
701 __le32 __iomem **port_array, int port_id, u16 wake_mask)
702 {
703 u32 temp;
704
705 temp = readl(port_array[port_id]);
706 temp = xhci_port_state_to_neutral(temp);
707
708 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
709 temp |= PORT_WKCONN_E;
710 else
711 temp &= ~PORT_WKCONN_E;
712
713 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
714 temp |= PORT_WKDISC_E;
715 else
716 temp &= ~PORT_WKDISC_E;
717
718 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
719 temp |= PORT_WKOC_E;
720 else
721 temp &= ~PORT_WKOC_E;
722
723 writel(temp, port_array[port_id]);
724 }
725
726 /* Test and clear port RWC bit */
xhci_test_and_clear_bit(struct xhci_hcd * xhci,__le32 __iomem ** port_array,int port_id,u32 port_bit)727 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
728 int port_id, u32 port_bit)
729 {
730 u32 temp;
731
732 temp = readl(port_array[port_id]);
733 if (temp & port_bit) {
734 temp = xhci_port_state_to_neutral(temp);
735 temp |= port_bit;
736 writel(temp, port_array[port_id]);
737 }
738 }
739
740 /* Updates Link Status for USB 2.1 port */
xhci_hub_report_usb2_link_state(u32 * status,u32 status_reg)741 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
742 {
743 if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
744 *status |= USB_PORT_STAT_L1;
745 }
746
747 /* Updates Link Status for super Speed port */
xhci_hub_report_usb3_link_state(struct xhci_hcd * xhci,u32 * status,u32 status_reg)748 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
749 u32 *status, u32 status_reg)
750 {
751 u32 pls = status_reg & PORT_PLS_MASK;
752
753 /* resume state is a xHCI internal state.
754 * Do not report it to usb core, instead, pretend to be U3,
755 * thus usb core knows it's not ready for transfer
756 */
757 if (pls == XDEV_RESUME) {
758 *status |= USB_SS_PORT_LS_U3;
759 return;
760 }
761
762 /* When the CAS bit is set then warm reset
763 * should be performed on port
764 */
765 if (status_reg & PORT_CAS) {
766 /* The CAS bit can be set while the port is
767 * in any link state.
768 * Only roothubs have CAS bit, so we
769 * pretend to be in compliance mode
770 * unless we're already in compliance
771 * or the inactive state.
772 */
773 if (pls != USB_SS_PORT_LS_COMP_MOD &&
774 pls != USB_SS_PORT_LS_SS_INACTIVE) {
775 pls = USB_SS_PORT_LS_COMP_MOD;
776 }
777 /* Return also connection bit -
778 * hub state machine resets port
779 * when this bit is set.
780 */
781 pls |= USB_PORT_STAT_CONNECTION;
782 } else {
783 /*
784 * If CAS bit isn't set but the Port is already at
785 * Compliance Mode, fake a connection so the USB core
786 * notices the Compliance state and resets the port.
787 * This resolves an issue generated by the SN65LVPE502CP
788 * in which sometimes the port enters compliance mode
789 * caused by a delay on the host-device negotiation.
790 */
791 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
792 (pls == USB_SS_PORT_LS_COMP_MOD))
793 pls |= USB_PORT_STAT_CONNECTION;
794 }
795
796 /* update status field */
797 *status |= pls;
798 }
799
800 /*
801 * Function for Compliance Mode Quirk.
802 *
803 * This Function verifies if all xhc USB3 ports have entered U0, if so,
804 * the compliance mode timer is deleted. A port won't enter
805 * compliance mode if it has previously entered U0.
806 */
xhci_del_comp_mod_timer(struct xhci_hcd * xhci,u32 status,u16 wIndex)807 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
808 u16 wIndex)
809 {
810 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
811 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
812
813 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
814 return;
815
816 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
817 xhci->port_status_u0 |= 1 << wIndex;
818 if (xhci->port_status_u0 == all_ports_seen_u0) {
819 del_timer_sync(&xhci->comp_mode_recovery_timer);
820 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
821 "All USB3 ports have entered U0 already!");
822 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
823 "Compliance Mode Recovery Timer Deleted.");
824 }
825 }
826 }
827
xhci_get_ext_port_status(u32 raw_port_status,u32 port_li)828 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
829 {
830 u32 ext_stat = 0;
831 int speed_id;
832
833 /* only support rx and tx lane counts of 1 in usb3.1 spec */
834 speed_id = DEV_PORT_SPEED(raw_port_status);
835 ext_stat |= speed_id; /* bits 3:0, RX speed id */
836 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
837
838 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
839 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
840
841 return ext_stat;
842 }
843
844 /*
845 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
846 * 3.0 hubs use.
847 *
848 * Possible side effects:
849 * - Mark a port as being done with device resume,
850 * and ring the endpoint doorbells.
851 * - Stop the Synopsys redriver Compliance Mode polling.
852 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
853 */
xhci_get_port_status(struct usb_hcd * hcd,struct xhci_bus_state * bus_state,__le32 __iomem ** port_array,u16 wIndex,u32 raw_port_status,unsigned long * flags)854 static u32 xhci_get_port_status(struct usb_hcd *hcd,
855 struct xhci_bus_state *bus_state,
856 __le32 __iomem **port_array,
857 u16 wIndex, u32 raw_port_status,
858 unsigned long *flags)
859 __releases(&xhci->lock)
860 __acquires(&xhci->lock)
861 {
862 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
863 u32 status = 0;
864 int slot_id;
865
866 /* wPortChange bits */
867 if (raw_port_status & PORT_CSC)
868 status |= USB_PORT_STAT_C_CONNECTION << 16;
869 if (raw_port_status & PORT_PEC)
870 status |= USB_PORT_STAT_C_ENABLE << 16;
871 if ((raw_port_status & PORT_OCC))
872 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
873 if ((raw_port_status & PORT_RC))
874 status |= USB_PORT_STAT_C_RESET << 16;
875 /* USB3.0 only */
876 if (hcd->speed >= HCD_USB3) {
877 /* Port link change with port in resume state should not be
878 * reported to usbcore, as this is an internal state to be
879 * handled by xhci driver. Reporting PLC to usbcore may
880 * cause usbcore clearing PLC first and port change event
881 * irq won't be generated.
882 */
883 if ((raw_port_status & PORT_PLC) &&
884 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
885 status |= USB_PORT_STAT_C_LINK_STATE << 16;
886 if ((raw_port_status & PORT_WRC))
887 status |= USB_PORT_STAT_C_BH_RESET << 16;
888 if ((raw_port_status & PORT_CEC))
889 status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
890
891 /* USB3 remote wake resume signaling completed */
892 if (bus_state->port_remote_wakeup & (1 << wIndex) &&
893 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME &&
894 (raw_port_status & PORT_PLS_MASK) != XDEV_RECOVERY) {
895 bus_state->port_remote_wakeup &= ~(1 << wIndex);
896 usb_hcd_end_port_resume(&hcd->self, wIndex);
897 }
898 }
899
900 if (hcd->speed < HCD_USB3) {
901 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
902 && (raw_port_status & PORT_POWER))
903 status |= USB_PORT_STAT_SUSPEND;
904 }
905 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
906 !DEV_SUPERSPEED_ANY(raw_port_status) && hcd->speed < HCD_USB3) {
907 if ((raw_port_status & PORT_RESET) ||
908 !(raw_port_status & PORT_PE))
909 return 0xffffffff;
910 /* did port event handler already start resume timing? */
911 if (!bus_state->resume_done[wIndex]) {
912 /* If not, maybe we are in a host initated resume? */
913 if (test_bit(wIndex, &bus_state->resuming_ports)) {
914 /* Host initated resume doesn't time the resume
915 * signalling using resume_done[].
916 * It manually sets RESUME state, sleeps 20ms
917 * and sets U0 state. This should probably be
918 * changed, but not right now.
919 */
920 } else {
921 /* port resume was discovered now and here,
922 * start resume timing
923 */
924 unsigned long timeout = jiffies +
925 msecs_to_jiffies(USB_RESUME_TIMEOUT);
926
927 set_bit(wIndex, &bus_state->resuming_ports);
928 bus_state->resume_done[wIndex] = timeout;
929 mod_timer(&hcd->rh_timer, timeout);
930 }
931 /* Has resume been signalled for USB_RESUME_TIME yet? */
932 } else if (time_after_eq(jiffies,
933 bus_state->resume_done[wIndex])) {
934 int time_left;
935
936 xhci_dbg(xhci, "Resume USB2 port %d\n",
937 wIndex + 1);
938 bus_state->resume_done[wIndex] = 0;
939 clear_bit(wIndex, &bus_state->resuming_ports);
940
941 set_bit(wIndex, &bus_state->rexit_ports);
942
943 xhci_test_and_clear_bit(xhci, port_array, wIndex,
944 PORT_PLC);
945 xhci_set_link_state(xhci, port_array, wIndex,
946 XDEV_U0);
947
948 spin_unlock_irqrestore(&xhci->lock, *flags);
949 time_left = wait_for_completion_timeout(
950 &bus_state->rexit_done[wIndex],
951 msecs_to_jiffies(
952 XHCI_MAX_REXIT_TIMEOUT_MS));
953 spin_lock_irqsave(&xhci->lock, *flags);
954
955 if (time_left) {
956 slot_id = xhci_find_slot_id_by_port(hcd,
957 xhci, wIndex + 1);
958 if (!slot_id) {
959 xhci_dbg(xhci, "slot_id is zero\n");
960 return 0xffffffff;
961 }
962 xhci_ring_device(xhci, slot_id);
963 } else {
964 int port_status = readl(port_array[wIndex]);
965 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
966 XHCI_MAX_REXIT_TIMEOUT_MS,
967 port_status);
968 status |= USB_PORT_STAT_SUSPEND;
969 clear_bit(wIndex, &bus_state->rexit_ports);
970 }
971
972 bus_state->port_c_suspend |= 1 << wIndex;
973 bus_state->suspended_ports &= ~(1 << wIndex);
974 } else {
975 /*
976 * The resume has been signaling for less than
977 * USB_RESUME_TIME. Report the port status as SUSPEND,
978 * let the usbcore check port status again and clear
979 * resume signaling later.
980 */
981 status |= USB_PORT_STAT_SUSPEND;
982 }
983 }
984 /*
985 * Clear stale usb2 resume signalling variables in case port changed
986 * state during resume signalling. For example on error
987 */
988 if ((bus_state->resume_done[wIndex] ||
989 test_bit(wIndex, &bus_state->resuming_ports)) &&
990 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
991 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
992 bus_state->resume_done[wIndex] = 0;
993 clear_bit(wIndex, &bus_state->resuming_ports);
994 }
995
996
997 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
998 (raw_port_status & PORT_POWER)) {
999 if (bus_state->suspended_ports & (1 << wIndex)) {
1000 bus_state->suspended_ports &= ~(1 << wIndex);
1001 if (hcd->speed < HCD_USB3)
1002 bus_state->port_c_suspend |= 1 << wIndex;
1003 }
1004 bus_state->resume_done[wIndex] = 0;
1005 clear_bit(wIndex, &bus_state->resuming_ports);
1006 }
1007 if (raw_port_status & PORT_CONNECT) {
1008 status |= USB_PORT_STAT_CONNECTION;
1009 status |= xhci_port_speed(raw_port_status);
1010 }
1011 if (raw_port_status & PORT_PE)
1012 status |= USB_PORT_STAT_ENABLE;
1013 if (raw_port_status & PORT_OC)
1014 status |= USB_PORT_STAT_OVERCURRENT;
1015 if (raw_port_status & PORT_RESET)
1016 status |= USB_PORT_STAT_RESET;
1017 if (raw_port_status & PORT_POWER) {
1018 if (hcd->speed >= HCD_USB3)
1019 status |= USB_SS_PORT_STAT_POWER;
1020 else
1021 status |= USB_PORT_STAT_POWER;
1022 }
1023 /* Update Port Link State */
1024 if (hcd->speed >= HCD_USB3) {
1025 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
1026 /*
1027 * Verify if all USB3 Ports Have entered U0 already.
1028 * Delete Compliance Mode Timer if so.
1029 */
1030 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
1031 } else {
1032 xhci_hub_report_usb2_link_state(&status, raw_port_status);
1033 }
1034 if (bus_state->port_c_suspend & (1 << wIndex))
1035 status |= USB_PORT_STAT_C_SUSPEND << 16;
1036
1037 return status;
1038 }
1039
xhci_hub_control(struct usb_hcd * hcd,u16 typeReq,u16 wValue,u16 wIndex,char * buf,u16 wLength)1040 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1041 u16 wIndex, char *buf, u16 wLength)
1042 {
1043 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1044 int max_ports;
1045 unsigned long flags;
1046 u32 temp, status;
1047 int retval = 0;
1048 __le32 __iomem **port_array;
1049 int slot_id;
1050 struct xhci_bus_state *bus_state;
1051 u16 link_state = 0;
1052 u16 wake_mask = 0;
1053 u16 timeout = 0;
1054 u16 test_mode = 0;
1055
1056 max_ports = xhci_get_ports(hcd, &port_array);
1057 bus_state = &xhci->bus_state[hcd_index(hcd)];
1058
1059 spin_lock_irqsave(&xhci->lock, flags);
1060 switch (typeReq) {
1061 case GetHubStatus:
1062 /* No power source, over-current reported per port */
1063 memset(buf, 0, 4);
1064 break;
1065 case GetHubDescriptor:
1066 /* Check to make sure userspace is asking for the USB 3.0 hub
1067 * descriptor for the USB 3.0 roothub. If not, we stall the
1068 * endpoint, like external hubs do.
1069 */
1070 if (hcd->speed >= HCD_USB3 &&
1071 (wLength < USB_DT_SS_HUB_SIZE ||
1072 wValue != (USB_DT_SS_HUB << 8))) {
1073 xhci_dbg(xhci, "Wrong hub descriptor type for "
1074 "USB 3.0 roothub.\n");
1075 goto error;
1076 }
1077 xhci_hub_descriptor(hcd, xhci,
1078 (struct usb_hub_descriptor *) buf);
1079 break;
1080 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1081 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1082 goto error;
1083
1084 if (hcd->speed < HCD_USB3)
1085 goto error;
1086
1087 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1088 spin_unlock_irqrestore(&xhci->lock, flags);
1089 return retval;
1090 case GetPortStatus:
1091 if (!wIndex || wIndex > max_ports)
1092 goto error;
1093 wIndex--;
1094 temp = readl(port_array[wIndex]);
1095 if (temp == ~(u32)0) {
1096 xhci_hc_died(xhci);
1097 retval = -ENODEV;
1098 break;
1099 }
1100 status = xhci_get_port_status(hcd, bus_state, port_array,
1101 wIndex, temp, &flags);
1102 if (status == 0xffffffff)
1103 goto error;
1104
1105 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
1106 wIndex, temp);
1107 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
1108
1109 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1110 /* if USB 3.1 extended port status return additional 4 bytes */
1111 if (wValue == 0x02) {
1112 u32 port_li;
1113
1114 if (hcd->speed < HCD_USB31 || wLength != 8) {
1115 xhci_err(xhci, "get ext port status invalid parameter\n");
1116 retval = -EINVAL;
1117 break;
1118 }
1119 port_li = readl(port_array[wIndex] + PORTLI);
1120 status = xhci_get_ext_port_status(temp, port_li);
1121 put_unaligned_le32(status, &buf[4]);
1122 }
1123 break;
1124 case SetPortFeature:
1125 if (wValue == USB_PORT_FEAT_LINK_STATE)
1126 link_state = (wIndex & 0xff00) >> 3;
1127 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1128 wake_mask = wIndex & 0xff00;
1129 if (wValue == USB_PORT_FEAT_TEST)
1130 test_mode = (wIndex & 0xff00) >> 8;
1131 /* The MSB of wIndex is the U1/U2 timeout */
1132 timeout = (wIndex & 0xff00) >> 8;
1133 wIndex &= 0xff;
1134 if (!wIndex || wIndex > max_ports)
1135 goto error;
1136 wIndex--;
1137 temp = readl(port_array[wIndex]);
1138 if (temp == ~(u32)0) {
1139 xhci_hc_died(xhci);
1140 retval = -ENODEV;
1141 break;
1142 }
1143 temp = xhci_port_state_to_neutral(temp);
1144 /* FIXME: What new port features do we need to support? */
1145 switch (wValue) {
1146 case USB_PORT_FEAT_SUSPEND:
1147 temp = readl(port_array[wIndex]);
1148 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1149 /* Resume the port to U0 first */
1150 xhci_set_link_state(xhci, port_array, wIndex,
1151 XDEV_U0);
1152 spin_unlock_irqrestore(&xhci->lock, flags);
1153 msleep(10);
1154 spin_lock_irqsave(&xhci->lock, flags);
1155 }
1156 /* In spec software should not attempt to suspend
1157 * a port unless the port reports that it is in the
1158 * enabled (PED = ‘1’,PLS < ‘3’) state.
1159 */
1160 temp = readl(port_array[wIndex]);
1161 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1162 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1163 xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
1164 goto error;
1165 }
1166
1167 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1168 wIndex + 1);
1169 if (!slot_id) {
1170 xhci_warn(xhci, "slot_id is zero\n");
1171 goto error;
1172 }
1173 /* unlock to execute stop endpoint commands */
1174 spin_unlock_irqrestore(&xhci->lock, flags);
1175 xhci_stop_device(xhci, slot_id, 1);
1176 spin_lock_irqsave(&xhci->lock, flags);
1177
1178 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1179
1180 spin_unlock_irqrestore(&xhci->lock, flags);
1181 msleep(10); /* wait device to enter */
1182 spin_lock_irqsave(&xhci->lock, flags);
1183
1184 temp = readl(port_array[wIndex]);
1185 bus_state->suspended_ports |= 1 << wIndex;
1186 break;
1187 case USB_PORT_FEAT_LINK_STATE:
1188 temp = readl(port_array[wIndex]);
1189
1190 /* Disable port */
1191 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1192 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1193 temp = xhci_port_state_to_neutral(temp);
1194 /*
1195 * Clear all change bits, so that we get a new
1196 * connection event.
1197 */
1198 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1199 PORT_OCC | PORT_RC | PORT_PLC |
1200 PORT_CEC;
1201 writel(temp | PORT_PE, port_array[wIndex]);
1202 temp = readl(port_array[wIndex]);
1203 break;
1204 }
1205
1206 /* Put link in RxDetect (enable port) */
1207 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1208 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1209 xhci_set_link_state(xhci, port_array, wIndex,
1210 link_state);
1211 temp = readl(port_array[wIndex]);
1212 break;
1213 }
1214
1215 /*
1216 * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1217 * root hub port's transition to compliance mode upon
1218 * detecting LFPS timeout may be controlled by an
1219 * Compliance Transition Enabled (CTE) flag (not
1220 * software visible). This flag is set by writing 0xA
1221 * to PORTSC PLS field which will allow transition to
1222 * compliance mode the next time LFPS timeout is
1223 * encountered. A warm reset will clear it.
1224 *
1225 * The CTE flag is only supported if the HCCPARAMS2 CTC
1226 * flag is set, otherwise, the compliance substate is
1227 * automatically entered as on 1.0 and prior.
1228 */
1229 if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1230 if (!HCC2_CTC(xhci->hcc_params2)) {
1231 xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1232 break;
1233 }
1234
1235 if ((temp & PORT_CONNECT)) {
1236 xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1237 goto error;
1238 }
1239
1240 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1241 wIndex);
1242 xhci_set_link_state(xhci, port_array, wIndex,
1243 link_state);
1244 temp = readl(port_array[wIndex]);
1245 break;
1246 }
1247 /* Port must be enabled */
1248 if (!(temp & PORT_PE)) {
1249 retval = -ENODEV;
1250 break;
1251 }
1252 /* Can't set port link state above '3' (U3) */
1253 if (link_state > USB_SS_PORT_LS_U3) {
1254 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1255 wIndex, link_state);
1256 goto error;
1257 }
1258 if (link_state == USB_SS_PORT_LS_U3) {
1259 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1260 wIndex + 1);
1261 if (slot_id) {
1262 /* unlock to execute stop endpoint
1263 * commands */
1264 spin_unlock_irqrestore(&xhci->lock,
1265 flags);
1266 xhci_stop_device(xhci, slot_id, 1);
1267 spin_lock_irqsave(&xhci->lock, flags);
1268 }
1269 }
1270
1271 xhci_set_link_state(xhci, port_array, wIndex,
1272 link_state);
1273
1274 spin_unlock_irqrestore(&xhci->lock, flags);
1275 msleep(20); /* wait device to enter */
1276 spin_lock_irqsave(&xhci->lock, flags);
1277
1278 temp = readl(port_array[wIndex]);
1279 if (link_state == USB_SS_PORT_LS_U3)
1280 bus_state->suspended_ports |= 1 << wIndex;
1281 break;
1282 case USB_PORT_FEAT_POWER:
1283 /*
1284 * Turn on ports, even if there isn't per-port switching.
1285 * HC will report connect events even before this is set.
1286 * However, hub_wq will ignore the roothub events until
1287 * the roothub is registered.
1288 */
1289 xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1290 break;
1291 case USB_PORT_FEAT_RESET:
1292 temp = (temp | PORT_RESET);
1293 writel(temp, port_array[wIndex]);
1294
1295 temp = readl(port_array[wIndex]);
1296 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
1297 break;
1298 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1299 xhci_set_remote_wake_mask(xhci, port_array,
1300 wIndex, wake_mask);
1301 temp = readl(port_array[wIndex]);
1302 xhci_dbg(xhci, "set port remote wake mask, "
1303 "actual port %d status = 0x%x\n",
1304 wIndex, temp);
1305 break;
1306 case USB_PORT_FEAT_BH_PORT_RESET:
1307 temp |= PORT_WR;
1308 writel(temp, port_array[wIndex]);
1309
1310 temp = readl(port_array[wIndex]);
1311 break;
1312 case USB_PORT_FEAT_U1_TIMEOUT:
1313 if (hcd->speed < HCD_USB3)
1314 goto error;
1315 temp = readl(port_array[wIndex] + PORTPMSC);
1316 temp &= ~PORT_U1_TIMEOUT_MASK;
1317 temp |= PORT_U1_TIMEOUT(timeout);
1318 writel(temp, port_array[wIndex] + PORTPMSC);
1319 break;
1320 case USB_PORT_FEAT_U2_TIMEOUT:
1321 if (hcd->speed < HCD_USB3)
1322 goto error;
1323 temp = readl(port_array[wIndex] + PORTPMSC);
1324 temp &= ~PORT_U2_TIMEOUT_MASK;
1325 temp |= PORT_U2_TIMEOUT(timeout);
1326 writel(temp, port_array[wIndex] + PORTPMSC);
1327 break;
1328 case USB_PORT_FEAT_TEST:
1329 /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1330 if (hcd->speed != HCD_USB2)
1331 goto error;
1332 if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1333 goto error;
1334 retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1335 &flags);
1336 break;
1337 default:
1338 goto error;
1339 }
1340 /* unblock any posted writes */
1341 temp = readl(port_array[wIndex]);
1342 break;
1343 case ClearPortFeature:
1344 if (!wIndex || wIndex > max_ports)
1345 goto error;
1346 wIndex--;
1347 temp = readl(port_array[wIndex]);
1348 if (temp == ~(u32)0) {
1349 xhci_hc_died(xhci);
1350 retval = -ENODEV;
1351 break;
1352 }
1353 /* FIXME: What new port features do we need to support? */
1354 temp = xhci_port_state_to_neutral(temp);
1355 switch (wValue) {
1356 case USB_PORT_FEAT_SUSPEND:
1357 temp = readl(port_array[wIndex]);
1358 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1359 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1360 if (temp & PORT_RESET)
1361 goto error;
1362 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1363 if ((temp & PORT_PE) == 0)
1364 goto error;
1365
1366 set_bit(wIndex, &bus_state->resuming_ports);
1367 xhci_set_link_state(xhci, port_array, wIndex,
1368 XDEV_RESUME);
1369 spin_unlock_irqrestore(&xhci->lock, flags);
1370 msleep(USB_RESUME_TIMEOUT);
1371 spin_lock_irqsave(&xhci->lock, flags);
1372 xhci_set_link_state(xhci, port_array, wIndex,
1373 XDEV_U0);
1374 clear_bit(wIndex, &bus_state->resuming_ports);
1375 }
1376 bus_state->port_c_suspend |= 1 << wIndex;
1377
1378 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1379 wIndex + 1);
1380 if (!slot_id) {
1381 xhci_dbg(xhci, "slot_id is zero\n");
1382 goto error;
1383 }
1384 xhci_ring_device(xhci, slot_id);
1385 break;
1386 case USB_PORT_FEAT_C_SUSPEND:
1387 bus_state->port_c_suspend &= ~(1 << wIndex);
1388 case USB_PORT_FEAT_C_RESET:
1389 case USB_PORT_FEAT_C_BH_PORT_RESET:
1390 case USB_PORT_FEAT_C_CONNECTION:
1391 case USB_PORT_FEAT_C_OVER_CURRENT:
1392 case USB_PORT_FEAT_C_ENABLE:
1393 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1394 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1395 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1396 port_array[wIndex], temp);
1397 break;
1398 case USB_PORT_FEAT_ENABLE:
1399 xhci_disable_port(hcd, xhci, wIndex,
1400 port_array[wIndex], temp);
1401 break;
1402 case USB_PORT_FEAT_POWER:
1403 xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1404 break;
1405 case USB_PORT_FEAT_TEST:
1406 retval = xhci_exit_test_mode(xhci);
1407 break;
1408 default:
1409 goto error;
1410 }
1411 break;
1412 default:
1413 error:
1414 /* "stall" on error */
1415 retval = -EPIPE;
1416 }
1417 spin_unlock_irqrestore(&xhci->lock, flags);
1418 return retval;
1419 }
1420
1421 /*
1422 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1423 * Ports are 0-indexed from the HCD point of view,
1424 * and 1-indexed from the USB core pointer of view.
1425 *
1426 * Note that the status change bits will be cleared as soon as a port status
1427 * change event is generated, so we use the saved status from that event.
1428 */
xhci_hub_status_data(struct usb_hcd * hcd,char * buf)1429 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1430 {
1431 unsigned long flags;
1432 u32 temp, status;
1433 u32 mask;
1434 int i, retval;
1435 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1436 int max_ports;
1437 __le32 __iomem **port_array;
1438 struct xhci_bus_state *bus_state;
1439 bool reset_change = false;
1440
1441 max_ports = xhci_get_ports(hcd, &port_array);
1442 bus_state = &xhci->bus_state[hcd_index(hcd)];
1443
1444 /* Initial status is no changes */
1445 retval = (max_ports + 8) / 8;
1446 memset(buf, 0, retval);
1447
1448 /*
1449 * Inform the usbcore about resume-in-progress by returning
1450 * a non-zero value even if there are no status changes.
1451 */
1452 status = bus_state->resuming_ports;
1453
1454 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1455
1456 spin_lock_irqsave(&xhci->lock, flags);
1457 /* For each port, did anything change? If so, set that bit in buf. */
1458 for (i = 0; i < max_ports; i++) {
1459 temp = readl(port_array[i]);
1460 if (temp == ~(u32)0) {
1461 xhci_hc_died(xhci);
1462 retval = -ENODEV;
1463 break;
1464 }
1465 if ((temp & mask) != 0 ||
1466 (bus_state->port_c_suspend & 1 << i) ||
1467 (bus_state->resume_done[i] && time_after_eq(
1468 jiffies, bus_state->resume_done[i]))) {
1469 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1470 status = 1;
1471 }
1472 if ((temp & PORT_RC))
1473 reset_change = true;
1474 }
1475 if (!status && !reset_change) {
1476 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1477 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1478 }
1479 spin_unlock_irqrestore(&xhci->lock, flags);
1480 return status ? retval : 0;
1481 }
1482
1483 #ifdef CONFIG_PM
1484
xhci_bus_suspend(struct usb_hcd * hcd)1485 int xhci_bus_suspend(struct usb_hcd *hcd)
1486 {
1487 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1488 int max_ports, port_index;
1489 __le32 __iomem **port_array;
1490 struct xhci_bus_state *bus_state;
1491 unsigned long flags;
1492 u32 portsc_buf[USB_MAXCHILDREN];
1493 bool wake_enabled;
1494
1495 max_ports = xhci_get_ports(hcd, &port_array);
1496 bus_state = &xhci->bus_state[hcd_index(hcd)];
1497 wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1498
1499 spin_lock_irqsave(&xhci->lock, flags);
1500
1501 if (wake_enabled) {
1502 if (bus_state->resuming_ports || /* USB2 */
1503 bus_state->port_remote_wakeup) { /* USB3 */
1504 spin_unlock_irqrestore(&xhci->lock, flags);
1505 xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1506 return -EBUSY;
1507 }
1508 }
1509 /*
1510 * Prepare ports for suspend, but don't write anything before all ports
1511 * are checked and we know bus suspend can proceed
1512 */
1513 bus_state->bus_suspended = 0;
1514 port_index = max_ports;
1515 while (port_index--) {
1516 u32 t1, t2;
1517
1518 t1 = readl(port_array[port_index]);
1519 t2 = xhci_port_state_to_neutral(t1);
1520 portsc_buf[port_index] = 0;
1521
1522 /* Bail out if a USB3 port has a new device in link training */
1523 if ((hcd->speed >= HCD_USB3) &&
1524 (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1525 bus_state->bus_suspended = 0;
1526 spin_unlock_irqrestore(&xhci->lock, flags);
1527 xhci_dbg(xhci, "Bus suspend bailout, port in polling\n");
1528 return -EBUSY;
1529 }
1530
1531 /* suspend ports in U0, or bail out for new connect changes */
1532 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1533 if ((t1 & PORT_CSC) && wake_enabled) {
1534 bus_state->bus_suspended = 0;
1535 spin_unlock_irqrestore(&xhci->lock, flags);
1536 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1537 return -EBUSY;
1538 }
1539 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1540 t2 &= ~PORT_PLS_MASK;
1541 t2 |= PORT_LINK_STROBE | XDEV_U3;
1542 set_bit(port_index, &bus_state->bus_suspended);
1543 }
1544 /* USB core sets remote wake mask for USB 3.0 hubs,
1545 * including the USB 3.0 roothub, but only if CONFIG_PM
1546 * is enabled, so also enable remote wake here.
1547 */
1548 if (wake_enabled) {
1549 if (t1 & PORT_CONNECT) {
1550 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1551 t2 &= ~PORT_WKCONN_E;
1552 } else {
1553 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1554 t2 &= ~PORT_WKDISC_E;
1555 }
1556
1557 if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1558 (hcd->speed < HCD_USB3)) {
1559 if (usb_amd_pt_check_port(hcd->self.controller,
1560 port_index))
1561 t2 &= ~PORT_WAKE_BITS;
1562 }
1563 } else
1564 t2 &= ~PORT_WAKE_BITS;
1565
1566 t1 = xhci_port_state_to_neutral(t1);
1567 if (t1 != t2)
1568 portsc_buf[port_index] = t2;
1569 }
1570
1571 /* write port settings, stopping and suspending ports if needed */
1572 port_index = max_ports;
1573 while (port_index--) {
1574 if (!portsc_buf[port_index])
1575 continue;
1576 if (test_bit(port_index, &bus_state->bus_suspended)) {
1577 int slot_id;
1578
1579 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1580 port_index + 1);
1581 if (slot_id) {
1582 spin_unlock_irqrestore(&xhci->lock, flags);
1583 xhci_stop_device(xhci, slot_id, 1);
1584 spin_lock_irqsave(&xhci->lock, flags);
1585 }
1586 }
1587 writel(portsc_buf[port_index], port_array[port_index]);
1588 }
1589 hcd->state = HC_STATE_SUSPENDED;
1590 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1591 spin_unlock_irqrestore(&xhci->lock, flags);
1592 return 0;
1593 }
1594
1595 /*
1596 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1597 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1598 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1599 */
xhci_port_missing_cas_quirk(int port_index,__le32 __iomem ** port_array)1600 static bool xhci_port_missing_cas_quirk(int port_index,
1601 __le32 __iomem **port_array)
1602 {
1603 u32 portsc;
1604
1605 portsc = readl(port_array[port_index]);
1606
1607 /* if any of these are set we are not stuck */
1608 if (portsc & (PORT_CONNECT | PORT_CAS))
1609 return false;
1610
1611 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1612 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1613 return false;
1614
1615 /* clear wakeup/change bits, and do a warm port reset */
1616 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1617 portsc |= PORT_WR;
1618 writel(portsc, port_array[port_index]);
1619 /* flush write */
1620 readl(port_array[port_index]);
1621 return true;
1622 }
1623
xhci_bus_resume(struct usb_hcd * hcd)1624 int xhci_bus_resume(struct usb_hcd *hcd)
1625 {
1626 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1627 struct xhci_bus_state *bus_state;
1628 __le32 __iomem **port_array;
1629 unsigned long flags;
1630 int max_ports, port_index;
1631 int slot_id;
1632 int sret;
1633 u32 next_state;
1634 u32 temp, portsc;
1635
1636 max_ports = xhci_get_ports(hcd, &port_array);
1637 bus_state = &xhci->bus_state[hcd_index(hcd)];
1638
1639 if (time_before(jiffies, bus_state->next_statechange))
1640 msleep(5);
1641
1642 spin_lock_irqsave(&xhci->lock, flags);
1643 if (!HCD_HW_ACCESSIBLE(hcd)) {
1644 spin_unlock_irqrestore(&xhci->lock, flags);
1645 return -ESHUTDOWN;
1646 }
1647
1648 /* delay the irqs */
1649 temp = readl(&xhci->op_regs->command);
1650 temp &= ~CMD_EIE;
1651 writel(temp, &xhci->op_regs->command);
1652
1653 /* bus specific resume for ports we suspended at bus_suspend */
1654 if (hcd->speed >= HCD_USB3)
1655 next_state = XDEV_U0;
1656 else
1657 next_state = XDEV_RESUME;
1658
1659 port_index = max_ports;
1660 while (port_index--) {
1661 portsc = readl(port_array[port_index]);
1662
1663 /* warm reset CAS limited ports stuck in polling/compliance */
1664 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1665 (hcd->speed >= HCD_USB3) &&
1666 xhci_port_missing_cas_quirk(port_index, port_array)) {
1667 xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1668 clear_bit(port_index, &bus_state->bus_suspended);
1669 continue;
1670 }
1671 /* resume if we suspended the link, and it is still suspended */
1672 if (test_bit(port_index, &bus_state->bus_suspended))
1673 switch (portsc & PORT_PLS_MASK) {
1674 case XDEV_U3:
1675 portsc = xhci_port_state_to_neutral(portsc);
1676 portsc &= ~PORT_PLS_MASK;
1677 portsc |= PORT_LINK_STROBE | next_state;
1678 break;
1679 case XDEV_RESUME:
1680 /* resume already initiated */
1681 break;
1682 default:
1683 /* not in a resumeable state, ignore it */
1684 clear_bit(port_index,
1685 &bus_state->bus_suspended);
1686 break;
1687 }
1688 /* disable wake for all ports, write new link state if needed */
1689 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1690 writel(portsc, port_array[port_index]);
1691 }
1692
1693 /* USB2 specific resume signaling delay and U0 link state transition */
1694 if (hcd->speed < HCD_USB3) {
1695 if (bus_state->bus_suspended) {
1696 spin_unlock_irqrestore(&xhci->lock, flags);
1697 msleep(USB_RESUME_TIMEOUT);
1698 spin_lock_irqsave(&xhci->lock, flags);
1699 }
1700 for_each_set_bit(port_index, &bus_state->bus_suspended,
1701 BITS_PER_LONG) {
1702 /* Clear PLC to poll it later for U0 transition */
1703 xhci_test_and_clear_bit(xhci, port_array, port_index,
1704 PORT_PLC);
1705 xhci_set_link_state(xhci, port_array, port_index,
1706 XDEV_U0);
1707 }
1708 }
1709
1710 /* poll for U0 link state complete, both USB2 and USB3 */
1711 for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1712 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1713 PORT_PLC, 10 * 1000);
1714 if (sret) {
1715 xhci_warn(xhci, "port %d resume PLC timeout\n",
1716 port_index);
1717 continue;
1718 }
1719 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1720 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1721 if (slot_id)
1722 xhci_ring_device(xhci, slot_id);
1723 }
1724 (void) readl(&xhci->op_regs->command);
1725
1726 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1727 /* re-enable irqs */
1728 temp = readl(&xhci->op_regs->command);
1729 temp |= CMD_EIE;
1730 writel(temp, &xhci->op_regs->command);
1731 temp = readl(&xhci->op_regs->command);
1732
1733 spin_unlock_irqrestore(&xhci->lock, flags);
1734 return 0;
1735 }
1736
1737 #endif /* CONFIG_PM */
1738