1 /*
2 * xHCI host controller driver PCI Bus Glue.
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/acpi.h>
27
28 #include "xhci.h"
29 #include "xhci-trace.h"
30
31 #define SSIC_PORT_NUM 2
32 #define SSIC_PORT_CFG2 0x880c
33 #define SSIC_PORT_CFG2_OFFSET 0x30
34 #define PROG_DONE (1 << 30)
35 #define SSIC_PORT_UNUSED (1 << 31)
36
37 /* Device for a quirk */
38 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
42
43 #define PCI_VENDOR_ID_ETRON 0x1b6f
44 #define PCI_DEVICE_ID_EJ168 0x7023
45
46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
48 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
49 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
52 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
53 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
54 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
55 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
56 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
57
58 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
59 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
60 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
61 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
62 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
63
64 static const char hcd_name[] = "xhci_hcd";
65
66 static struct hc_driver __read_mostly xhci_pci_hc_driver;
67
68 static int xhci_pci_setup(struct usb_hcd *hcd);
69
70 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
71 .reset = xhci_pci_setup,
72 };
73
74 /* called after powerup, by probe or system-pm "wakeup" */
xhci_pci_reinit(struct xhci_hcd * xhci,struct pci_dev * pdev)75 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
76 {
77 /*
78 * TODO: Implement finding debug ports later.
79 * TODO: see if there are any quirks that need to be added to handle
80 * new extended capabilities.
81 */
82
83 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
84 if (!pci_set_mwi(pdev))
85 xhci_dbg(xhci, "MWI active\n");
86
87 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
88 return 0;
89 }
90
xhci_pci_quirks(struct device * dev,struct xhci_hcd * xhci)91 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
92 {
93 struct pci_dev *pdev = to_pci_dev(dev);
94
95 /* Look for vendor-specific quirks */
96 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
97 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
98 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
99 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
100 pdev->revision == 0x0) {
101 xhci->quirks |= XHCI_RESET_EP_QUIRK;
102 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
103 "QUIRK: Fresco Logic xHC needs configure"
104 " endpoint cmd after reset endpoint");
105 }
106 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
107 pdev->revision == 0x4) {
108 xhci->quirks |= XHCI_SLOW_SUSPEND;
109 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
110 "QUIRK: Fresco Logic xHC revision %u"
111 "must be suspended extra slowly",
112 pdev->revision);
113 }
114 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
115 xhci->quirks |= XHCI_BROKEN_STREAMS;
116 /* Fresco Logic confirms: all revisions of this chip do not
117 * support MSI, even though some of them claim to in their PCI
118 * capabilities.
119 */
120 xhci->quirks |= XHCI_BROKEN_MSI;
121 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
122 "QUIRK: Fresco Logic revision %u "
123 "has broken MSI implementation",
124 pdev->revision);
125 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
126 }
127
128 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
129 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
130 xhci->quirks |= XHCI_BROKEN_STREAMS;
131
132 if (pdev->vendor == PCI_VENDOR_ID_NEC)
133 xhci->quirks |= XHCI_NEC_HOST;
134
135 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
136 xhci->quirks |= XHCI_AMD_0x96_HOST;
137
138 /* AMD PLL quirk */
139 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
140 xhci->quirks |= XHCI_AMD_PLL_FIX;
141
142 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
143 (pdev->device == 0x145c ||
144 pdev->device == 0x15e0 ||
145 pdev->device == 0x15e1 ||
146 pdev->device == 0x43bb))
147 xhci->quirks |= XHCI_SUSPEND_DELAY;
148
149 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
150 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
151 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
152
153 if (pdev->vendor == PCI_VENDOR_ID_AMD)
154 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
155
156 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
157 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
158 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
159 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
160 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
161 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
162
163 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
164 xhci->quirks |= XHCI_LPM_SUPPORT;
165 xhci->quirks |= XHCI_INTEL_HOST;
166 xhci->quirks |= XHCI_AVOID_BEI;
167 }
168 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
169 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
170 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
171 xhci->limit_active_eps = 64;
172 xhci->quirks |= XHCI_SW_BW_CHECKING;
173 /*
174 * PPT desktop boards DH77EB and DH77DF will power back on after
175 * a few seconds of being shutdown. The fix for this is to
176 * switch the ports from xHCI to EHCI on shutdown. We can't use
177 * DMI information to find those particular boards (since each
178 * vendor will change the board name), so we have to key off all
179 * PPT chipsets.
180 */
181 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
182 }
183 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
184 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
185 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
186 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
187 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
188 }
189 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
190 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
191 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
192 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
193 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
194 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
195 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
196 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
197 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
198 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
199 }
200 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
201 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
202 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
203 }
204 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
205 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
206 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
207 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
208 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
209 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
210 xhci->quirks |= XHCI_MISSING_CAS;
211
212 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
213 pdev->device == PCI_DEVICE_ID_EJ168) {
214 xhci->quirks |= XHCI_RESET_ON_RESUME;
215 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
216 xhci->quirks |= XHCI_BROKEN_STREAMS;
217 }
218 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
219 pdev->device == 0x0014)
220 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
221 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
222 pdev->device == 0x0015)
223 xhci->quirks |= XHCI_RESET_ON_RESUME;
224 if (pdev->vendor == PCI_VENDOR_ID_VIA)
225 xhci->quirks |= XHCI_RESET_ON_RESUME;
226
227 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
228 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
229 pdev->device == 0x3432)
230 xhci->quirks |= XHCI_BROKEN_STREAMS;
231
232 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
233 pdev->device == 0x1042)
234 xhci->quirks |= XHCI_BROKEN_STREAMS;
235 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
236 pdev->device == 0x1142)
237 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
238
239 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
240 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
241 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
242
243 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
244 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
245
246 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
247 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
248 pdev->device == 0x9026)
249 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
250
251 if (xhci->quirks & XHCI_RESET_ON_RESUME)
252 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
253 "QUIRK: Resetting on resume");
254 }
255
256 #ifdef CONFIG_ACPI
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)257 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
258 {
259 static const guid_t intel_dsm_guid =
260 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
261 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
262 union acpi_object *obj;
263
264 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
265 NULL);
266 ACPI_FREE(obj);
267 }
268 #else
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)269 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
270 #endif /* CONFIG_ACPI */
271
272 /* called during probe() after chip reset completes */
xhci_pci_setup(struct usb_hcd * hcd)273 static int xhci_pci_setup(struct usb_hcd *hcd)
274 {
275 struct xhci_hcd *xhci;
276 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
277 int retval;
278
279 xhci = hcd_to_xhci(hcd);
280 if (!xhci->sbrn)
281 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
282
283 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
284 if (retval)
285 return retval;
286
287 if (!usb_hcd_is_primary_hcd(hcd))
288 return 0;
289
290 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
291 xhci_pme_acpi_rtd3_enable(pdev);
292
293 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
294
295 /* Find any debug ports */
296 return xhci_pci_reinit(xhci, pdev);
297 }
298
299 /*
300 * We need to register our own PCI probe function (instead of the USB core's
301 * function) in order to create a second roothub under xHCI.
302 */
xhci_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)303 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
304 {
305 int retval;
306 struct xhci_hcd *xhci;
307 struct hc_driver *driver;
308 struct usb_hcd *hcd;
309
310 driver = (struct hc_driver *)id->driver_data;
311
312 /* For some HW implementation, a XHCI reset is just not enough... */
313 if (usb_xhci_needs_pci_reset(dev)) {
314 dev_info(&dev->dev, "Resetting\n");
315 if (pci_reset_function_locked(dev))
316 dev_warn(&dev->dev, "Reset failed");
317 }
318
319 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
320 pm_runtime_get_noresume(&dev->dev);
321
322 /* Register the USB 2.0 roothub.
323 * FIXME: USB core must know to register the USB 2.0 roothub first.
324 * This is sort of silly, because we could just set the HCD driver flags
325 * to say USB 2.0, but I'm not sure what the implications would be in
326 * the other parts of the HCD code.
327 */
328 retval = usb_hcd_pci_probe(dev, id);
329
330 if (retval)
331 goto put_runtime_pm;
332
333 /* USB 2.0 roothub is stored in the PCI device now. */
334 hcd = dev_get_drvdata(&dev->dev);
335 xhci = hcd_to_xhci(hcd);
336 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
337 pci_name(dev), hcd);
338 if (!xhci->shared_hcd) {
339 retval = -ENOMEM;
340 goto dealloc_usb2_hcd;
341 }
342
343 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
344 IRQF_SHARED);
345 if (retval)
346 goto put_usb3_hcd;
347 /* Roothub already marked as USB 3.0 speed */
348
349 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
350 HCC_MAX_PSA(xhci->hcc_params) >= 4)
351 xhci->shared_hcd->can_do_streams = 1;
352
353 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
354 pm_runtime_put_noidle(&dev->dev);
355
356 return 0;
357
358 put_usb3_hcd:
359 usb_put_hcd(xhci->shared_hcd);
360 dealloc_usb2_hcd:
361 usb_hcd_pci_remove(dev);
362 put_runtime_pm:
363 pm_runtime_put_noidle(&dev->dev);
364 return retval;
365 }
366
xhci_pci_remove(struct pci_dev * dev)367 static void xhci_pci_remove(struct pci_dev *dev)
368 {
369 struct xhci_hcd *xhci;
370
371 xhci = hcd_to_xhci(pci_get_drvdata(dev));
372 xhci->xhc_state |= XHCI_STATE_REMOVING;
373 if (xhci->shared_hcd) {
374 usb_remove_hcd(xhci->shared_hcd);
375 usb_put_hcd(xhci->shared_hcd);
376 xhci->shared_hcd = NULL;
377 }
378
379 /* Workaround for spurious wakeups at shutdown with HSW */
380 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
381 pci_set_power_state(dev, PCI_D3hot);
382
383 usb_hcd_pci_remove(dev);
384 }
385
386 #ifdef CONFIG_PM
387 /*
388 * In some Intel xHCI controllers, in order to get D3 working,
389 * through a vendor specific SSIC CONFIG register at offset 0x883c,
390 * SSIC PORT need to be marked as "unused" before putting xHCI
391 * into D3. After D3 exit, the SSIC port need to be marked as "used".
392 * Without this change, xHCI might not enter D3 state.
393 */
xhci_ssic_port_unused_quirk(struct usb_hcd * hcd,bool suspend)394 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
395 {
396 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
397 u32 val;
398 void __iomem *reg;
399 int i;
400
401 for (i = 0; i < SSIC_PORT_NUM; i++) {
402 reg = (void __iomem *) xhci->cap_regs +
403 SSIC_PORT_CFG2 +
404 i * SSIC_PORT_CFG2_OFFSET;
405
406 /* Notify SSIC that SSIC profile programming is not done. */
407 val = readl(reg) & ~PROG_DONE;
408 writel(val, reg);
409
410 /* Mark SSIC port as unused(suspend) or used(resume) */
411 val = readl(reg);
412 if (suspend)
413 val |= SSIC_PORT_UNUSED;
414 else
415 val &= ~SSIC_PORT_UNUSED;
416 writel(val, reg);
417
418 /* Notify SSIC that SSIC profile programming is done */
419 val = readl(reg) | PROG_DONE;
420 writel(val, reg);
421 readl(reg);
422 }
423 }
424
425 /*
426 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
427 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
428 */
xhci_pme_quirk(struct usb_hcd * hcd)429 static void xhci_pme_quirk(struct usb_hcd *hcd)
430 {
431 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
432 void __iomem *reg;
433 u32 val;
434
435 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
436 val = readl(reg);
437 writel(val | BIT(28), reg);
438 readl(reg);
439 }
440
xhci_pci_suspend(struct usb_hcd * hcd,bool do_wakeup)441 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
442 {
443 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
444 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
445 int ret;
446
447 /*
448 * Systems with the TI redriver that loses port status change events
449 * need to have the registers polled during D3, so avoid D3cold.
450 */
451 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
452 pci_d3cold_disable(pdev);
453
454 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
455 xhci_pme_quirk(hcd);
456
457 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
458 xhci_ssic_port_unused_quirk(hcd, true);
459
460 ret = xhci_suspend(xhci, do_wakeup);
461 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
462 xhci_ssic_port_unused_quirk(hcd, false);
463
464 return ret;
465 }
466
xhci_pci_resume(struct usb_hcd * hcd,bool hibernated)467 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
468 {
469 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
470 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
471 int retval = 0;
472
473 /* The BIOS on systems with the Intel Panther Point chipset may or may
474 * not support xHCI natively. That means that during system resume, it
475 * may switch the ports back to EHCI so that users can use their
476 * keyboard to select a kernel from GRUB after resume from hibernate.
477 *
478 * The BIOS is supposed to remember whether the OS had xHCI ports
479 * enabled before resume, and switch the ports back to xHCI when the
480 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
481 * writers.
482 *
483 * Unconditionally switch the ports back to xHCI after a system resume.
484 * It should not matter whether the EHCI or xHCI controller is
485 * resumed first. It's enough to do the switchover in xHCI because
486 * USB core won't notice anything as the hub driver doesn't start
487 * running again until after all the devices (including both EHCI and
488 * xHCI host controllers) have been resumed.
489 */
490
491 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
492 usb_enable_intel_xhci_ports(pdev);
493
494 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
495 xhci_ssic_port_unused_quirk(hcd, false);
496
497 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
498 xhci_pme_quirk(hcd);
499
500 retval = xhci_resume(xhci, hibernated);
501 return retval;
502 }
503
xhci_pci_shutdown(struct usb_hcd * hcd)504 static void xhci_pci_shutdown(struct usb_hcd *hcd)
505 {
506 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
507 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
508
509 xhci_shutdown(hcd);
510
511 /* Yet another workaround for spurious wakeups at shutdown with HSW */
512 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
513 pci_set_power_state(pdev, PCI_D3hot);
514 }
515 #endif /* CONFIG_PM */
516
517 /*-------------------------------------------------------------------------*/
518
519 /* PCI driver selection metadata; PCI hotplugging uses this */
520 static const struct pci_device_id pci_ids[] = { {
521 /* handle any USB 3.0 xHCI controller */
522 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
523 .driver_data = (unsigned long) &xhci_pci_hc_driver,
524 },
525 { /* end: all zeroes */ }
526 };
527 MODULE_DEVICE_TABLE(pci, pci_ids);
528
529 /* pci driver glue; this is a "new style" PCI driver module */
530 static struct pci_driver xhci_pci_driver = {
531 .name = (char *) hcd_name,
532 .id_table = pci_ids,
533
534 .probe = xhci_pci_probe,
535 .remove = xhci_pci_remove,
536 /* suspend and resume implemented later */
537
538 .shutdown = usb_hcd_pci_shutdown,
539 #ifdef CONFIG_PM
540 .driver = {
541 .pm = &usb_hcd_pci_pm_ops
542 },
543 #endif
544 };
545
xhci_pci_init(void)546 static int __init xhci_pci_init(void)
547 {
548 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
549 #ifdef CONFIG_PM
550 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
551 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
552 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
553 #endif
554 return pci_register_driver(&xhci_pci_driver);
555 }
556 module_init(xhci_pci_init);
557
xhci_pci_exit(void)558 static void __exit xhci_pci_exit(void)
559 {
560 pci_unregister_driver(&xhci_pci_driver);
561 }
562 module_exit(xhci_pci_exit);
563
564 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
565 MODULE_LICENSE("GPL");
566