1 /*
2 * Copyright (C) 2005-2006 by Texas Instruments
3 *
4 * This file implements a DMA interface using TI's CPPI DMA.
5 * For now it's DaVinci-only, but CPPI isn't specific to DaVinci or USB.
6 * The TUSB6020, using VLYNQ, has CPPI that looks much like DaVinci.
7 */
8
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/slab.h>
12 #include <linux/usb.h>
13
14 #include "musb_core.h"
15 #include "musb_debug.h"
16 #include "cppi_dma.h"
17 #include "davinci.h"
18
19
20 /* CPPI DMA status 7-mar-2006:
21 *
22 * - See musb_{host,gadget}.c for more info
23 *
24 * - Correct RX DMA generally forces the engine into irq-per-packet mode,
25 * which can easily saturate the CPU under non-mass-storage loads.
26 *
27 * NOTES 24-aug-2006 (2.6.18-rc4):
28 *
29 * - peripheral RXDMA wedged in a test with packets of length 512/512/1.
30 * evidently after the 1 byte packet was received and acked, the queue
31 * of BDs got garbaged so it wouldn't empty the fifo. (rxcsr 0x2003,
32 * and RX DMA0: 4 left, 80000000 8feff880, 8feff860 8feff860; 8f321401
33 * 004001ff 00000001 .. 8feff860) Host was just getting NAKed on tx
34 * of its next (512 byte) packet. IRQ issues?
35 *
36 * REVISIT: the "transfer DMA" glue between CPPI and USB fifos will
37 * evidently also directly update the RX and TX CSRs ... so audit all
38 * host and peripheral side DMA code to avoid CSR access after DMA has
39 * been started.
40 */
41
42 /* REVISIT now we can avoid preallocating these descriptors; or
43 * more simply, switch to a global freelist not per-channel ones.
44 * Note: at full speed, 64 descriptors == 4K bulk data.
45 */
46 #define NUM_TXCHAN_BD 64
47 #define NUM_RXCHAN_BD 64
48
cpu_drain_writebuffer(void)49 static inline void cpu_drain_writebuffer(void)
50 {
51 wmb();
52 #ifdef CONFIG_CPU_ARM926T
53 /* REVISIT this "should not be needed",
54 * but lack of it sure seemed to hurt ...
55 */
56 asm("mcr p15, 0, r0, c7, c10, 4 @ drain write buffer\n");
57 #endif
58 }
59
cppi_bd_alloc(struct cppi_channel * c)60 static inline struct cppi_descriptor *cppi_bd_alloc(struct cppi_channel *c)
61 {
62 struct cppi_descriptor *bd = c->freelist;
63
64 if (bd)
65 c->freelist = bd->next;
66 return bd;
67 }
68
69 static inline void
cppi_bd_free(struct cppi_channel * c,struct cppi_descriptor * bd)70 cppi_bd_free(struct cppi_channel *c, struct cppi_descriptor *bd)
71 {
72 if (!bd)
73 return;
74 bd->next = c->freelist;
75 c->freelist = bd;
76 }
77
78 /*
79 * Start DMA controller
80 *
81 * Initialize the DMA controller as necessary.
82 */
83
84 /* zero out entire rx state RAM entry for the channel */
cppi_reset_rx(struct cppi_rx_stateram __iomem * rx)85 static void cppi_reset_rx(struct cppi_rx_stateram __iomem *rx)
86 {
87 musb_writel(&rx->rx_skipbytes, 0, 0);
88 musb_writel(&rx->rx_head, 0, 0);
89 musb_writel(&rx->rx_sop, 0, 0);
90 musb_writel(&rx->rx_current, 0, 0);
91 musb_writel(&rx->rx_buf_current, 0, 0);
92 musb_writel(&rx->rx_len_len, 0, 0);
93 musb_writel(&rx->rx_cnt_cnt, 0, 0);
94 }
95
96 /* zero out entire tx state RAM entry for the channel */
cppi_reset_tx(struct cppi_tx_stateram __iomem * tx,u32 ptr)97 static void cppi_reset_tx(struct cppi_tx_stateram __iomem *tx, u32 ptr)
98 {
99 musb_writel(&tx->tx_head, 0, 0);
100 musb_writel(&tx->tx_buf, 0, 0);
101 musb_writel(&tx->tx_current, 0, 0);
102 musb_writel(&tx->tx_buf_current, 0, 0);
103 musb_writel(&tx->tx_info, 0, 0);
104 musb_writel(&tx->tx_rem_len, 0, 0);
105 /* musb_writel(&tx->tx_dummy, 0, 0); */
106 musb_writel(&tx->tx_complete, 0, ptr);
107 }
108
cppi_pool_init(struct cppi * cppi,struct cppi_channel * c)109 static void cppi_pool_init(struct cppi *cppi, struct cppi_channel *c)
110 {
111 int j;
112
113 /* initialize channel fields */
114 c->head = NULL;
115 c->tail = NULL;
116 c->last_processed = NULL;
117 c->channel.status = MUSB_DMA_STATUS_UNKNOWN;
118 c->controller = cppi;
119 c->is_rndis = 0;
120 c->freelist = NULL;
121
122 /* build the BD Free list for the channel */
123 for (j = 0; j < NUM_TXCHAN_BD + 1; j++) {
124 struct cppi_descriptor *bd;
125 dma_addr_t dma;
126
127 bd = dma_pool_alloc(cppi->pool, GFP_KERNEL, &dma);
128 bd->dma = dma;
129 cppi_bd_free(c, bd);
130 }
131 }
132
133 static int cppi_channel_abort(struct dma_channel *);
134
cppi_pool_free(struct cppi_channel * c)135 static void cppi_pool_free(struct cppi_channel *c)
136 {
137 struct cppi *cppi = c->controller;
138 struct cppi_descriptor *bd;
139
140 (void) cppi_channel_abort(&c->channel);
141 c->channel.status = MUSB_DMA_STATUS_UNKNOWN;
142 c->controller = NULL;
143
144 /* free all its bds */
145 bd = c->last_processed;
146 do {
147 if (bd)
148 dma_pool_free(cppi->pool, bd, bd->dma);
149 bd = cppi_bd_alloc(c);
150 } while (bd);
151 c->last_processed = NULL;
152 }
153
cppi_controller_start(struct cppi * controller)154 static void cppi_controller_start(struct cppi *controller)
155 {
156 void __iomem *tibase;
157 int i;
158
159 /* do whatever is necessary to start controller */
160 for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {
161 controller->tx[i].transmit = true;
162 controller->tx[i].index = i;
163 }
164 for (i = 0; i < ARRAY_SIZE(controller->rx); i++) {
165 controller->rx[i].transmit = false;
166 controller->rx[i].index = i;
167 }
168
169 /* setup BD list on a per channel basis */
170 for (i = 0; i < ARRAY_SIZE(controller->tx); i++)
171 cppi_pool_init(controller, controller->tx + i);
172 for (i = 0; i < ARRAY_SIZE(controller->rx); i++)
173 cppi_pool_init(controller, controller->rx + i);
174
175 tibase = controller->tibase;
176 INIT_LIST_HEAD(&controller->tx_complete);
177
178 /* initialise tx/rx channel head pointers to zero */
179 for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {
180 struct cppi_channel *tx_ch = controller->tx + i;
181 struct cppi_tx_stateram __iomem *tx;
182
183 INIT_LIST_HEAD(&tx_ch->tx_complete);
184
185 tx = tibase + DAVINCI_TXCPPI_STATERAM_OFFSET(i);
186 tx_ch->state_ram = tx;
187 cppi_reset_tx(tx, 0);
188 }
189 for (i = 0; i < ARRAY_SIZE(controller->rx); i++) {
190 struct cppi_channel *rx_ch = controller->rx + i;
191 struct cppi_rx_stateram __iomem *rx;
192
193 INIT_LIST_HEAD(&rx_ch->tx_complete);
194
195 rx = tibase + DAVINCI_RXCPPI_STATERAM_OFFSET(i);
196 rx_ch->state_ram = rx;
197 cppi_reset_rx(rx);
198 }
199
200 /* enable individual cppi channels */
201 musb_writel(tibase, DAVINCI_TXCPPI_INTENAB_REG,
202 DAVINCI_DMA_ALL_CHANNELS_ENABLE);
203 musb_writel(tibase, DAVINCI_RXCPPI_INTENAB_REG,
204 DAVINCI_DMA_ALL_CHANNELS_ENABLE);
205
206 /* enable tx/rx CPPI control */
207 musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE);
208 musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE);
209
210 /* disable RNDIS mode, also host rx RNDIS autorequest */
211 musb_writel(tibase, DAVINCI_RNDIS_REG, 0);
212 musb_writel(tibase, DAVINCI_AUTOREQ_REG, 0);
213 }
214
215 /*
216 * Stop DMA controller
217 *
218 * De-Init the DMA controller as necessary.
219 */
220
cppi_controller_stop(struct cppi * controller)221 static void cppi_controller_stop(struct cppi *controller)
222 {
223 void __iomem *tibase;
224 int i;
225 struct musb *musb;
226
227 musb = controller->controller.musb;
228
229 tibase = controller->tibase;
230 /* DISABLE INDIVIDUAL CHANNEL Interrupts */
231 musb_writel(tibase, DAVINCI_TXCPPI_INTCLR_REG,
232 DAVINCI_DMA_ALL_CHANNELS_ENABLE);
233 musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG,
234 DAVINCI_DMA_ALL_CHANNELS_ENABLE);
235
236 musb_dbg(musb, "Tearing down RX and TX Channels");
237 for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {
238 /* FIXME restructure of txdma to use bds like rxdma */
239 controller->tx[i].last_processed = NULL;
240 cppi_pool_free(controller->tx + i);
241 }
242 for (i = 0; i < ARRAY_SIZE(controller->rx); i++)
243 cppi_pool_free(controller->rx + i);
244
245 /* in Tx Case proper teardown is supported. We resort to disabling
246 * Tx/Rx CPPI after cleanup of Tx channels. Before TX teardown is
247 * complete TX CPPI cannot be disabled.
248 */
249 /*disable tx/rx cppi */
250 musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE);
251 musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE);
252 }
253
254 /* While dma channel is allocated, we only want the core irqs active
255 * for fault reports, otherwise we'd get irqs that we don't care about.
256 * Except for TX irqs, where dma done != fifo empty and reusable ...
257 *
258 * NOTE: docs don't say either way, but irq masking **enables** irqs.
259 *
260 * REVISIT same issue applies to pure PIO usage too, and non-cppi dma...
261 */
core_rxirq_disable(void __iomem * tibase,unsigned epnum)262 static inline void core_rxirq_disable(void __iomem *tibase, unsigned epnum)
263 {
264 musb_writel(tibase, DAVINCI_USB_INT_MASK_CLR_REG, 1 << (epnum + 8));
265 }
266
core_rxirq_enable(void __iomem * tibase,unsigned epnum)267 static inline void core_rxirq_enable(void __iomem *tibase, unsigned epnum)
268 {
269 musb_writel(tibase, DAVINCI_USB_INT_MASK_SET_REG, 1 << (epnum + 8));
270 }
271
272
273 /*
274 * Allocate a CPPI Channel for DMA. With CPPI, channels are bound to
275 * each transfer direction of a non-control endpoint, so allocating
276 * (and deallocating) is mostly a way to notice bad housekeeping on
277 * the software side. We assume the irqs are always active.
278 */
279 static struct dma_channel *
cppi_channel_allocate(struct dma_controller * c,struct musb_hw_ep * ep,u8 transmit)280 cppi_channel_allocate(struct dma_controller *c,
281 struct musb_hw_ep *ep, u8 transmit)
282 {
283 struct cppi *controller;
284 u8 index;
285 struct cppi_channel *cppi_ch;
286 void __iomem *tibase;
287 struct musb *musb;
288
289 controller = container_of(c, struct cppi, controller);
290 tibase = controller->tibase;
291 musb = c->musb;
292
293 /* ep0 doesn't use DMA; remember cppi indices are 0..N-1 */
294 index = ep->epnum - 1;
295
296 /* return the corresponding CPPI Channel Handle, and
297 * probably disable the non-CPPI irq until we need it.
298 */
299 if (transmit) {
300 if (index >= ARRAY_SIZE(controller->tx)) {
301 musb_dbg(musb, "no %cX%d CPPI channel", 'T', index);
302 return NULL;
303 }
304 cppi_ch = controller->tx + index;
305 } else {
306 if (index >= ARRAY_SIZE(controller->rx)) {
307 musb_dbg(musb, "no %cX%d CPPI channel", 'R', index);
308 return NULL;
309 }
310 cppi_ch = controller->rx + index;
311 core_rxirq_disable(tibase, ep->epnum);
312 }
313
314 /* REVISIT make this an error later once the same driver code works
315 * with the other DMA engine too
316 */
317 if (cppi_ch->hw_ep)
318 musb_dbg(musb, "re-allocating DMA%d %cX channel %p",
319 index, transmit ? 'T' : 'R', cppi_ch);
320 cppi_ch->hw_ep = ep;
321 cppi_ch->channel.status = MUSB_DMA_STATUS_FREE;
322 cppi_ch->channel.max_len = 0x7fffffff;
323
324 musb_dbg(musb, "Allocate CPPI%d %cX", index, transmit ? 'T' : 'R');
325 return &cppi_ch->channel;
326 }
327
328 /* Release a CPPI Channel. */
cppi_channel_release(struct dma_channel * channel)329 static void cppi_channel_release(struct dma_channel *channel)
330 {
331 struct cppi_channel *c;
332 void __iomem *tibase;
333
334 /* REVISIT: for paranoia, check state and abort if needed... */
335
336 c = container_of(channel, struct cppi_channel, channel);
337 tibase = c->controller->tibase;
338 if (!c->hw_ep)
339 musb_dbg(c->controller->controller.musb,
340 "releasing idle DMA channel %p", c);
341 else if (!c->transmit)
342 core_rxirq_enable(tibase, c->index + 1);
343
344 /* for now, leave its cppi IRQ enabled (we won't trigger it) */
345 c->hw_ep = NULL;
346 channel->status = MUSB_DMA_STATUS_UNKNOWN;
347 }
348
349 /* Context: controller irqlocked */
350 static void
cppi_dump_rx(int level,struct cppi_channel * c,const char * tag)351 cppi_dump_rx(int level, struct cppi_channel *c, const char *tag)
352 {
353 void __iomem *base = c->controller->mregs;
354 struct cppi_rx_stateram __iomem *rx = c->state_ram;
355
356 musb_ep_select(base, c->index + 1);
357
358 musb_dbg(c->controller->controller.musb,
359 "RX DMA%d%s: %d left, csr %04x, "
360 "%08x H%08x S%08x C%08x, "
361 "B%08x L%08x %08x .. %08x",
362 c->index, tag,
363 musb_readl(c->controller->tibase,
364 DAVINCI_RXCPPI_BUFCNT0_REG + 4 * c->index),
365 musb_readw(c->hw_ep->regs, MUSB_RXCSR),
366
367 musb_readl(&rx->rx_skipbytes, 0),
368 musb_readl(&rx->rx_head, 0),
369 musb_readl(&rx->rx_sop, 0),
370 musb_readl(&rx->rx_current, 0),
371
372 musb_readl(&rx->rx_buf_current, 0),
373 musb_readl(&rx->rx_len_len, 0),
374 musb_readl(&rx->rx_cnt_cnt, 0),
375 musb_readl(&rx->rx_complete, 0)
376 );
377 }
378
379 /* Context: controller irqlocked */
380 static void
cppi_dump_tx(int level,struct cppi_channel * c,const char * tag)381 cppi_dump_tx(int level, struct cppi_channel *c, const char *tag)
382 {
383 void __iomem *base = c->controller->mregs;
384 struct cppi_tx_stateram __iomem *tx = c->state_ram;
385
386 musb_ep_select(base, c->index + 1);
387
388 musb_dbg(c->controller->controller.musb,
389 "TX DMA%d%s: csr %04x, "
390 "H%08x S%08x C%08x %08x, "
391 "F%08x L%08x .. %08x",
392 c->index, tag,
393 musb_readw(c->hw_ep->regs, MUSB_TXCSR),
394
395 musb_readl(&tx->tx_head, 0),
396 musb_readl(&tx->tx_buf, 0),
397 musb_readl(&tx->tx_current, 0),
398 musb_readl(&tx->tx_buf_current, 0),
399
400 musb_readl(&tx->tx_info, 0),
401 musb_readl(&tx->tx_rem_len, 0),
402 /* dummy/unused word 6 */
403 musb_readl(&tx->tx_complete, 0)
404 );
405 }
406
407 /* Context: controller irqlocked */
408 static inline void
cppi_rndis_update(struct cppi_channel * c,int is_rx,void __iomem * tibase,int is_rndis)409 cppi_rndis_update(struct cppi_channel *c, int is_rx,
410 void __iomem *tibase, int is_rndis)
411 {
412 /* we may need to change the rndis flag for this cppi channel */
413 if (c->is_rndis != is_rndis) {
414 u32 value = musb_readl(tibase, DAVINCI_RNDIS_REG);
415 u32 temp = 1 << (c->index);
416
417 if (is_rx)
418 temp <<= 16;
419 if (is_rndis)
420 value |= temp;
421 else
422 value &= ~temp;
423 musb_writel(tibase, DAVINCI_RNDIS_REG, value);
424 c->is_rndis = is_rndis;
425 }
426 }
427
cppi_dump_rxbd(const char * tag,struct cppi_descriptor * bd)428 static void cppi_dump_rxbd(const char *tag, struct cppi_descriptor *bd)
429 {
430 pr_debug("RXBD/%s %08x: "
431 "nxt %08x buf %08x off.blen %08x opt.plen %08x\n",
432 tag, bd->dma,
433 bd->hw_next, bd->hw_bufp, bd->hw_off_len,
434 bd->hw_options);
435 }
436
cppi_dump_rxq(int level,const char * tag,struct cppi_channel * rx)437 static void cppi_dump_rxq(int level, const char *tag, struct cppi_channel *rx)
438 {
439 struct cppi_descriptor *bd;
440
441 cppi_dump_rx(level, rx, tag);
442 if (rx->last_processed)
443 cppi_dump_rxbd("last", rx->last_processed);
444 for (bd = rx->head; bd; bd = bd->next)
445 cppi_dump_rxbd("active", bd);
446 }
447
448
449 /* NOTE: DaVinci autoreq is ignored except for host side "RNDIS" mode RX;
450 * so we won't ever use it (see "CPPI RX Woes" below).
451 */
cppi_autoreq_update(struct cppi_channel * rx,void __iomem * tibase,int onepacket,unsigned n_bds)452 static inline int cppi_autoreq_update(struct cppi_channel *rx,
453 void __iomem *tibase, int onepacket, unsigned n_bds)
454 {
455 u32 val;
456
457 #ifdef RNDIS_RX_IS_USABLE
458 u32 tmp;
459 /* assert(is_host_active(musb)) */
460
461 /* start from "AutoReq never" */
462 tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG);
463 val = tmp & ~((0x3) << (rx->index * 2));
464
465 /* HCD arranged reqpkt for packet #1. we arrange int
466 * for all but the last one, maybe in two segments.
467 */
468 if (!onepacket) {
469 #if 0
470 /* use two segments, autoreq "all" then the last "never" */
471 val |= ((0x3) << (rx->index * 2));
472 n_bds--;
473 #else
474 /* one segment, autoreq "all-but-last" */
475 val |= ((0x1) << (rx->index * 2));
476 #endif
477 }
478
479 if (val != tmp) {
480 int n = 100;
481
482 /* make sure that autoreq is updated before continuing */
483 musb_writel(tibase, DAVINCI_AUTOREQ_REG, val);
484 do {
485 tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG);
486 if (tmp == val)
487 break;
488 cpu_relax();
489 } while (n-- > 0);
490 }
491 #endif
492
493 /* REQPKT is turned off after each segment */
494 if (n_bds && rx->channel.actual_len) {
495 void __iomem *regs = rx->hw_ep->regs;
496
497 val = musb_readw(regs, MUSB_RXCSR);
498 if (!(val & MUSB_RXCSR_H_REQPKT)) {
499 val |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS;
500 musb_writew(regs, MUSB_RXCSR, val);
501 /* flush writebuffer */
502 val = musb_readw(regs, MUSB_RXCSR);
503 }
504 }
505 return n_bds;
506 }
507
508
509 /* Buffer enqueuing Logic:
510 *
511 * - RX builds new queues each time, to help handle routine "early
512 * termination" cases (faults, including errors and short reads)
513 * more correctly.
514 *
515 * - for now, TX reuses the same queue of BDs every time
516 *
517 * REVISIT long term, we want a normal dynamic model.
518 * ... the goal will be to append to the
519 * existing queue, processing completed "dma buffers" (segments) on the fly.
520 *
521 * Otherwise we force an IRQ latency between requests, which slows us a lot
522 * (especially in "transparent" dma). Unfortunately that model seems to be
523 * inherent in the DMA model from the Mentor code, except in the rare case
524 * of transfers big enough (~128+ KB) that we could append "middle" segments
525 * in the TX paths. (RX can't do this, see below.)
526 *
527 * That's true even in the CPPI- friendly iso case, where most urbs have
528 * several small segments provided in a group and where the "packet at a time"
529 * "transparent" DMA model is always correct, even on the RX side.
530 */
531
532 /*
533 * CPPI TX:
534 * ========
535 * TX is a lot more reasonable than RX; it doesn't need to run in
536 * irq-per-packet mode very often. RNDIS mode seems to behave too
537 * (except how it handles the exactly-N-packets case). Building a
538 * txdma queue with multiple requests (urb or usb_request) looks
539 * like it would work ... but fault handling would need much testing.
540 *
541 * The main issue with TX mode RNDIS relates to transfer lengths that
542 * are an exact multiple of the packet length. It appears that there's
543 * a hiccup in that case (maybe the DMA completes before the ZLP gets
544 * written?) boiling down to not being able to rely on CPPI writing any
545 * terminating zero length packet before the next transfer is written.
546 * So that's punted to PIO; better yet, gadget drivers can avoid it.
547 *
548 * Plus, there's allegedly an undocumented constraint that rndis transfer
549 * length be a multiple of 64 bytes ... but the chip doesn't act that
550 * way, and we really don't _want_ that behavior anyway.
551 *
552 * On TX, "transparent" mode works ... although experiments have shown
553 * problems trying to use the SOP/EOP bits in different USB packets.
554 *
555 * REVISIT try to handle terminating zero length packets using CPPI
556 * instead of doing it by PIO after an IRQ. (Meanwhile, make Ethernet
557 * links avoid that issue by forcing them to avoid zlps.)
558 */
559 static void
cppi_next_tx_segment(struct musb * musb,struct cppi_channel * tx)560 cppi_next_tx_segment(struct musb *musb, struct cppi_channel *tx)
561 {
562 unsigned maxpacket = tx->maxpacket;
563 dma_addr_t addr = tx->buf_dma + tx->offset;
564 size_t length = tx->buf_len - tx->offset;
565 struct cppi_descriptor *bd;
566 unsigned n_bds;
567 unsigned i;
568 struct cppi_tx_stateram __iomem *tx_ram = tx->state_ram;
569 int rndis;
570
571 /* TX can use the CPPI "rndis" mode, where we can probably fit this
572 * transfer in one BD and one IRQ. The only time we would NOT want
573 * to use it is when hardware constraints prevent it, or if we'd
574 * trigger the "send a ZLP?" confusion.
575 */
576 rndis = (maxpacket & 0x3f) == 0
577 && length > maxpacket
578 && length < 0xffff
579 && (length % maxpacket) != 0;
580
581 if (rndis) {
582 maxpacket = length;
583 n_bds = 1;
584 } else {
585 if (length)
586 n_bds = DIV_ROUND_UP(length, maxpacket);
587 else
588 n_bds = 1;
589 n_bds = min(n_bds, (unsigned) NUM_TXCHAN_BD);
590 length = min(n_bds * maxpacket, length);
591 }
592
593 musb_dbg(musb, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u",
594 tx->index,
595 maxpacket,
596 rndis ? "rndis" : "transparent",
597 n_bds,
598 (unsigned long long)addr, length);
599
600 cppi_rndis_update(tx, 0, musb->ctrl_base, rndis);
601
602 /* assuming here that channel_program is called during
603 * transfer initiation ... current code maintains state
604 * for one outstanding request only (no queues, not even
605 * the implicit ones of an iso urb).
606 */
607
608 bd = tx->freelist;
609 tx->head = bd;
610 tx->last_processed = NULL;
611
612 /* FIXME use BD pool like RX side does, and just queue
613 * the minimum number for this request.
614 */
615
616 /* Prepare queue of BDs first, then hand it to hardware.
617 * All BDs except maybe the last should be of full packet
618 * size; for RNDIS there _is_ only that last packet.
619 */
620 for (i = 0; i < n_bds; ) {
621 if (++i < n_bds && bd->next)
622 bd->hw_next = bd->next->dma;
623 else
624 bd->hw_next = 0;
625
626 bd->hw_bufp = tx->buf_dma + tx->offset;
627
628 /* FIXME set EOP only on the last packet,
629 * SOP only on the first ... avoid IRQs
630 */
631 if ((tx->offset + maxpacket) <= tx->buf_len) {
632 tx->offset += maxpacket;
633 bd->hw_off_len = maxpacket;
634 bd->hw_options = CPPI_SOP_SET | CPPI_EOP_SET
635 | CPPI_OWN_SET | maxpacket;
636 } else {
637 /* only this one may be a partial USB Packet */
638 u32 partial_len;
639
640 partial_len = tx->buf_len - tx->offset;
641 tx->offset = tx->buf_len;
642 bd->hw_off_len = partial_len;
643
644 bd->hw_options = CPPI_SOP_SET | CPPI_EOP_SET
645 | CPPI_OWN_SET | partial_len;
646 if (partial_len == 0)
647 bd->hw_options |= CPPI_ZERO_SET;
648 }
649
650 musb_dbg(musb, "TXBD %p: nxt %08x buf %08x len %04x opt %08x",
651 bd, bd->hw_next, bd->hw_bufp,
652 bd->hw_off_len, bd->hw_options);
653
654 /* update the last BD enqueued to the list */
655 tx->tail = bd;
656 bd = bd->next;
657 }
658
659 /* BDs live in DMA-coherent memory, but writes might be pending */
660 cpu_drain_writebuffer();
661
662 /* Write to the HeadPtr in state RAM to trigger */
663 musb_writel(&tx_ram->tx_head, 0, (u32)tx->freelist->dma);
664
665 cppi_dump_tx(5, tx, "/S");
666 }
667
668 /*
669 * CPPI RX Woes:
670 * =============
671 * Consider a 1KB bulk RX buffer in two scenarios: (a) it's fed two 300 byte
672 * packets back-to-back, and (b) it's fed two 512 byte packets back-to-back.
673 * (Full speed transfers have similar scenarios.)
674 *
675 * The correct behavior for Linux is that (a) fills the buffer with 300 bytes,
676 * and the next packet goes into a buffer that's queued later; while (b) fills
677 * the buffer with 1024 bytes. How to do that with CPPI?
678 *
679 * - RX queues in "rndis" mode -- one single BD -- handle (a) correctly, but
680 * (b) loses **BADLY** because nothing (!) happens when that second packet
681 * fills the buffer, much less when a third one arrives. (Which makes this
682 * not a "true" RNDIS mode. In the RNDIS protocol short-packet termination
683 * is optional, and it's fine if peripherals -- not hosts! -- pad messages
684 * out to end-of-buffer. Standard PCI host controller DMA descriptors
685 * implement that mode by default ... which is no accident.)
686 *
687 * - RX queues in "transparent" mode -- two BDs with 512 bytes each -- have
688 * converse problems: (b) is handled right, but (a) loses badly. CPPI RX
689 * ignores SOP/EOP markings and processes both of those BDs; so both packets
690 * are loaded into the buffer (with a 212 byte gap between them), and the next
691 * buffer queued will NOT get its 300 bytes of data. (It seems like SOP/EOP
692 * are intended as outputs for RX queues, not inputs...)
693 *
694 * - A variant of "transparent" mode -- one BD at a time -- is the only way to
695 * reliably make both cases work, with software handling both cases correctly
696 * and at the significant penalty of needing an IRQ per packet. (The lack of
697 * I/O overlap can be slightly ameliorated by enabling double buffering.)
698 *
699 * So how to get rid of IRQ-per-packet? The transparent multi-BD case could
700 * be used in special cases like mass storage, which sets URB_SHORT_NOT_OK
701 * (or maybe its peripheral side counterpart) to flag (a) scenarios as errors
702 * with guaranteed driver level fault recovery and scrubbing out what's left
703 * of that garbaged datastream.
704 *
705 * But there seems to be no way to identify the cases where CPPI RNDIS mode
706 * is appropriate -- which do NOT include RNDIS host drivers, but do include
707 * the CDC Ethernet driver! -- and the documentation is incomplete/wrong.
708 * So we can't _ever_ use RX RNDIS mode ... except by using a heuristic
709 * that applies best on the peripheral side (and which could fail rudely).
710 *
711 * Leaving only "transparent" mode; we avoid multi-bd modes in almost all
712 * cases other than mass storage class. Otherwise we're correct but slow,
713 * since CPPI penalizes our need for a "true RNDIS" default mode.
714 */
715
716
717 /* Heuristic, intended to kick in for ethernet/rndis peripheral ONLY
718 *
719 * IFF
720 * (a) peripheral mode ... since rndis peripherals could pad their
721 * writes to hosts, causing i/o failure; or we'd have to cope with
722 * a largely unknowable variety of host side protocol variants
723 * (b) and short reads are NOT errors ... since full reads would
724 * cause those same i/o failures
725 * (c) and read length is
726 * - less than 64KB (max per cppi descriptor)
727 * - not a multiple of 4096 (g_zero default, full reads typical)
728 * - N (>1) packets long, ditto (full reads not EXPECTED)
729 * THEN
730 * try rx rndis mode
731 *
732 * Cost of heuristic failing: RXDMA wedges at the end of transfers that
733 * fill out the whole buffer. Buggy host side usb network drivers could
734 * trigger that, but "in the field" such bugs seem to be all but unknown.
735 *
736 * So this module parameter lets the heuristic be disabled. When using
737 * gadgetfs, the heuristic will probably need to be disabled.
738 */
739 static bool cppi_rx_rndis = 1;
740
741 module_param(cppi_rx_rndis, bool, 0);
742 MODULE_PARM_DESC(cppi_rx_rndis, "enable/disable RX RNDIS heuristic");
743
744
745 /**
746 * cppi_next_rx_segment - dma read for the next chunk of a buffer
747 * @musb: the controller
748 * @rx: dma channel
749 * @onepacket: true unless caller treats short reads as errors, and
750 * performs fault recovery above usbcore.
751 * Context: controller irqlocked
752 *
753 * See above notes about why we can't use multi-BD RX queues except in
754 * rare cases (mass storage class), and can never use the hardware "rndis"
755 * mode (since it's not a "true" RNDIS mode) with complete safety..
756 *
757 * It's ESSENTIAL that callers specify "onepacket" mode unless they kick in
758 * code to recover from corrupted datastreams after each short transfer.
759 */
760 static void
cppi_next_rx_segment(struct musb * musb,struct cppi_channel * rx,int onepacket)761 cppi_next_rx_segment(struct musb *musb, struct cppi_channel *rx, int onepacket)
762 {
763 unsigned maxpacket = rx->maxpacket;
764 dma_addr_t addr = rx->buf_dma + rx->offset;
765 size_t length = rx->buf_len - rx->offset;
766 struct cppi_descriptor *bd, *tail;
767 unsigned n_bds;
768 unsigned i;
769 void __iomem *tibase = musb->ctrl_base;
770 int is_rndis = 0;
771 struct cppi_rx_stateram __iomem *rx_ram = rx->state_ram;
772 struct cppi_descriptor *d;
773
774 if (onepacket) {
775 /* almost every USB driver, host or peripheral side */
776 n_bds = 1;
777
778 /* maybe apply the heuristic above */
779 if (cppi_rx_rndis
780 && is_peripheral_active(musb)
781 && length > maxpacket
782 && (length & ~0xffff) == 0
783 && (length & 0x0fff) != 0
784 && (length & (maxpacket - 1)) == 0) {
785 maxpacket = length;
786 is_rndis = 1;
787 }
788 } else {
789 /* virtually nothing except mass storage class */
790 if (length > 0xffff) {
791 n_bds = 0xffff / maxpacket;
792 length = n_bds * maxpacket;
793 } else {
794 n_bds = DIV_ROUND_UP(length, maxpacket);
795 }
796 if (n_bds == 1)
797 onepacket = 1;
798 else
799 n_bds = min(n_bds, (unsigned) NUM_RXCHAN_BD);
800 }
801
802 /* In host mode, autorequest logic can generate some IN tokens; it's
803 * tricky since we can't leave REQPKT set in RXCSR after the transfer
804 * finishes. So: multipacket transfers involve two or more segments.
805 * And always at least two IRQs ... RNDIS mode is not an option.
806 */
807 if (is_host_active(musb))
808 n_bds = cppi_autoreq_update(rx, tibase, onepacket, n_bds);
809
810 cppi_rndis_update(rx, 1, musb->ctrl_base, is_rndis);
811
812 length = min(n_bds * maxpacket, length);
813
814 musb_dbg(musb, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) "
815 "dma 0x%llx len %u %u/%u",
816 rx->index, maxpacket,
817 onepacket
818 ? (is_rndis ? "rndis" : "onepacket")
819 : "multipacket",
820 n_bds,
821 musb_readl(tibase,
822 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
823 & 0xffff,
824 (unsigned long long)addr, length,
825 rx->channel.actual_len, rx->buf_len);
826
827 /* only queue one segment at a time, since the hardware prevents
828 * correct queue shutdown after unexpected short packets
829 */
830 bd = cppi_bd_alloc(rx);
831 rx->head = bd;
832
833 /* Build BDs for all packets in this segment */
834 for (i = 0, tail = NULL; bd && i < n_bds; i++, tail = bd) {
835 u32 bd_len;
836
837 if (i) {
838 bd = cppi_bd_alloc(rx);
839 if (!bd)
840 break;
841 tail->next = bd;
842 tail->hw_next = bd->dma;
843 }
844 bd->hw_next = 0;
845
846 /* all but the last packet will be maxpacket size */
847 if (maxpacket < length)
848 bd_len = maxpacket;
849 else
850 bd_len = length;
851
852 bd->hw_bufp = addr;
853 addr += bd_len;
854 rx->offset += bd_len;
855
856 bd->hw_off_len = (0 /*offset*/ << 16) + bd_len;
857 bd->buflen = bd_len;
858
859 bd->hw_options = CPPI_OWN_SET | (i == 0 ? length : 0);
860 length -= bd_len;
861 }
862
863 /* we always expect at least one reusable BD! */
864 if (!tail) {
865 WARNING("rx dma%d -- no BDs? need %d\n", rx->index, n_bds);
866 return;
867 } else if (i < n_bds)
868 WARNING("rx dma%d -- only %d of %d BDs\n", rx->index, i, n_bds);
869
870 tail->next = NULL;
871 tail->hw_next = 0;
872
873 bd = rx->head;
874 rx->tail = tail;
875
876 /* short reads and other faults should terminate this entire
877 * dma segment. we want one "dma packet" per dma segment, not
878 * one per USB packet, terminating the whole queue at once...
879 * NOTE that current hardware seems to ignore SOP and EOP.
880 */
881 bd->hw_options |= CPPI_SOP_SET;
882 tail->hw_options |= CPPI_EOP_SET;
883
884 for (d = rx->head; d; d = d->next)
885 cppi_dump_rxbd("S", d);
886
887 /* in case the preceding transfer left some state... */
888 tail = rx->last_processed;
889 if (tail) {
890 tail->next = bd;
891 tail->hw_next = bd->dma;
892 }
893
894 core_rxirq_enable(tibase, rx->index + 1);
895
896 /* BDs live in DMA-coherent memory, but writes might be pending */
897 cpu_drain_writebuffer();
898
899 /* REVISIT specs say to write this AFTER the BUFCNT register
900 * below ... but that loses badly.
901 */
902 musb_writel(&rx_ram->rx_head, 0, bd->dma);
903
904 /* bufferCount must be at least 3, and zeroes on completion
905 * unless it underflows below zero, or stops at two, or keeps
906 * growing ... grr.
907 */
908 i = musb_readl(tibase,
909 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
910 & 0xffff;
911
912 if (!i)
913 musb_writel(tibase,
914 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),
915 n_bds + 2);
916 else if (n_bds > (i - 3))
917 musb_writel(tibase,
918 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),
919 n_bds - (i - 3));
920
921 i = musb_readl(tibase,
922 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
923 & 0xffff;
924 if (i < (2 + n_bds)) {
925 musb_dbg(musb, "bufcnt%d underrun - %d (for %d)",
926 rx->index, i, n_bds);
927 musb_writel(tibase,
928 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),
929 n_bds + 2);
930 }
931
932 cppi_dump_rx(4, rx, "/S");
933 }
934
935 /**
936 * cppi_channel_program - program channel for data transfer
937 * @ch: the channel
938 * @maxpacket: max packet size
939 * @mode: For RX, 1 unless the usb protocol driver promised to treat
940 * all short reads as errors and kick in high level fault recovery.
941 * For TX, ignored because of RNDIS mode races/glitches.
942 * @dma_addr: dma address of buffer
943 * @len: length of buffer
944 * Context: controller irqlocked
945 */
cppi_channel_program(struct dma_channel * ch,u16 maxpacket,u8 mode,dma_addr_t dma_addr,u32 len)946 static int cppi_channel_program(struct dma_channel *ch,
947 u16 maxpacket, u8 mode,
948 dma_addr_t dma_addr, u32 len)
949 {
950 struct cppi_channel *cppi_ch;
951 struct cppi *controller;
952 struct musb *musb;
953
954 cppi_ch = container_of(ch, struct cppi_channel, channel);
955 controller = cppi_ch->controller;
956 musb = controller->controller.musb;
957
958 switch (ch->status) {
959 case MUSB_DMA_STATUS_BUS_ABORT:
960 case MUSB_DMA_STATUS_CORE_ABORT:
961 /* fault irq handler should have handled cleanup */
962 WARNING("%cX DMA%d not cleaned up after abort!\n",
963 cppi_ch->transmit ? 'T' : 'R',
964 cppi_ch->index);
965 /* WARN_ON(1); */
966 break;
967 case MUSB_DMA_STATUS_BUSY:
968 WARNING("program active channel? %cX DMA%d\n",
969 cppi_ch->transmit ? 'T' : 'R',
970 cppi_ch->index);
971 /* WARN_ON(1); */
972 break;
973 case MUSB_DMA_STATUS_UNKNOWN:
974 musb_dbg(musb, "%cX DMA%d not allocated!",
975 cppi_ch->transmit ? 'T' : 'R',
976 cppi_ch->index);
977 /* FALLTHROUGH */
978 case MUSB_DMA_STATUS_FREE:
979 break;
980 }
981
982 ch->status = MUSB_DMA_STATUS_BUSY;
983
984 /* set transfer parameters, then queue up its first segment */
985 cppi_ch->buf_dma = dma_addr;
986 cppi_ch->offset = 0;
987 cppi_ch->maxpacket = maxpacket;
988 cppi_ch->buf_len = len;
989 cppi_ch->channel.actual_len = 0;
990
991 /* TX channel? or RX? */
992 if (cppi_ch->transmit)
993 cppi_next_tx_segment(musb, cppi_ch);
994 else
995 cppi_next_rx_segment(musb, cppi_ch, mode);
996
997 return true;
998 }
999
cppi_rx_scan(struct cppi * cppi,unsigned ch)1000 static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
1001 {
1002 struct cppi_channel *rx = &cppi->rx[ch];
1003 struct cppi_rx_stateram __iomem *state = rx->state_ram;
1004 struct cppi_descriptor *bd;
1005 struct cppi_descriptor *last = rx->last_processed;
1006 bool completed = false;
1007 bool acked = false;
1008 int i;
1009 dma_addr_t safe2ack;
1010 void __iomem *regs = rx->hw_ep->regs;
1011 struct musb *musb = cppi->controller.musb;
1012
1013 cppi_dump_rx(6, rx, "/K");
1014
1015 bd = last ? last->next : rx->head;
1016 if (!bd)
1017 return false;
1018
1019 /* run through all completed BDs */
1020 for (i = 0, safe2ack = musb_readl(&state->rx_complete, 0);
1021 (safe2ack || completed) && bd && i < NUM_RXCHAN_BD;
1022 i++, bd = bd->next) {
1023 u16 len;
1024
1025 /* catch latest BD writes from CPPI */
1026 rmb();
1027 if (!completed && (bd->hw_options & CPPI_OWN_SET))
1028 break;
1029
1030 musb_dbg(musb, "C/RXBD %llx: nxt %08x buf %08x "
1031 "off.len %08x opt.len %08x (%d)",
1032 (unsigned long long)bd->dma, bd->hw_next, bd->hw_bufp,
1033 bd->hw_off_len, bd->hw_options,
1034 rx->channel.actual_len);
1035
1036 /* actual packet received length */
1037 if ((bd->hw_options & CPPI_SOP_SET) && !completed)
1038 len = bd->hw_off_len & CPPI_RECV_PKTLEN_MASK;
1039 else
1040 len = 0;
1041
1042 if (bd->hw_options & CPPI_EOQ_MASK)
1043 completed = true;
1044
1045 if (!completed && len < bd->buflen) {
1046 /* NOTE: when we get a short packet, RXCSR_H_REQPKT
1047 * must have been cleared, and no more DMA packets may
1048 * active be in the queue... TI docs didn't say, but
1049 * CPPI ignores those BDs even though OWN is still set.
1050 */
1051 completed = true;
1052 musb_dbg(musb, "rx short %d/%d (%d)",
1053 len, bd->buflen,
1054 rx->channel.actual_len);
1055 }
1056
1057 /* If we got here, we expect to ack at least one BD; meanwhile
1058 * CPPI may completing other BDs while we scan this list...
1059 *
1060 * RACE: we can notice OWN cleared before CPPI raises the
1061 * matching irq by writing that BD as the completion pointer.
1062 * In such cases, stop scanning and wait for the irq, avoiding
1063 * lost acks and states where BD ownership is unclear.
1064 */
1065 if (bd->dma == safe2ack) {
1066 musb_writel(&state->rx_complete, 0, safe2ack);
1067 safe2ack = musb_readl(&state->rx_complete, 0);
1068 acked = true;
1069 if (bd->dma == safe2ack)
1070 safe2ack = 0;
1071 }
1072
1073 rx->channel.actual_len += len;
1074
1075 cppi_bd_free(rx, last);
1076 last = bd;
1077
1078 /* stop scanning on end-of-segment */
1079 if (bd->hw_next == 0)
1080 completed = true;
1081 }
1082 rx->last_processed = last;
1083
1084 /* dma abort, lost ack, or ... */
1085 if (!acked && last) {
1086 int csr;
1087
1088 if (safe2ack == 0 || safe2ack == rx->last_processed->dma)
1089 musb_writel(&state->rx_complete, 0, safe2ack);
1090 if (safe2ack == 0) {
1091 cppi_bd_free(rx, last);
1092 rx->last_processed = NULL;
1093
1094 /* if we land here on the host side, H_REQPKT will
1095 * be clear and we need to restart the queue...
1096 */
1097 WARN_ON(rx->head);
1098 }
1099 musb_ep_select(cppi->mregs, rx->index + 1);
1100 csr = musb_readw(regs, MUSB_RXCSR);
1101 if (csr & MUSB_RXCSR_DMAENAB) {
1102 musb_dbg(musb, "list%d %p/%p, last %llx%s, csr %04x",
1103 rx->index,
1104 rx->head, rx->tail,
1105 rx->last_processed
1106 ? (unsigned long long)
1107 rx->last_processed->dma
1108 : 0,
1109 completed ? ", completed" : "",
1110 csr);
1111 cppi_dump_rxq(4, "/what?", rx);
1112 }
1113 }
1114 if (!completed) {
1115 int csr;
1116
1117 rx->head = bd;
1118
1119 /* REVISIT seems like "autoreq all but EOP" doesn't...
1120 * setting it here "should" be racey, but seems to work
1121 */
1122 csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR);
1123 if (is_host_active(cppi->controller.musb)
1124 && bd
1125 && !(csr & MUSB_RXCSR_H_REQPKT)) {
1126 csr |= MUSB_RXCSR_H_REQPKT;
1127 musb_writew(regs, MUSB_RXCSR,
1128 MUSB_RXCSR_H_WZC_BITS | csr);
1129 csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR);
1130 }
1131 } else {
1132 rx->head = NULL;
1133 rx->tail = NULL;
1134 }
1135
1136 cppi_dump_rx(6, rx, completed ? "/completed" : "/cleaned");
1137 return completed;
1138 }
1139
cppi_interrupt(int irq,void * dev_id)1140 irqreturn_t cppi_interrupt(int irq, void *dev_id)
1141 {
1142 struct musb *musb = dev_id;
1143 struct cppi *cppi;
1144 void __iomem *tibase;
1145 struct musb_hw_ep *hw_ep = NULL;
1146 u32 rx, tx;
1147 int i, index;
1148 unsigned long uninitialized_var(flags);
1149
1150 cppi = container_of(musb->dma_controller, struct cppi, controller);
1151 if (cppi->irq)
1152 spin_lock_irqsave(&musb->lock, flags);
1153
1154 tibase = musb->ctrl_base;
1155
1156 tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
1157 rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
1158
1159 if (!tx && !rx) {
1160 if (cppi->irq)
1161 spin_unlock_irqrestore(&musb->lock, flags);
1162 return IRQ_NONE;
1163 }
1164
1165 musb_dbg(musb, "CPPI IRQ Tx%x Rx%x", tx, rx);
1166
1167 /* process TX channels */
1168 for (index = 0; tx; tx = tx >> 1, index++) {
1169 struct cppi_channel *tx_ch;
1170 struct cppi_tx_stateram __iomem *tx_ram;
1171 bool completed = false;
1172 struct cppi_descriptor *bd;
1173
1174 if (!(tx & 1))
1175 continue;
1176
1177 tx_ch = cppi->tx + index;
1178 tx_ram = tx_ch->state_ram;
1179
1180 /* FIXME need a cppi_tx_scan() routine, which
1181 * can also be called from abort code
1182 */
1183
1184 cppi_dump_tx(5, tx_ch, "/E");
1185
1186 bd = tx_ch->head;
1187
1188 /*
1189 * If Head is null then this could mean that a abort interrupt
1190 * that needs to be acknowledged.
1191 */
1192 if (NULL == bd) {
1193 musb_dbg(musb, "null BD");
1194 musb_writel(&tx_ram->tx_complete, 0, 0);
1195 continue;
1196 }
1197
1198 /* run through all completed BDs */
1199 for (i = 0; !completed && bd && i < NUM_TXCHAN_BD;
1200 i++, bd = bd->next) {
1201 u16 len;
1202
1203 /* catch latest BD writes from CPPI */
1204 rmb();
1205 if (bd->hw_options & CPPI_OWN_SET)
1206 break;
1207
1208 musb_dbg(musb, "C/TXBD %p n %x b %x off %x opt %x",
1209 bd, bd->hw_next, bd->hw_bufp,
1210 bd->hw_off_len, bd->hw_options);
1211
1212 len = bd->hw_off_len & CPPI_BUFFER_LEN_MASK;
1213 tx_ch->channel.actual_len += len;
1214
1215 tx_ch->last_processed = bd;
1216
1217 /* write completion register to acknowledge
1218 * processing of completed BDs, and possibly
1219 * release the IRQ; EOQ might not be set ...
1220 *
1221 * REVISIT use the same ack strategy as rx
1222 *
1223 * REVISIT have observed bit 18 set; huh??
1224 */
1225 /* if ((bd->hw_options & CPPI_EOQ_MASK)) */
1226 musb_writel(&tx_ram->tx_complete, 0, bd->dma);
1227
1228 /* stop scanning on end-of-segment */
1229 if (bd->hw_next == 0)
1230 completed = true;
1231 }
1232
1233 /* on end of segment, maybe go to next one */
1234 if (completed) {
1235 /* cppi_dump_tx(4, tx_ch, "/complete"); */
1236
1237 /* transfer more, or report completion */
1238 if (tx_ch->offset >= tx_ch->buf_len) {
1239 tx_ch->head = NULL;
1240 tx_ch->tail = NULL;
1241 tx_ch->channel.status = MUSB_DMA_STATUS_FREE;
1242
1243 hw_ep = tx_ch->hw_ep;
1244
1245 musb_dma_completion(musb, index + 1, 1);
1246
1247 } else {
1248 /* Bigger transfer than we could fit in
1249 * that first batch of descriptors...
1250 */
1251 cppi_next_tx_segment(musb, tx_ch);
1252 }
1253 } else
1254 tx_ch->head = bd;
1255 }
1256
1257 /* Start processing the RX block */
1258 for (index = 0; rx; rx = rx >> 1, index++) {
1259
1260 if (rx & 1) {
1261 struct cppi_channel *rx_ch;
1262
1263 rx_ch = cppi->rx + index;
1264
1265 /* let incomplete dma segments finish */
1266 if (!cppi_rx_scan(cppi, index))
1267 continue;
1268
1269 /* start another dma segment if needed */
1270 if (rx_ch->channel.actual_len != rx_ch->buf_len
1271 && rx_ch->channel.actual_len
1272 == rx_ch->offset) {
1273 cppi_next_rx_segment(musb, rx_ch, 1);
1274 continue;
1275 }
1276
1277 /* all segments completed! */
1278 rx_ch->channel.status = MUSB_DMA_STATUS_FREE;
1279
1280 hw_ep = rx_ch->hw_ep;
1281
1282 core_rxirq_disable(tibase, index + 1);
1283 musb_dma_completion(musb, index + 1, 0);
1284 }
1285 }
1286
1287 /* write to CPPI EOI register to re-enable interrupts */
1288 musb_writel(tibase, DAVINCI_CPPI_EOI_REG, 0);
1289
1290 if (cppi->irq)
1291 spin_unlock_irqrestore(&musb->lock, flags);
1292
1293 return IRQ_HANDLED;
1294 }
1295 EXPORT_SYMBOL_GPL(cppi_interrupt);
1296
1297 /* Instantiate a software object representing a DMA controller. */
1298 struct dma_controller *
cppi_dma_controller_create(struct musb * musb,void __iomem * mregs)1299 cppi_dma_controller_create(struct musb *musb, void __iomem *mregs)
1300 {
1301 struct cppi *controller;
1302 struct device *dev = musb->controller;
1303 struct platform_device *pdev = to_platform_device(dev);
1304 int irq = platform_get_irq_byname(pdev, "dma");
1305
1306 controller = kzalloc(sizeof *controller, GFP_KERNEL);
1307 if (!controller)
1308 return NULL;
1309
1310 controller->mregs = mregs;
1311 controller->tibase = mregs - DAVINCI_BASE_OFFSET;
1312
1313 controller->controller.musb = musb;
1314 controller->controller.channel_alloc = cppi_channel_allocate;
1315 controller->controller.channel_release = cppi_channel_release;
1316 controller->controller.channel_program = cppi_channel_program;
1317 controller->controller.channel_abort = cppi_channel_abort;
1318
1319 /* NOTE: allocating from on-chip SRAM would give the least
1320 * contention for memory access, if that ever matters here.
1321 */
1322
1323 /* setup BufferPool */
1324 controller->pool = dma_pool_create("cppi",
1325 controller->controller.musb->controller,
1326 sizeof(struct cppi_descriptor),
1327 CPPI_DESCRIPTOR_ALIGN, 0);
1328 if (!controller->pool) {
1329 kfree(controller);
1330 return NULL;
1331 }
1332
1333 if (irq > 0) {
1334 if (request_irq(irq, cppi_interrupt, 0, "cppi-dma", musb)) {
1335 dev_err(dev, "request_irq %d failed!\n", irq);
1336 musb_dma_controller_destroy(&controller->controller);
1337 return NULL;
1338 }
1339 controller->irq = irq;
1340 }
1341
1342 cppi_controller_start(controller);
1343 return &controller->controller;
1344 }
1345 EXPORT_SYMBOL_GPL(cppi_dma_controller_create);
1346
1347 /*
1348 * Destroy a previously-instantiated DMA controller.
1349 */
cppi_dma_controller_destroy(struct dma_controller * c)1350 void cppi_dma_controller_destroy(struct dma_controller *c)
1351 {
1352 struct cppi *cppi;
1353
1354 cppi = container_of(c, struct cppi, controller);
1355
1356 cppi_controller_stop(cppi);
1357
1358 if (cppi->irq)
1359 free_irq(cppi->irq, cppi->controller.musb);
1360
1361 /* assert: caller stopped the controller first */
1362 dma_pool_destroy(cppi->pool);
1363
1364 kfree(cppi);
1365 }
1366 EXPORT_SYMBOL_GPL(cppi_dma_controller_destroy);
1367
1368 /*
1369 * Context: controller irqlocked, endpoint selected
1370 */
cppi_channel_abort(struct dma_channel * channel)1371 static int cppi_channel_abort(struct dma_channel *channel)
1372 {
1373 struct cppi_channel *cppi_ch;
1374 struct cppi *controller;
1375 void __iomem *mbase;
1376 void __iomem *tibase;
1377 void __iomem *regs;
1378 u32 value;
1379 struct cppi_descriptor *queue;
1380
1381 cppi_ch = container_of(channel, struct cppi_channel, channel);
1382
1383 controller = cppi_ch->controller;
1384
1385 switch (channel->status) {
1386 case MUSB_DMA_STATUS_BUS_ABORT:
1387 case MUSB_DMA_STATUS_CORE_ABORT:
1388 /* from RX or TX fault irq handler */
1389 case MUSB_DMA_STATUS_BUSY:
1390 /* the hardware needs shutting down */
1391 regs = cppi_ch->hw_ep->regs;
1392 break;
1393 case MUSB_DMA_STATUS_UNKNOWN:
1394 case MUSB_DMA_STATUS_FREE:
1395 return 0;
1396 default:
1397 return -EINVAL;
1398 }
1399
1400 if (!cppi_ch->transmit && cppi_ch->head)
1401 cppi_dump_rxq(3, "/abort", cppi_ch);
1402
1403 mbase = controller->mregs;
1404 tibase = controller->tibase;
1405
1406 queue = cppi_ch->head;
1407 cppi_ch->head = NULL;
1408 cppi_ch->tail = NULL;
1409
1410 /* REVISIT should rely on caller having done this,
1411 * and caller should rely on us not changing it.
1412 * peripheral code is safe ... check host too.
1413 */
1414 musb_ep_select(mbase, cppi_ch->index + 1);
1415
1416 if (cppi_ch->transmit) {
1417 struct cppi_tx_stateram __iomem *tx_ram;
1418 /* REVISIT put timeouts on these controller handshakes */
1419
1420 cppi_dump_tx(6, cppi_ch, " (teardown)");
1421
1422 /* teardown DMA engine then usb core */
1423 do {
1424 value = musb_readl(tibase, DAVINCI_TXCPPI_TEAR_REG);
1425 } while (!(value & CPPI_TEAR_READY));
1426 musb_writel(tibase, DAVINCI_TXCPPI_TEAR_REG, cppi_ch->index);
1427
1428 tx_ram = cppi_ch->state_ram;
1429 do {
1430 value = musb_readl(&tx_ram->tx_complete, 0);
1431 } while (0xFFFFFFFC != value);
1432
1433 /* FIXME clean up the transfer state ... here?
1434 * the completion routine should get called with
1435 * an appropriate status code.
1436 */
1437
1438 value = musb_readw(regs, MUSB_TXCSR);
1439 value &= ~MUSB_TXCSR_DMAENAB;
1440 value |= MUSB_TXCSR_FLUSHFIFO;
1441 musb_writew(regs, MUSB_TXCSR, value);
1442 musb_writew(regs, MUSB_TXCSR, value);
1443
1444 /*
1445 * 1. Write to completion Ptr value 0x1(bit 0 set)
1446 * (write back mode)
1447 * 2. Wait for abort interrupt and then put the channel in
1448 * compare mode by writing 1 to the tx_complete register.
1449 */
1450 cppi_reset_tx(tx_ram, 1);
1451 cppi_ch->head = NULL;
1452 musb_writel(&tx_ram->tx_complete, 0, 1);
1453 cppi_dump_tx(5, cppi_ch, " (done teardown)");
1454
1455 /* REVISIT tx side _should_ clean up the same way
1456 * as the RX side ... this does no cleanup at all!
1457 */
1458
1459 } else /* RX */ {
1460 u16 csr;
1461
1462 /* NOTE: docs don't guarantee any of this works ... we
1463 * expect that if the usb core stops telling the cppi core
1464 * to pull more data from it, then it'll be safe to flush
1465 * current RX DMA state iff any pending fifo transfer is done.
1466 */
1467
1468 core_rxirq_disable(tibase, cppi_ch->index + 1);
1469
1470 /* for host, ensure ReqPkt is never set again */
1471 if (is_host_active(cppi_ch->controller->controller.musb)) {
1472 value = musb_readl(tibase, DAVINCI_AUTOREQ_REG);
1473 value &= ~((0x3) << (cppi_ch->index * 2));
1474 musb_writel(tibase, DAVINCI_AUTOREQ_REG, value);
1475 }
1476
1477 csr = musb_readw(regs, MUSB_RXCSR);
1478
1479 /* for host, clear (just) ReqPkt at end of current packet(s) */
1480 if (is_host_active(cppi_ch->controller->controller.musb)) {
1481 csr |= MUSB_RXCSR_H_WZC_BITS;
1482 csr &= ~MUSB_RXCSR_H_REQPKT;
1483 } else
1484 csr |= MUSB_RXCSR_P_WZC_BITS;
1485
1486 /* clear dma enable */
1487 csr &= ~(MUSB_RXCSR_DMAENAB);
1488 musb_writew(regs, MUSB_RXCSR, csr);
1489 csr = musb_readw(regs, MUSB_RXCSR);
1490
1491 /* Quiesce: wait for current dma to finish (if not cleanup).
1492 * We can't use bit zero of stateram->rx_sop, since that
1493 * refers to an entire "DMA packet" not just emptying the
1494 * current fifo. Most segments need multiple usb packets.
1495 */
1496 if (channel->status == MUSB_DMA_STATUS_BUSY)
1497 udelay(50);
1498
1499 /* scan the current list, reporting any data that was
1500 * transferred and acking any IRQ
1501 */
1502 cppi_rx_scan(controller, cppi_ch->index);
1503
1504 /* clobber the existing state once it's idle
1505 *
1506 * NOTE: arguably, we should also wait for all the other
1507 * RX channels to quiesce (how??) and then temporarily
1508 * disable RXCPPI_CTRL_REG ... but it seems that we can
1509 * rely on the controller restarting from state ram, with
1510 * only RXCPPI_BUFCNT state being bogus. BUFCNT will
1511 * correct itself after the next DMA transfer though.
1512 *
1513 * REVISIT does using rndis mode change that?
1514 */
1515 cppi_reset_rx(cppi_ch->state_ram);
1516
1517 /* next DMA request _should_ load cppi head ptr */
1518
1519 /* ... we don't "free" that list, only mutate it in place. */
1520 cppi_dump_rx(5, cppi_ch, " (done abort)");
1521
1522 /* clean up previously pending bds */
1523 cppi_bd_free(cppi_ch, cppi_ch->last_processed);
1524 cppi_ch->last_processed = NULL;
1525
1526 while (queue) {
1527 struct cppi_descriptor *tmp = queue->next;
1528
1529 cppi_bd_free(cppi_ch, queue);
1530 queue = tmp;
1531 }
1532 }
1533
1534 channel->status = MUSB_DMA_STATUS_FREE;
1535 cppi_ch->buf_dma = 0;
1536 cppi_ch->offset = 0;
1537 cppi_ch->buf_len = 0;
1538 cppi_ch->maxpacket = 0;
1539 return 0;
1540 }
1541
1542 /* TBD Queries:
1543 *
1544 * Power Management ... probably turn off cppi during suspend, restart;
1545 * check state ram? Clocking is presumably shared with usb core.
1546 */
1547