1 /*
2 * Texas Instruments DSPS platforms "glue layer"
3 *
4 * Copyright (C) 2012, by Texas Instruments
5 *
6 * Based on the am35x "glue layer" code.
7 *
8 * This file is part of the Inventra Controller Driver for Linux.
9 *
10 * The Inventra Controller Driver for Linux is free software; you
11 * can redistribute it and/or modify it under the terms of the GNU
12 * General Public License version 2 as published by the Free Software
13 * Foundation.
14 *
15 * The Inventra Controller Driver for Linux is distributed in
16 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
17 * without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 * License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with The Inventra Controller Driver for Linux ; if not,
23 * write to the Free Software Foundation, Inc., 59 Temple Place,
24 * Suite 330, Boston, MA 02111-1307 USA
25 *
26 * musb_dsps.c will be a common file for all the TI DSPS platforms
27 * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x.
28 * For now only ti81x is using this and in future davinci.c, am35x.c
29 * da8xx.c would be merged to this file after testing.
30 */
31
32 #include <linux/io.h>
33 #include <linux/err.h>
34 #include <linux/platform_device.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/module.h>
38 #include <linux/usb/usb_phy_generic.h>
39 #include <linux/platform_data/usb-omap.h>
40 #include <linux/sizes.h>
41
42 #include <linux/of.h>
43 #include <linux/of_device.h>
44 #include <linux/of_address.h>
45 #include <linux/of_irq.h>
46 #include <linux/usb/of.h>
47
48 #include <linux/debugfs.h>
49
50 #include "musb_core.h"
51
52 static const struct of_device_id musb_dsps_of_match[];
53
54 /**
55 * DSPS musb wrapper register offset.
56 * FIXME: This should be expanded to have all the wrapper registers from TI DSPS
57 * musb ips.
58 */
59 struct dsps_musb_wrapper {
60 u16 revision;
61 u16 control;
62 u16 status;
63 u16 epintr_set;
64 u16 epintr_clear;
65 u16 epintr_status;
66 u16 coreintr_set;
67 u16 coreintr_clear;
68 u16 coreintr_status;
69 u16 phy_utmi;
70 u16 mode;
71 u16 tx_mode;
72 u16 rx_mode;
73
74 /* bit positions for control */
75 unsigned reset:5;
76
77 /* bit positions for interrupt */
78 unsigned usb_shift:5;
79 u32 usb_mask;
80 u32 usb_bitmap;
81 unsigned drvvbus:5;
82
83 unsigned txep_shift:5;
84 u32 txep_mask;
85 u32 txep_bitmap;
86
87 unsigned rxep_shift:5;
88 u32 rxep_mask;
89 u32 rxep_bitmap;
90
91 /* bit positions for phy_utmi */
92 unsigned otg_disable:5;
93
94 /* bit positions for mode */
95 unsigned iddig:5;
96 unsigned iddig_mux:5;
97 /* miscellaneous stuff */
98 unsigned poll_timeout;
99 };
100
101 /*
102 * register shadow for suspend
103 */
104 struct dsps_context {
105 u32 control;
106 u32 epintr;
107 u32 coreintr;
108 u32 phy_utmi;
109 u32 mode;
110 u32 tx_mode;
111 u32 rx_mode;
112 };
113
114 /**
115 * DSPS glue structure.
116 */
117 struct dsps_glue {
118 struct device *dev;
119 struct platform_device *musb; /* child musb pdev */
120 const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */
121 int vbus_irq; /* optional vbus irq */
122 struct timer_list timer; /* otg_workaround timer */
123 unsigned long last_timer; /* last timer data for each instance */
124 bool sw_babble_enabled;
125 void __iomem *usbss_base;
126
127 struct dsps_context context;
128 struct debugfs_regset32 regset;
129 struct dentry *dbgfs_root;
130 };
131
132 static const struct debugfs_reg32 dsps_musb_regs[] = {
133 { "revision", 0x00 },
134 { "control", 0x14 },
135 { "status", 0x18 },
136 { "eoi", 0x24 },
137 { "intr0_stat", 0x30 },
138 { "intr1_stat", 0x34 },
139 { "intr0_set", 0x38 },
140 { "intr1_set", 0x3c },
141 { "txmode", 0x70 },
142 { "rxmode", 0x74 },
143 { "autoreq", 0xd0 },
144 { "srpfixtime", 0xd4 },
145 { "tdown", 0xd8 },
146 { "phy_utmi", 0xe0 },
147 { "mode", 0xe8 },
148 };
149
dsps_mod_timer(struct dsps_glue * glue,int wait_ms)150 static void dsps_mod_timer(struct dsps_glue *glue, int wait_ms)
151 {
152 int wait;
153
154 if (wait_ms < 0)
155 wait = msecs_to_jiffies(glue->wrp->poll_timeout);
156 else
157 wait = msecs_to_jiffies(wait_ms);
158
159 mod_timer(&glue->timer, jiffies + wait);
160 }
161
162 /*
163 * If no vbus irq from the PMIC is configured, we need to poll VBUS status.
164 */
dsps_mod_timer_optional(struct dsps_glue * glue)165 static void dsps_mod_timer_optional(struct dsps_glue *glue)
166 {
167 if (glue->vbus_irq)
168 return;
169
170 dsps_mod_timer(glue, -1);
171 }
172
173 /* USBSS / USB AM335x */
174 #define USBSS_IRQ_STATUS 0x28
175 #define USBSS_IRQ_ENABLER 0x2c
176 #define USBSS_IRQ_CLEARR 0x30
177
178 #define USBSS_IRQ_PD_COMP (1 << 2)
179
180 /**
181 * dsps_musb_enable - enable interrupts
182 */
dsps_musb_enable(struct musb * musb)183 static void dsps_musb_enable(struct musb *musb)
184 {
185 struct device *dev = musb->controller;
186 struct platform_device *pdev = to_platform_device(dev->parent);
187 struct dsps_glue *glue = platform_get_drvdata(pdev);
188 const struct dsps_musb_wrapper *wrp = glue->wrp;
189 void __iomem *reg_base = musb->ctrl_base;
190 u32 epmask, coremask;
191
192 /* Workaround: setup IRQs through both register sets. */
193 epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) |
194 ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift);
195 coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF);
196
197 musb_writel(reg_base, wrp->epintr_set, epmask);
198 musb_writel(reg_base, wrp->coreintr_set, coremask);
199 /* start polling for ID change in dual-role idle mode */
200 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE &&
201 musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
202 dsps_mod_timer(glue, -1);
203 }
204
205 /**
206 * dsps_musb_disable - disable HDRC and flush interrupts
207 */
dsps_musb_disable(struct musb * musb)208 static void dsps_musb_disable(struct musb *musb)
209 {
210 struct device *dev = musb->controller;
211 struct platform_device *pdev = to_platform_device(dev->parent);
212 struct dsps_glue *glue = platform_get_drvdata(pdev);
213 const struct dsps_musb_wrapper *wrp = glue->wrp;
214 void __iomem *reg_base = musb->ctrl_base;
215
216 musb_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
217 musb_writel(reg_base, wrp->epintr_clear,
218 wrp->txep_bitmap | wrp->rxep_bitmap);
219 del_timer_sync(&glue->timer);
220 }
221
222 /* Caller must take musb->lock */
dsps_check_status(struct musb * musb,void * unused)223 static int dsps_check_status(struct musb *musb, void *unused)
224 {
225 void __iomem *mregs = musb->mregs;
226 struct device *dev = musb->controller;
227 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
228 const struct dsps_musb_wrapper *wrp = glue->wrp;
229 u8 devctl;
230 int skip_session = 0;
231
232 if (glue->vbus_irq)
233 del_timer(&glue->timer);
234
235 /*
236 * We poll because DSPS IP's won't expose several OTG-critical
237 * status change events (from the transceiver) otherwise.
238 */
239 devctl = musb_readb(mregs, MUSB_DEVCTL);
240 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
241 usb_otg_state_string(musb->xceiv->otg->state));
242
243 switch (musb->xceiv->otg->state) {
244 case OTG_STATE_A_WAIT_VRISE:
245 if (musb->port_mode == MUSB_HOST) {
246 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
247 dsps_mod_timer_optional(glue);
248 break;
249 }
250 /* fall through */
251
252 case OTG_STATE_A_WAIT_BCON:
253 /* keep VBUS on for host-only mode */
254 if (musb->port_mode == MUSB_PORT_MODE_HOST) {
255 dsps_mod_timer_optional(glue);
256 break;
257 }
258 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
259 skip_session = 1;
260 /* fall */
261
262 case OTG_STATE_A_IDLE:
263 case OTG_STATE_B_IDLE:
264 if (!glue->vbus_irq) {
265 if (devctl & MUSB_DEVCTL_BDEVICE) {
266 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
267 MUSB_DEV_MODE(musb);
268 } else {
269 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
270 MUSB_HST_MODE(musb);
271 }
272 if (!(devctl & MUSB_DEVCTL_SESSION) && !skip_session)
273 musb_writeb(mregs, MUSB_DEVCTL,
274 MUSB_DEVCTL_SESSION);
275 }
276 dsps_mod_timer_optional(glue);
277 break;
278 case OTG_STATE_A_WAIT_VFALL:
279 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
280 musb_writel(musb->ctrl_base, wrp->coreintr_set,
281 MUSB_INTR_VBUSERROR << wrp->usb_shift);
282 break;
283 default:
284 break;
285 }
286
287 return 0;
288 }
289
otg_timer(unsigned long _musb)290 static void otg_timer(unsigned long _musb)
291 {
292 struct musb *musb = (void *)_musb;
293 struct device *dev = musb->controller;
294 unsigned long flags;
295 int err;
296
297 err = pm_runtime_get(dev);
298 if ((err != -EINPROGRESS) && err < 0) {
299 dev_err(dev, "Poll could not pm_runtime_get: %i\n", err);
300 pm_runtime_put_noidle(dev);
301
302 return;
303 }
304
305 spin_lock_irqsave(&musb->lock, flags);
306 err = musb_queue_resume_work(musb, dsps_check_status, NULL);
307 if (err < 0)
308 dev_err(dev, "%s resume work: %i\n", __func__, err);
309 spin_unlock_irqrestore(&musb->lock, flags);
310 pm_runtime_mark_last_busy(dev);
311 pm_runtime_put_autosuspend(dev);
312 }
313
dsps_musb_clear_ep_rxintr(struct musb * musb,int epnum)314 static void dsps_musb_clear_ep_rxintr(struct musb *musb, int epnum)
315 {
316 u32 epintr;
317 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
318 const struct dsps_musb_wrapper *wrp = glue->wrp;
319
320 /* musb->lock might already been held */
321 epintr = (1 << epnum) << wrp->rxep_shift;
322 musb_writel(musb->ctrl_base, wrp->epintr_status, epintr);
323 }
324
dsps_interrupt(int irq,void * hci)325 static irqreturn_t dsps_interrupt(int irq, void *hci)
326 {
327 struct musb *musb = hci;
328 void __iomem *reg_base = musb->ctrl_base;
329 struct device *dev = musb->controller;
330 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
331 const struct dsps_musb_wrapper *wrp = glue->wrp;
332 unsigned long flags;
333 irqreturn_t ret = IRQ_NONE;
334 u32 epintr, usbintr;
335
336 spin_lock_irqsave(&musb->lock, flags);
337
338 /* Get endpoint interrupts */
339 epintr = musb_readl(reg_base, wrp->epintr_status);
340 musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift;
341 musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift;
342
343 if (epintr)
344 musb_writel(reg_base, wrp->epintr_status, epintr);
345
346 /* Get usb core interrupts */
347 usbintr = musb_readl(reg_base, wrp->coreintr_status);
348 if (!usbintr && !epintr)
349 goto out;
350
351 musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift;
352 if (usbintr)
353 musb_writel(reg_base, wrp->coreintr_status, usbintr);
354
355 dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n",
356 usbintr, epintr);
357
358 if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) {
359 int drvvbus = musb_readl(reg_base, wrp->status);
360 void __iomem *mregs = musb->mregs;
361 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
362 int err;
363
364 err = musb->int_usb & MUSB_INTR_VBUSERROR;
365 if (err) {
366 /*
367 * The Mentor core doesn't debounce VBUS as needed
368 * to cope with device connect current spikes. This
369 * means it's not uncommon for bus-powered devices
370 * to get VBUS errors during enumeration.
371 *
372 * This is a workaround, but newer RTL from Mentor
373 * seems to allow a better one: "re"-starting sessions
374 * without waiting for VBUS to stop registering in
375 * devctl.
376 */
377 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
378 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
379 dsps_mod_timer_optional(glue);
380 WARNING("VBUS error workaround (delay coming)\n");
381 } else if (drvvbus) {
382 MUSB_HST_MODE(musb);
383 musb->xceiv->otg->default_a = 1;
384 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
385 dsps_mod_timer_optional(glue);
386 } else {
387 musb->is_active = 0;
388 MUSB_DEV_MODE(musb);
389 musb->xceiv->otg->default_a = 0;
390 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
391 }
392
393 /* NOTE: this must complete power-on within 100 ms. */
394 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
395 drvvbus ? "on" : "off",
396 usb_otg_state_string(musb->xceiv->otg->state),
397 err ? " ERROR" : "",
398 devctl);
399 ret = IRQ_HANDLED;
400 }
401
402 if (musb->int_tx || musb->int_rx || musb->int_usb)
403 ret |= musb_interrupt(musb);
404
405 /* Poll for ID change and connect */
406 switch (musb->xceiv->otg->state) {
407 case OTG_STATE_B_IDLE:
408 case OTG_STATE_A_WAIT_BCON:
409 dsps_mod_timer_optional(glue);
410 break;
411 default:
412 break;
413 }
414
415 out:
416 spin_unlock_irqrestore(&musb->lock, flags);
417
418 return ret;
419 }
420
dsps_musb_dbg_init(struct musb * musb,struct dsps_glue * glue)421 static int dsps_musb_dbg_init(struct musb *musb, struct dsps_glue *glue)
422 {
423 struct dentry *root;
424 struct dentry *file;
425 char buf[128];
426
427 sprintf(buf, "%s.dsps", dev_name(musb->controller));
428 root = debugfs_create_dir(buf, NULL);
429 if (!root)
430 return -ENOMEM;
431 glue->dbgfs_root = root;
432
433 glue->regset.regs = dsps_musb_regs;
434 glue->regset.nregs = ARRAY_SIZE(dsps_musb_regs);
435 glue->regset.base = musb->ctrl_base;
436
437 file = debugfs_create_regset32("regdump", S_IRUGO, root, &glue->regset);
438 if (!file) {
439 debugfs_remove_recursive(root);
440 return -ENOMEM;
441 }
442 return 0;
443 }
444
dsps_musb_init(struct musb * musb)445 static int dsps_musb_init(struct musb *musb)
446 {
447 struct device *dev = musb->controller;
448 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
449 struct platform_device *parent = to_platform_device(dev->parent);
450 const struct dsps_musb_wrapper *wrp = glue->wrp;
451 void __iomem *reg_base;
452 struct resource *r;
453 u32 rev, val;
454 int ret;
455
456 r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control");
457 reg_base = devm_ioremap_resource(dev, r);
458 if (IS_ERR(reg_base))
459 return PTR_ERR(reg_base);
460 musb->ctrl_base = reg_base;
461
462 /* NOP driver needs change if supporting dual instance */
463 musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent, "phys", 0);
464 if (IS_ERR(musb->xceiv))
465 return PTR_ERR(musb->xceiv);
466
467 musb->phy = devm_phy_get(dev->parent, "usb2-phy");
468
469 /* Returns zero if e.g. not clocked */
470 rev = musb_readl(reg_base, wrp->revision);
471 if (!rev)
472 return -ENODEV;
473
474 usb_phy_init(musb->xceiv);
475 if (IS_ERR(musb->phy)) {
476 musb->phy = NULL;
477 } else {
478 ret = phy_init(musb->phy);
479 if (ret < 0)
480 return ret;
481 ret = phy_power_on(musb->phy);
482 if (ret) {
483 phy_exit(musb->phy);
484 return ret;
485 }
486 }
487
488 setup_timer(&glue->timer, otg_timer, (unsigned long) musb);
489
490 /* Reset the musb */
491 musb_writel(reg_base, wrp->control, (1 << wrp->reset));
492
493 musb->isr = dsps_interrupt;
494
495 /* reset the otgdisable bit, needed for host mode to work */
496 val = musb_readl(reg_base, wrp->phy_utmi);
497 val &= ~(1 << wrp->otg_disable);
498 musb_writel(musb->ctrl_base, wrp->phy_utmi, val);
499
500 /*
501 * Check whether the dsps version has babble control enabled.
502 * In latest silicon revision the babble control logic is enabled.
503 * If MUSB_BABBLE_CTL returns 0x4 then we have the babble control
504 * logic enabled.
505 */
506 val = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
507 if (val & MUSB_BABBLE_RCV_DISABLE) {
508 glue->sw_babble_enabled = true;
509 val |= MUSB_BABBLE_SW_SESSION_CTRL;
510 musb_writeb(musb->mregs, MUSB_BABBLE_CTL, val);
511 }
512
513 dsps_mod_timer(glue, -1);
514
515 return dsps_musb_dbg_init(musb, glue);
516 }
517
dsps_musb_exit(struct musb * musb)518 static int dsps_musb_exit(struct musb *musb)
519 {
520 struct device *dev = musb->controller;
521 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
522
523 del_timer_sync(&glue->timer);
524 usb_phy_shutdown(musb->xceiv);
525 phy_power_off(musb->phy);
526 phy_exit(musb->phy);
527 debugfs_remove_recursive(glue->dbgfs_root);
528
529 return 0;
530 }
531
dsps_musb_set_mode(struct musb * musb,u8 mode)532 static int dsps_musb_set_mode(struct musb *musb, u8 mode)
533 {
534 struct device *dev = musb->controller;
535 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
536 const struct dsps_musb_wrapper *wrp = glue->wrp;
537 void __iomem *ctrl_base = musb->ctrl_base;
538 u32 reg;
539
540 reg = musb_readl(ctrl_base, wrp->mode);
541
542 switch (mode) {
543 case MUSB_HOST:
544 reg &= ~(1 << wrp->iddig);
545
546 /*
547 * if we're setting mode to host-only or device-only, we're
548 * going to ignore whatever the PHY sends us and just force
549 * ID pin status by SW
550 */
551 reg |= (1 << wrp->iddig_mux);
552
553 musb_writel(ctrl_base, wrp->mode, reg);
554 musb_writel(ctrl_base, wrp->phy_utmi, 0x02);
555 break;
556 case MUSB_PERIPHERAL:
557 reg |= (1 << wrp->iddig);
558
559 /*
560 * if we're setting mode to host-only or device-only, we're
561 * going to ignore whatever the PHY sends us and just force
562 * ID pin status by SW
563 */
564 reg |= (1 << wrp->iddig_mux);
565
566 musb_writel(ctrl_base, wrp->mode, reg);
567 break;
568 case MUSB_OTG:
569 musb_writel(ctrl_base, wrp->phy_utmi, 0x02);
570 break;
571 default:
572 dev_err(glue->dev, "unsupported mode %d\n", mode);
573 return -EINVAL;
574 }
575
576 return 0;
577 }
578
dsps_sw_babble_control(struct musb * musb)579 static bool dsps_sw_babble_control(struct musb *musb)
580 {
581 u8 babble_ctl;
582 bool session_restart = false;
583
584 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
585 dev_dbg(musb->controller, "babble: MUSB_BABBLE_CTL value %x\n",
586 babble_ctl);
587 /*
588 * check line monitor flag to check whether babble is
589 * due to noise
590 */
591 dev_dbg(musb->controller, "STUCK_J is %s\n",
592 babble_ctl & MUSB_BABBLE_STUCK_J ? "set" : "reset");
593
594 if (babble_ctl & MUSB_BABBLE_STUCK_J) {
595 int timeout = 10;
596
597 /*
598 * babble is due to noise, then set transmit idle (d7 bit)
599 * to resume normal operation
600 */
601 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
602 babble_ctl |= MUSB_BABBLE_FORCE_TXIDLE;
603 musb_writeb(musb->mregs, MUSB_BABBLE_CTL, babble_ctl);
604
605 /* wait till line monitor flag cleared */
606 dev_dbg(musb->controller, "Set TXIDLE, wait J to clear\n");
607 do {
608 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
609 udelay(1);
610 } while ((babble_ctl & MUSB_BABBLE_STUCK_J) && timeout--);
611
612 /* check whether stuck_at_j bit cleared */
613 if (babble_ctl & MUSB_BABBLE_STUCK_J) {
614 /*
615 * real babble condition has occurred
616 * restart the controller to start the
617 * session again
618 */
619 dev_dbg(musb->controller, "J not cleared, misc (%x)\n",
620 babble_ctl);
621 session_restart = true;
622 }
623 } else {
624 session_restart = true;
625 }
626
627 return session_restart;
628 }
629
dsps_musb_recover(struct musb * musb)630 static int dsps_musb_recover(struct musb *musb)
631 {
632 struct device *dev = musb->controller;
633 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
634 int session_restart = 0;
635
636 if (glue->sw_babble_enabled)
637 session_restart = dsps_sw_babble_control(musb);
638 else
639 session_restart = 1;
640
641 return session_restart ? 0 : -EPIPE;
642 }
643
644 /* Similar to am35x, dm81xx support only 32-bit read operation */
dsps_read_fifo32(struct musb_hw_ep * hw_ep,u16 len,u8 * dst)645 static void dsps_read_fifo32(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
646 {
647 void __iomem *fifo = hw_ep->fifo;
648
649 if (len >= 4) {
650 ioread32_rep(fifo, dst, len >> 2);
651 dst += len & ~0x03;
652 len &= 0x03;
653 }
654
655 /* Read any remaining 1 to 3 bytes */
656 if (len > 0) {
657 u32 val = musb_readl(fifo, 0);
658 memcpy(dst, &val, len);
659 }
660 }
661
662 #ifdef CONFIG_USB_TI_CPPI41_DMA
dsps_dma_controller_callback(struct dma_controller * c)663 static void dsps_dma_controller_callback(struct dma_controller *c)
664 {
665 struct musb *musb = c->musb;
666 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
667 void __iomem *usbss_base = glue->usbss_base;
668 u32 status;
669
670 status = musb_readl(usbss_base, USBSS_IRQ_STATUS);
671 if (status & USBSS_IRQ_PD_COMP)
672 musb_writel(usbss_base, USBSS_IRQ_STATUS, USBSS_IRQ_PD_COMP);
673 }
674
675 static struct dma_controller *
dsps_dma_controller_create(struct musb * musb,void __iomem * base)676 dsps_dma_controller_create(struct musb *musb, void __iomem *base)
677 {
678 struct dma_controller *controller;
679 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
680 void __iomem *usbss_base = glue->usbss_base;
681
682 controller = cppi41_dma_controller_create(musb, base);
683 if (IS_ERR_OR_NULL(controller))
684 return controller;
685
686 musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP);
687 controller->dma_callback = dsps_dma_controller_callback;
688
689 return controller;
690 }
691
692 #ifdef CONFIG_PM_SLEEP
dsps_dma_controller_suspend(struct dsps_glue * glue)693 static void dsps_dma_controller_suspend(struct dsps_glue *glue)
694 {
695 void __iomem *usbss_base = glue->usbss_base;
696
697 musb_writel(usbss_base, USBSS_IRQ_CLEARR, USBSS_IRQ_PD_COMP);
698 }
699
dsps_dma_controller_resume(struct dsps_glue * glue)700 static void dsps_dma_controller_resume(struct dsps_glue *glue)
701 {
702 void __iomem *usbss_base = glue->usbss_base;
703
704 musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP);
705 }
706 #endif
707 #else /* CONFIG_USB_TI_CPPI41_DMA */
708 #ifdef CONFIG_PM_SLEEP
dsps_dma_controller_suspend(struct dsps_glue * glue)709 static void dsps_dma_controller_suspend(struct dsps_glue *glue) {}
dsps_dma_controller_resume(struct dsps_glue * glue)710 static void dsps_dma_controller_resume(struct dsps_glue *glue) {}
711 #endif
712 #endif /* CONFIG_USB_TI_CPPI41_DMA */
713
714 static struct musb_platform_ops dsps_ops = {
715 .quirks = MUSB_DMA_CPPI41 | MUSB_INDEXED_EP,
716 .init = dsps_musb_init,
717 .exit = dsps_musb_exit,
718
719 #ifdef CONFIG_USB_TI_CPPI41_DMA
720 .dma_init = dsps_dma_controller_create,
721 .dma_exit = cppi41_dma_controller_destroy,
722 #endif
723 .enable = dsps_musb_enable,
724 .disable = dsps_musb_disable,
725
726 .set_mode = dsps_musb_set_mode,
727 .recover = dsps_musb_recover,
728 .clear_ep_rxintr = dsps_musb_clear_ep_rxintr,
729 };
730
731 static u64 musb_dmamask = DMA_BIT_MASK(32);
732
get_int_prop(struct device_node * dn,const char * s)733 static int get_int_prop(struct device_node *dn, const char *s)
734 {
735 int ret;
736 u32 val;
737
738 ret = of_property_read_u32(dn, s, &val);
739 if (ret)
740 return 0;
741 return val;
742 }
743
get_musb_port_mode(struct device * dev)744 static int get_musb_port_mode(struct device *dev)
745 {
746 enum usb_dr_mode mode;
747
748 mode = usb_get_dr_mode(dev);
749 switch (mode) {
750 case USB_DR_MODE_HOST:
751 return MUSB_PORT_MODE_HOST;
752
753 case USB_DR_MODE_PERIPHERAL:
754 return MUSB_PORT_MODE_GADGET;
755
756 case USB_DR_MODE_UNKNOWN:
757 case USB_DR_MODE_OTG:
758 default:
759 return MUSB_PORT_MODE_DUAL_ROLE;
760 }
761 }
762
dsps_create_musb_pdev(struct dsps_glue * glue,struct platform_device * parent)763 static int dsps_create_musb_pdev(struct dsps_glue *glue,
764 struct platform_device *parent)
765 {
766 struct musb_hdrc_platform_data pdata;
767 struct resource resources[2];
768 struct resource *res;
769 struct device *dev = &parent->dev;
770 struct musb_hdrc_config *config;
771 struct platform_device *musb;
772 struct device_node *dn = parent->dev.of_node;
773 int ret, val;
774
775 memset(resources, 0, sizeof(resources));
776 res = platform_get_resource_byname(parent, IORESOURCE_MEM, "mc");
777 if (!res) {
778 dev_err(dev, "failed to get memory.\n");
779 return -EINVAL;
780 }
781 resources[0] = *res;
782
783 res = platform_get_resource_byname(parent, IORESOURCE_IRQ, "mc");
784 if (!res) {
785 dev_err(dev, "failed to get irq.\n");
786 return -EINVAL;
787 }
788 resources[1] = *res;
789
790 /* allocate the child platform device */
791 musb = platform_device_alloc("musb-hdrc",
792 (resources[0].start & 0xFFF) == 0x400 ? 0 : 1);
793 if (!musb) {
794 dev_err(dev, "failed to allocate musb device\n");
795 return -ENOMEM;
796 }
797
798 musb->dev.parent = dev;
799 musb->dev.dma_mask = &musb_dmamask;
800 musb->dev.coherent_dma_mask = musb_dmamask;
801
802 glue->musb = musb;
803
804 ret = platform_device_add_resources(musb, resources,
805 ARRAY_SIZE(resources));
806 if (ret) {
807 dev_err(dev, "failed to add resources\n");
808 goto err;
809 }
810
811 config = devm_kzalloc(&parent->dev, sizeof(*config), GFP_KERNEL);
812 if (!config) {
813 ret = -ENOMEM;
814 goto err;
815 }
816 pdata.config = config;
817 pdata.platform_ops = &dsps_ops;
818
819 config->num_eps = get_int_prop(dn, "mentor,num-eps");
820 config->ram_bits = get_int_prop(dn, "mentor,ram-bits");
821 config->host_port_deassert_reset_at_resume = 1;
822 pdata.mode = get_musb_port_mode(dev);
823 /* DT keeps this entry in mA, musb expects it as per USB spec */
824 pdata.power = get_int_prop(dn, "mentor,power") / 2;
825
826 ret = of_property_read_u32(dn, "mentor,multipoint", &val);
827 if (!ret && val)
828 config->multipoint = true;
829
830 config->maximum_speed = usb_get_maximum_speed(&parent->dev);
831 switch (config->maximum_speed) {
832 case USB_SPEED_LOW:
833 case USB_SPEED_FULL:
834 break;
835 case USB_SPEED_SUPER:
836 dev_warn(dev, "ignore incorrect maximum_speed "
837 "(super-speed) setting in dts");
838 /* fall through */
839 default:
840 config->maximum_speed = USB_SPEED_HIGH;
841 }
842
843 ret = platform_device_add_data(musb, &pdata, sizeof(pdata));
844 if (ret) {
845 dev_err(dev, "failed to add platform_data\n");
846 goto err;
847 }
848
849 ret = platform_device_add(musb);
850 if (ret) {
851 dev_err(dev, "failed to register musb device\n");
852 goto err;
853 }
854 return 0;
855
856 err:
857 platform_device_put(musb);
858 return ret;
859 }
860
dsps_vbus_threaded_irq(int irq,void * priv)861 static irqreturn_t dsps_vbus_threaded_irq(int irq, void *priv)
862 {
863 struct dsps_glue *glue = priv;
864 struct musb *musb = platform_get_drvdata(glue->musb);
865
866 if (!musb)
867 return IRQ_NONE;
868
869 dev_dbg(glue->dev, "VBUS interrupt\n");
870 dsps_mod_timer(glue, 0);
871
872 return IRQ_HANDLED;
873 }
874
dsps_setup_optional_vbus_irq(struct platform_device * pdev,struct dsps_glue * glue)875 static int dsps_setup_optional_vbus_irq(struct platform_device *pdev,
876 struct dsps_glue *glue)
877 {
878 int error;
879
880 glue->vbus_irq = platform_get_irq_byname(pdev, "vbus");
881 if (glue->vbus_irq == -EPROBE_DEFER)
882 return -EPROBE_DEFER;
883
884 if (glue->vbus_irq <= 0) {
885 glue->vbus_irq = 0;
886 return 0;
887 }
888
889 error = devm_request_threaded_irq(glue->dev, glue->vbus_irq,
890 NULL, dsps_vbus_threaded_irq,
891 IRQF_ONESHOT,
892 "vbus", glue);
893 if (error) {
894 glue->vbus_irq = 0;
895 return error;
896 }
897 dev_dbg(glue->dev, "VBUS irq %i configured\n", glue->vbus_irq);
898
899 return 0;
900 }
901
dsps_probe(struct platform_device * pdev)902 static int dsps_probe(struct platform_device *pdev)
903 {
904 const struct of_device_id *match;
905 const struct dsps_musb_wrapper *wrp;
906 struct dsps_glue *glue;
907 int ret;
908
909 if (!strcmp(pdev->name, "musb-hdrc"))
910 return -ENODEV;
911
912 match = of_match_node(musb_dsps_of_match, pdev->dev.of_node);
913 if (!match) {
914 dev_err(&pdev->dev, "fail to get matching of_match struct\n");
915 return -EINVAL;
916 }
917 wrp = match->data;
918
919 if (of_device_is_compatible(pdev->dev.of_node, "ti,musb-dm816"))
920 dsps_ops.read_fifo = dsps_read_fifo32;
921
922 /* allocate glue */
923 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
924 if (!glue)
925 return -ENOMEM;
926
927 glue->dev = &pdev->dev;
928 glue->wrp = wrp;
929 glue->usbss_base = of_iomap(pdev->dev.parent->of_node, 0);
930 if (!glue->usbss_base)
931 return -ENXIO;
932
933 if (usb_get_dr_mode(&pdev->dev) == USB_DR_MODE_PERIPHERAL) {
934 ret = dsps_setup_optional_vbus_irq(pdev, glue);
935 if (ret)
936 goto err_iounmap;
937 }
938
939 platform_set_drvdata(pdev, glue);
940 pm_runtime_enable(&pdev->dev);
941 ret = dsps_create_musb_pdev(glue, pdev);
942 if (ret)
943 goto err;
944
945 return 0;
946
947 err:
948 pm_runtime_disable(&pdev->dev);
949 err_iounmap:
950 iounmap(glue->usbss_base);
951 return ret;
952 }
953
dsps_remove(struct platform_device * pdev)954 static int dsps_remove(struct platform_device *pdev)
955 {
956 struct dsps_glue *glue = platform_get_drvdata(pdev);
957
958 platform_device_unregister(glue->musb);
959
960 pm_runtime_disable(&pdev->dev);
961 iounmap(glue->usbss_base);
962
963 return 0;
964 }
965
966 static const struct dsps_musb_wrapper am33xx_driver_data = {
967 .revision = 0x00,
968 .control = 0x14,
969 .status = 0x18,
970 .epintr_set = 0x38,
971 .epintr_clear = 0x40,
972 .epintr_status = 0x30,
973 .coreintr_set = 0x3c,
974 .coreintr_clear = 0x44,
975 .coreintr_status = 0x34,
976 .phy_utmi = 0xe0,
977 .mode = 0xe8,
978 .tx_mode = 0x70,
979 .rx_mode = 0x74,
980 .reset = 0,
981 .otg_disable = 21,
982 .iddig = 8,
983 .iddig_mux = 7,
984 .usb_shift = 0,
985 .usb_mask = 0x1ff,
986 .usb_bitmap = (0x1ff << 0),
987 .drvvbus = 8,
988 .txep_shift = 0,
989 .txep_mask = 0xffff,
990 .txep_bitmap = (0xffff << 0),
991 .rxep_shift = 16,
992 .rxep_mask = 0xfffe,
993 .rxep_bitmap = (0xfffe << 16),
994 .poll_timeout = 2000, /* ms */
995 };
996
997 static const struct of_device_id musb_dsps_of_match[] = {
998 { .compatible = "ti,musb-am33xx",
999 .data = &am33xx_driver_data, },
1000 { .compatible = "ti,musb-dm816",
1001 .data = &am33xx_driver_data, },
1002 { },
1003 };
1004 MODULE_DEVICE_TABLE(of, musb_dsps_of_match);
1005
1006 #ifdef CONFIG_PM_SLEEP
dsps_suspend(struct device * dev)1007 static int dsps_suspend(struct device *dev)
1008 {
1009 struct dsps_glue *glue = dev_get_drvdata(dev);
1010 const struct dsps_musb_wrapper *wrp = glue->wrp;
1011 struct musb *musb = platform_get_drvdata(glue->musb);
1012 void __iomem *mbase;
1013 int ret;
1014
1015 if (!musb)
1016 /* This can happen if the musb device is in -EPROBE_DEFER */
1017 return 0;
1018
1019 ret = pm_runtime_get_sync(dev);
1020 if (ret < 0) {
1021 pm_runtime_put_noidle(dev);
1022 return ret;
1023 }
1024
1025 del_timer_sync(&glue->timer);
1026
1027 mbase = musb->ctrl_base;
1028 glue->context.control = musb_readl(mbase, wrp->control);
1029 glue->context.epintr = musb_readl(mbase, wrp->epintr_set);
1030 glue->context.coreintr = musb_readl(mbase, wrp->coreintr_set);
1031 glue->context.phy_utmi = musb_readl(mbase, wrp->phy_utmi);
1032 glue->context.mode = musb_readl(mbase, wrp->mode);
1033 glue->context.tx_mode = musb_readl(mbase, wrp->tx_mode);
1034 glue->context.rx_mode = musb_readl(mbase, wrp->rx_mode);
1035
1036 dsps_dma_controller_suspend(glue);
1037
1038 return 0;
1039 }
1040
dsps_resume(struct device * dev)1041 static int dsps_resume(struct device *dev)
1042 {
1043 struct dsps_glue *glue = dev_get_drvdata(dev);
1044 const struct dsps_musb_wrapper *wrp = glue->wrp;
1045 struct musb *musb = platform_get_drvdata(glue->musb);
1046 void __iomem *mbase;
1047
1048 if (!musb)
1049 return 0;
1050
1051 dsps_dma_controller_resume(glue);
1052
1053 mbase = musb->ctrl_base;
1054 musb_writel(mbase, wrp->control, glue->context.control);
1055 musb_writel(mbase, wrp->epintr_set, glue->context.epintr);
1056 musb_writel(mbase, wrp->coreintr_set, glue->context.coreintr);
1057 musb_writel(mbase, wrp->phy_utmi, glue->context.phy_utmi);
1058 musb_writel(mbase, wrp->mode, glue->context.mode);
1059 musb_writel(mbase, wrp->tx_mode, glue->context.tx_mode);
1060 musb_writel(mbase, wrp->rx_mode, glue->context.rx_mode);
1061 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE &&
1062 musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
1063 dsps_mod_timer(glue, -1);
1064
1065 pm_runtime_put(dev);
1066
1067 return 0;
1068 }
1069 #endif
1070
1071 static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume);
1072
1073 static struct platform_driver dsps_usbss_driver = {
1074 .probe = dsps_probe,
1075 .remove = dsps_remove,
1076 .driver = {
1077 .name = "musb-dsps",
1078 .pm = &dsps_pm_ops,
1079 .of_match_table = musb_dsps_of_match,
1080 },
1081 };
1082
1083 MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer");
1084 MODULE_AUTHOR("Ravi B <ravibabu@ti.com>");
1085 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
1086 MODULE_LICENSE("GPL v2");
1087
1088 module_platform_driver(dsps_usbss_driver);
1089