1 /*
2 * Generic EDAC defs
3 *
4 * Author: Dave Jiang <djiang@mvista.com>
5 *
6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 */
12 #ifndef _LINUX_EDAC_H_
13 #define _LINUX_EDAC_H_
14
15 #include <linux/atomic.h>
16 #include <linux/device.h>
17 #include <linux/completion.h>
18 #include <linux/workqueue.h>
19 #include <linux/debugfs.h>
20 #include <linux/numa.h>
21
22 #define EDAC_DEVICE_NAME_LEN 31
23
24 struct device;
25
26 #define EDAC_OPSTATE_INVAL -1
27 #define EDAC_OPSTATE_POLL 0
28 #define EDAC_OPSTATE_NMI 1
29 #define EDAC_OPSTATE_INT 2
30
31 extern int edac_op_state;
32
33 struct bus_type *edac_get_sysfs_subsys(void);
34 int edac_get_report_status(void);
35 void edac_set_report_status(int new);
36
37 enum {
38 EDAC_REPORTING_ENABLED,
39 EDAC_REPORTING_DISABLED,
40 EDAC_REPORTING_FORCE
41 };
42
opstate_init(void)43 static inline void opstate_init(void)
44 {
45 switch (edac_op_state) {
46 case EDAC_OPSTATE_POLL:
47 case EDAC_OPSTATE_NMI:
48 break;
49 default:
50 edac_op_state = EDAC_OPSTATE_POLL;
51 }
52 return;
53 }
54
55 /* Max length of a DIMM label*/
56 #define EDAC_MC_LABEL_LEN 31
57
58 /* Maximum size of the location string */
59 #define LOCATION_SIZE 256
60
61 /* Defines the maximum number of labels that can be reported */
62 #define EDAC_MAX_LABELS 8
63
64 /* String used to join two or more labels */
65 #define OTHER_LABEL " or "
66
67 /**
68 * enum dev_type - describe the type of memory DRAM chips used at the stick
69 * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it
70 * @DEV_X1: 1 bit for data
71 * @DEV_X2: 2 bits for data
72 * @DEV_X4: 4 bits for data
73 * @DEV_X8: 8 bits for data
74 * @DEV_X16: 16 bits for data
75 * @DEV_X32: 32 bits for data
76 * @DEV_X64: 64 bits for data
77 *
78 * Typical values are x4 and x8.
79 */
80 enum dev_type {
81 DEV_UNKNOWN = 0,
82 DEV_X1,
83 DEV_X2,
84 DEV_X4,
85 DEV_X8,
86 DEV_X16,
87 DEV_X32, /* Do these parts exist? */
88 DEV_X64 /* Do these parts exist? */
89 };
90
91 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
92 #define DEV_FLAG_X1 BIT(DEV_X1)
93 #define DEV_FLAG_X2 BIT(DEV_X2)
94 #define DEV_FLAG_X4 BIT(DEV_X4)
95 #define DEV_FLAG_X8 BIT(DEV_X8)
96 #define DEV_FLAG_X16 BIT(DEV_X16)
97 #define DEV_FLAG_X32 BIT(DEV_X32)
98 #define DEV_FLAG_X64 BIT(DEV_X64)
99
100 /**
101 * enum hw_event_mc_err_type - type of the detected error
102 *
103 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
104 * corrected error was detected
105 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
106 * can't be corrected by ECC, but it is not
107 * fatal (maybe it is on an unused memory area,
108 * or the memory controller could recover from
109 * it for example, by re-trying the operation).
110 * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable
111 * error whose handling is not urgent. This could
112 * be due to hardware data poisoning where the
113 * system can continue operation until the poisoned
114 * data is consumed. Preemptive measures may also
115 * be taken, e.g. offlining pages, etc.
116 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
117 * be recovered.
118 * @HW_EVENT_ERR_INFO: Informational - The CPER spec defines a forth
119 * type of error: informational logs.
120 */
121 enum hw_event_mc_err_type {
122 HW_EVENT_ERR_CORRECTED,
123 HW_EVENT_ERR_UNCORRECTED,
124 HW_EVENT_ERR_DEFERRED,
125 HW_EVENT_ERR_FATAL,
126 HW_EVENT_ERR_INFO,
127 };
128
mc_event_error_type(const unsigned int err_type)129 static inline char *mc_event_error_type(const unsigned int err_type)
130 {
131 switch (err_type) {
132 case HW_EVENT_ERR_CORRECTED:
133 return "Corrected";
134 case HW_EVENT_ERR_UNCORRECTED:
135 return "Uncorrected";
136 case HW_EVENT_ERR_DEFERRED:
137 return "Deferred";
138 case HW_EVENT_ERR_FATAL:
139 return "Fatal";
140 default:
141 case HW_EVENT_ERR_INFO:
142 return "Info";
143 }
144 }
145
146 /**
147 * enum mem_type - memory types. For a more detailed reference, please see
148 * http://en.wikipedia.org/wiki/DRAM
149 *
150 * @MEM_EMPTY: Empty csrow
151 * @MEM_RESERVED: Reserved csrow type
152 * @MEM_UNKNOWN: Unknown csrow type
153 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
154 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
155 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
156 * @MEM_SDR: SDR - Single data rate SDRAM
157 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
158 * They use 3 pins for chip select: Pins 0 and 2 are
159 * for rank 0; pins 1 and 3 are for rank 1, if the memory
160 * is dual-rank.
161 * @MEM_RDR: Registered SDR SDRAM
162 * @MEM_DDR: Double data rate SDRAM
163 * http://en.wikipedia.org/wiki/DDR_SDRAM
164 * @MEM_RDDR: Registered Double data rate SDRAM
165 * This is a variant of the DDR memories.
166 * A registered memory has a buffer inside it, hiding
167 * part of the memory details to the memory controller.
168 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
169 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
170 * Those memories are labeled as "PC2-" instead of "PC" to
171 * differentiate from DDR.
172 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
173 * and JESD206.
174 * Those memories are accessed per DIMM slot, and not by
175 * a chip select signal.
176 * @MEM_RDDR2: Registered DDR2 RAM
177 * This is a variant of the DDR2 memories.
178 * @MEM_XDR: Rambus XDR
179 * It is an evolution of the original RAMBUS memories,
180 * created to compete with DDR2. Weren't used on any
181 * x86 arch, but cell_edac PPC memory controller uses it.
182 * @MEM_DDR3: DDR3 RAM
183 * @MEM_RDDR3: Registered DDR3 RAM
184 * This is a variant of the DDR3 memories.
185 * @MEM_LRDDR3: Load-Reduced DDR3 memory.
186 * @MEM_DDR4: Unbuffered DDR4 RAM
187 * @MEM_RDDR4: Registered DDR4 RAM
188 * This is a variant of the DDR4 memories.
189 * @MEM_LRDDR4: Load-Reduced DDR4 memory.
190 */
191 enum mem_type {
192 MEM_EMPTY = 0,
193 MEM_RESERVED,
194 MEM_UNKNOWN,
195 MEM_FPM,
196 MEM_EDO,
197 MEM_BEDO,
198 MEM_SDR,
199 MEM_RDR,
200 MEM_DDR,
201 MEM_RDDR,
202 MEM_RMBS,
203 MEM_DDR2,
204 MEM_FB_DDR2,
205 MEM_RDDR2,
206 MEM_XDR,
207 MEM_DDR3,
208 MEM_RDDR3,
209 MEM_LRDDR3,
210 MEM_DDR4,
211 MEM_RDDR4,
212 MEM_LRDDR4,
213 };
214
215 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
216 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
217 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
218 #define MEM_FLAG_FPM BIT(MEM_FPM)
219 #define MEM_FLAG_EDO BIT(MEM_EDO)
220 #define MEM_FLAG_BEDO BIT(MEM_BEDO)
221 #define MEM_FLAG_SDR BIT(MEM_SDR)
222 #define MEM_FLAG_RDR BIT(MEM_RDR)
223 #define MEM_FLAG_DDR BIT(MEM_DDR)
224 #define MEM_FLAG_RDDR BIT(MEM_RDDR)
225 #define MEM_FLAG_RMBS BIT(MEM_RMBS)
226 #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
227 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
228 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
229 #define MEM_FLAG_XDR BIT(MEM_XDR)
230 #define MEM_FLAG_DDR3 BIT(MEM_DDR3)
231 #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
232 #define MEM_FLAG_DDR4 BIT(MEM_DDR4)
233 #define MEM_FLAG_RDDR4 BIT(MEM_RDDR4)
234 #define MEM_FLAG_LRDDR4 BIT(MEM_LRDDR4)
235
236 /**
237 * enum edac-type - Error Detection and Correction capabilities and mode
238 * @EDAC_UNKNOWN: Unknown if ECC is available
239 * @EDAC_NONE: Doesn't support ECC
240 * @EDAC_RESERVED: Reserved ECC type
241 * @EDAC_PARITY: Detects parity errors
242 * @EDAC_EC: Error Checking - no correction
243 * @EDAC_SECDED: Single bit error correction, Double detection
244 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
245 * @EDAC_S4ECD4ED: Chipkill x4 devices
246 * @EDAC_S8ECD8ED: Chipkill x8 devices
247 * @EDAC_S16ECD16ED: Chipkill x16 devices
248 */
249 enum edac_type {
250 EDAC_UNKNOWN = 0,
251 EDAC_NONE,
252 EDAC_RESERVED,
253 EDAC_PARITY,
254 EDAC_EC,
255 EDAC_SECDED,
256 EDAC_S2ECD2ED,
257 EDAC_S4ECD4ED,
258 EDAC_S8ECD8ED,
259 EDAC_S16ECD16ED,
260 };
261
262 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
263 #define EDAC_FLAG_NONE BIT(EDAC_NONE)
264 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
265 #define EDAC_FLAG_EC BIT(EDAC_EC)
266 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
267 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
268 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
269 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
270 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
271
272 /**
273 * enum scrub_type - scrubbing capabilities
274 * @SCRUB_UNKNOWN: Unknown if scrubber is available
275 * @SCRUB_NONE: No scrubber
276 * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing
277 * @SCRUB_SW_SRC: Software scrub only errors
278 * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error
279 * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable
280 * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing
281 * @SCRUB_HW_SRC: Hardware scrub only errors
282 * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error
283 * @SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
284 */
285 enum scrub_type {
286 SCRUB_UNKNOWN = 0,
287 SCRUB_NONE,
288 SCRUB_SW_PROG,
289 SCRUB_SW_SRC,
290 SCRUB_SW_PROG_SRC,
291 SCRUB_SW_TUNABLE,
292 SCRUB_HW_PROG,
293 SCRUB_HW_SRC,
294 SCRUB_HW_PROG_SRC,
295 SCRUB_HW_TUNABLE
296 };
297
298 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
299 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
300 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
301 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
302 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
303 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
304 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
305 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
306
307 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
308
309 /* EDAC internal operation states */
310 #define OP_ALLOC 0x100
311 #define OP_RUNNING_POLL 0x201
312 #define OP_RUNNING_INTERRUPT 0x202
313 #define OP_RUNNING_POLL_INTR 0x203
314 #define OP_OFFLINE 0x300
315
316 /**
317 * enum edac_mc_layer - memory controller hierarchy layer
318 *
319 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
320 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
321 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
322 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
323 * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped
324 * as a single memory area. This is used when
325 * retrieving errors from a firmware driven driver.
326 *
327 * This enum is used by the drivers to tell edac_mc_sysfs what name should
328 * be used when describing a memory stick location.
329 */
330 enum edac_mc_layer_type {
331 EDAC_MC_LAYER_BRANCH,
332 EDAC_MC_LAYER_CHANNEL,
333 EDAC_MC_LAYER_SLOT,
334 EDAC_MC_LAYER_CHIP_SELECT,
335 EDAC_MC_LAYER_ALL_MEM,
336 };
337
338 /**
339 * struct edac_mc_layer - describes the memory controller hierarchy
340 * @type: layer type
341 * @size: number of components per layer. For example,
342 * if the channel layer has two channels, size = 2
343 * @is_virt_csrow: This layer is part of the "csrow" when old API
344 * compatibility mode is enabled. Otherwise, it is
345 * a channel
346 */
347 struct edac_mc_layer {
348 enum edac_mc_layer_type type;
349 unsigned size;
350 bool is_virt_csrow;
351 };
352
353 /*
354 * Maximum number of layers used by the memory controller to uniquely
355 * identify a single memory stick.
356 * NOTE: Changing this constant requires not only to change the constant
357 * below, but also to change the existing code at the core, as there are
358 * some code there that are optimized for 3 layers.
359 */
360 #define EDAC_MAX_LAYERS 3
361
362 /**
363 * EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer
364 * array for the element given by [layer0,layer1,layer2]
365 * position
366 *
367 * @layers: a struct edac_mc_layer array, describing how many elements
368 * were allocated for each layer
369 * @nlayers: Number of layers at the @layers array
370 * @layer0: layer0 position
371 * @layer1: layer1 position. Unused if n_layers < 2
372 * @layer2: layer2 position. Unused if n_layers < 3
373 *
374 * For 1 layer, this macro returns "var[layer0] - var";
375 *
376 * For 2 layers, this macro is similar to allocate a bi-dimensional array
377 * and to return "var[layer0][layer1] - var";
378 *
379 * For 3 layers, this macro is similar to allocate a tri-dimensional array
380 * and to return "var[layer0][layer1][layer2] - var".
381 *
382 * A loop could be used here to make it more generic, but, as we only have
383 * 3 layers, this is a little faster.
384 *
385 * By design, layers can never be 0 or more than 3. If that ever happens,
386 * a NULL is returned, causing an OOPS during the memory allocation routine,
387 * with would point to the developer that he's doing something wrong.
388 */
389 #define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \
390 int __i; \
391 if ((nlayers) == 1) \
392 __i = layer0; \
393 else if ((nlayers) == 2) \
394 __i = (layer1) + ((layers[1]).size * (layer0)); \
395 else if ((nlayers) == 3) \
396 __i = (layer2) + ((layers[2]).size * ((layer1) + \
397 ((layers[1]).size * (layer0)))); \
398 else \
399 __i = -EINVAL; \
400 __i; \
401 })
402
403 /**
404 * EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array
405 * for the element given by [layer0,layer1,layer2] position
406 *
407 * @layers: a struct edac_mc_layer array, describing how many elements
408 * were allocated for each layer
409 * @var: name of the var where we want to get the pointer
410 * (like mci->dimms)
411 * @nlayers: Number of layers at the @layers array
412 * @layer0: layer0 position
413 * @layer1: layer1 position. Unused if n_layers < 2
414 * @layer2: layer2 position. Unused if n_layers < 3
415 *
416 * For 1 layer, this macro returns "var[layer0]";
417 *
418 * For 2 layers, this macro is similar to allocate a bi-dimensional array
419 * and to return "var[layer0][layer1]";
420 *
421 * For 3 layers, this macro is similar to allocate a tri-dimensional array
422 * and to return "var[layer0][layer1][layer2]";
423 */
424 #define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \
425 typeof(*var) __p; \
426 int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \
427 if (___i < 0) \
428 __p = NULL; \
429 else \
430 __p = (var)[___i]; \
431 __p; \
432 })
433
434 struct dimm_info {
435 struct device dev;
436
437 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
438
439 /* Memory location data */
440 unsigned location[EDAC_MAX_LAYERS];
441
442 struct mem_ctl_info *mci; /* the parent */
443
444 u32 grain; /* granularity of reported error in bytes */
445 enum dev_type dtype; /* memory device type */
446 enum mem_type mtype; /* memory dimm type */
447 enum edac_type edac_mode; /* EDAC mode for this dimm */
448
449 u32 nr_pages; /* number of pages on this dimm */
450
451 unsigned csrow, cschannel; /* Points to the old API data */
452 };
453
454 /**
455 * struct rank_info - contains the information for one DIMM rank
456 *
457 * @chan_idx: channel number where the rank is (typically, 0 or 1)
458 * @ce_count: number of correctable errors for this rank
459 * @csrow: A pointer to the chip select row structure (the parent
460 * structure). The location of the rank is given by
461 * the (csrow->csrow_idx, chan_idx) vector.
462 * @dimm: A pointer to the DIMM structure, where the DIMM label
463 * information is stored.
464 *
465 * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
466 * This is a bad assumption, but it makes this patch easier. Later
467 * patches in this series will fix this issue.
468 */
469 struct rank_info {
470 int chan_idx;
471 struct csrow_info *csrow;
472 struct dimm_info *dimm;
473
474 u32 ce_count; /* Correctable Errors for this csrow */
475 };
476
477 struct csrow_info {
478 struct device dev;
479
480 /* Used only by edac_mc_find_csrow_by_page() */
481 unsigned long first_page; /* first page number in csrow */
482 unsigned long last_page; /* last page number in csrow */
483 unsigned long page_mask; /* used for interleaving -
484 * 0UL for non intlv */
485
486 int csrow_idx; /* the chip-select row */
487
488 u32 ue_count; /* Uncorrectable Errors for this csrow */
489 u32 ce_count; /* Correctable Errors for this csrow */
490
491 struct mem_ctl_info *mci; /* the parent */
492
493 /* channel information for this csrow */
494 u32 nr_channels;
495 struct rank_info **channels;
496 };
497
498 /*
499 * struct errcount_attribute - used to store the several error counts
500 */
501 struct errcount_attribute_data {
502 int n_layers;
503 int pos[EDAC_MAX_LAYERS];
504 int layer0, layer1, layer2;
505 };
506
507 /**
508 * struct edac_raw_error_desc - Raw error report structure
509 * @grain: minimum granularity for an error report, in bytes
510 * @error_count: number of errors of the same type
511 * @top_layer: top layer of the error (layer[0])
512 * @mid_layer: middle layer of the error (layer[1])
513 * @low_layer: low layer of the error (layer[2])
514 * @page_frame_number: page where the error happened
515 * @offset_in_page: page offset
516 * @syndrome: syndrome of the error (or 0 if unknown or if
517 * the syndrome is not applicable)
518 * @msg: error message
519 * @location: location of the error
520 * @label: label of the affected DIMM(s)
521 * @other_detail: other driver-specific detail about the error
522 * @enable_per_layer_report: if false, the error affects all layers
523 * (typically, a memory controller error)
524 */
525 struct edac_raw_error_desc {
526 /*
527 * NOTE: everything before grain won't be cleaned by
528 * edac_raw_error_desc_clean()
529 */
530 char location[LOCATION_SIZE];
531 char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
532 long grain;
533
534 /* the vars below and grain will be cleaned on every new error report */
535 u16 error_count;
536 int top_layer;
537 int mid_layer;
538 int low_layer;
539 unsigned long page_frame_number;
540 unsigned long offset_in_page;
541 unsigned long syndrome;
542 const char *msg;
543 const char *other_detail;
544 bool enable_per_layer_report;
545 };
546
547 /* MEMORY controller information structure
548 */
549 struct mem_ctl_info {
550 struct device dev;
551 struct bus_type *bus;
552
553 struct list_head link; /* for global list of mem_ctl_info structs */
554
555 struct module *owner; /* Module owner of this control struct */
556
557 unsigned long mtype_cap; /* memory types supported by mc */
558 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
559 unsigned long edac_cap; /* configuration capabilities - this is
560 * closely related to edac_ctl_cap. The
561 * difference is that the controller may be
562 * capable of s4ecd4ed which would be listed
563 * in edac_ctl_cap, but if channels aren't
564 * capable of s4ecd4ed then the edac_cap would
565 * not have that capability.
566 */
567 unsigned long scrub_cap; /* chipset scrub capabilities */
568 enum scrub_type scrub_mode; /* current scrub mode */
569
570 /* Translates sdram memory scrub rate given in bytes/sec to the
571 internal representation and configures whatever else needs
572 to be configured.
573 */
574 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
575
576 /* Get the current sdram memory scrub rate from the internal
577 representation and converts it to the closest matching
578 bandwidth in bytes/sec.
579 */
580 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
581
582
583 /* pointer to edac checking routine */
584 void (*edac_check) (struct mem_ctl_info * mci);
585
586 /*
587 * Remaps memory pages: controller pages to physical pages.
588 * For most MC's, this will be NULL.
589 */
590 /* FIXME - why not send the phys page to begin with? */
591 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
592 unsigned long page);
593 int mc_idx;
594 struct csrow_info **csrows;
595 unsigned nr_csrows, num_cschannel;
596
597 /*
598 * Memory Controller hierarchy
599 *
600 * There are basically two types of memory controller: the ones that
601 * sees memory sticks ("dimms"), and the ones that sees memory ranks.
602 * All old memory controllers enumerate memories per rank, but most
603 * of the recent drivers enumerate memories per DIMM, instead.
604 * When the memory controller is per rank, csbased is true.
605 */
606 unsigned n_layers;
607 struct edac_mc_layer *layers;
608 bool csbased;
609
610 /*
611 * DIMM info. Will eventually remove the entire csrows_info some day
612 */
613 unsigned tot_dimms;
614 struct dimm_info **dimms;
615
616 /*
617 * FIXME - what about controllers on other busses? - IDs must be
618 * unique. dev pointer should be sufficiently unique, but
619 * BUS:SLOT.FUNC numbers may not be unique.
620 */
621 struct device *pdev;
622 const char *mod_name;
623 const char *ctl_name;
624 const char *dev_name;
625 void *pvt_info;
626 unsigned long start_time; /* mci load start time (in jiffies) */
627
628 /*
629 * drivers shouldn't access those fields directly, as the core
630 * already handles that.
631 */
632 u32 ce_noinfo_count, ue_noinfo_count;
633 u32 ue_mc, ce_mc;
634 u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
635
636 struct completion complete;
637
638 /* Additional top controller level attributes, but specified
639 * by the low level driver.
640 *
641 * Set by the low level driver to provide attributes at the
642 * controller level.
643 * An array of structures, NULL terminated
644 *
645 * If attributes are desired, then set to array of attributes
646 * If no attributes are desired, leave NULL
647 */
648 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
649
650 /* work struct for this MC */
651 struct delayed_work work;
652
653 /*
654 * Used to report an error - by being at the global struct
655 * makes the memory allocated by the EDAC core
656 */
657 struct edac_raw_error_desc error_desc;
658
659 /* the internal state of this controller instance */
660 int op_state;
661
662 struct dentry *debugfs;
663 u8 fake_inject_layer[EDAC_MAX_LAYERS];
664 bool fake_inject_ue;
665 u16 fake_inject_count;
666 };
667
668 /*
669 * Maximum number of memory controllers in the coherent fabric.
670 */
671 #define EDAC_MAX_MCS 2 * MAX_NUMNODES
672
673 #endif
674