1 /* 2 * board initialization should put one of these structures into platform_data 3 * and place the bfin-rotary onto platform_bus named "bfin-rotary". 4 * 5 * Copyright 2008-2010 Analog Devices Inc. 6 * 7 * Licensed under the GPL-2 or later. 8 */ 9 10 #ifndef _BFIN_ROTARY_H 11 #define _BFIN_ROTARY_H 12 13 /* mode bitmasks */ 14 #define ROT_QUAD_ENC CNTMODE_QUADENC /* quadrature/grey code encoder mode */ 15 #define ROT_BIN_ENC CNTMODE_BINENC /* binary encoder mode */ 16 #define ROT_UD_CNT CNTMODE_UDCNT /* rotary counter mode */ 17 #define ROT_DIR_CNT CNTMODE_DIRCNT /* direction counter mode */ 18 19 #define ROT_DEBE DEBE /* Debounce Enable */ 20 21 #define ROT_CDGINV CDGINV /* CDG Pin Polarity Invert */ 22 #define ROT_CUDINV CUDINV /* CUD Pin Polarity Invert */ 23 #define ROT_CZMINV CZMINV /* CZM Pin Polarity Invert */ 24 25 struct bfin_rotary_platform_data { 26 /* set rotary UP KEY_### or BTN_### in case you prefer 27 * bfin-rotary to send EV_KEY otherwise set 0 28 */ 29 unsigned int rotary_up_key; 30 /* set rotary DOWN KEY_### or BTN_### in case you prefer 31 * bfin-rotary to send EV_KEY otherwise set 0 32 */ 33 unsigned int rotary_down_key; 34 /* set rotary BUTTON KEY_### or BTN_### */ 35 unsigned int rotary_button_key; 36 /* set rotary Relative Axis REL_### in case you prefer 37 * bfin-rotary to send EV_REL otherwise set 0 38 */ 39 unsigned int rotary_rel_code; 40 unsigned short debounce; /* 0..17 */ 41 unsigned short mode; 42 unsigned short pm_wakeup; 43 unsigned short *pin_list; 44 }; 45 46 /* CNT_CONFIG bitmasks */ 47 #define CNTE (1 << 0) /* Counter Enable */ 48 #define DEBE (1 << 1) /* Debounce Enable */ 49 #define CDGINV (1 << 4) /* CDG Pin Polarity Invert */ 50 #define CUDINV (1 << 5) /* CUD Pin Polarity Invert */ 51 #define CZMINV (1 << 6) /* CZM Pin Polarity Invert */ 52 #define CNTMODE_SHIFT 8 53 #define CNTMODE (0x7 << CNTMODE_SHIFT) /* Counter Operating Mode */ 54 #define ZMZC (1 << 1) /* CZM Zeroes Counter Enable */ 55 #define BNDMODE_SHIFT 12 56 #define BNDMODE (0x3 << BNDMODE_SHIFT) /* Boundary register Mode */ 57 #define INPDIS (1 << 15) /* CUG and CDG Input Disable */ 58 59 #define CNTMODE_QUADENC (0 << CNTMODE_SHIFT) /* quadrature encoder mode */ 60 #define CNTMODE_BINENC (1 << CNTMODE_SHIFT) /* binary encoder mode */ 61 #define CNTMODE_UDCNT (2 << CNTMODE_SHIFT) /* up/down counter mode */ 62 #define CNTMODE_DIRCNT (4 << CNTMODE_SHIFT) /* direction counter mode */ 63 #define CNTMODE_DIRTMR (5 << CNTMODE_SHIFT) /* direction timer mode */ 64 65 #define BNDMODE_COMP (0 << BNDMODE_SHIFT) /* boundary compare mode */ 66 #define BNDMODE_ZERO (1 << BNDMODE_SHIFT) /* boundary compare and zero mode */ 67 #define BNDMODE_CAPT (2 << BNDMODE_SHIFT) /* boundary capture mode */ 68 #define BNDMODE_AEXT (3 << BNDMODE_SHIFT) /* boundary auto-extend mode */ 69 70 /* CNT_IMASK bitmasks */ 71 #define ICIE (1 << 0) /* Illegal Gray/Binary Code Interrupt Enable */ 72 #define UCIE (1 << 1) /* Up count Interrupt Enable */ 73 #define DCIE (1 << 2) /* Down count Interrupt Enable */ 74 #define MINCIE (1 << 3) /* Min Count Interrupt Enable */ 75 #define MAXCIE (1 << 4) /* Max Count Interrupt Enable */ 76 #define COV31IE (1 << 5) /* Bit 31 Overflow Interrupt Enable */ 77 #define COV15IE (1 << 6) /* Bit 15 Overflow Interrupt Enable */ 78 #define CZEROIE (1 << 7) /* Count to Zero Interrupt Enable */ 79 #define CZMIE (1 << 8) /* CZM Pin Interrupt Enable */ 80 #define CZMEIE (1 << 9) /* CZM Error Interrupt Enable */ 81 #define CZMZIE (1 << 10) /* CZM Zeroes Counter Interrupt Enable */ 82 83 /* CNT_STATUS bitmasks */ 84 #define ICII (1 << 0) /* Illegal Gray/Binary Code Interrupt Identifier */ 85 #define UCII (1 << 1) /* Up count Interrupt Identifier */ 86 #define DCII (1 << 2) /* Down count Interrupt Identifier */ 87 #define MINCII (1 << 3) /* Min Count Interrupt Identifier */ 88 #define MAXCII (1 << 4) /* Max Count Interrupt Identifier */ 89 #define COV31II (1 << 5) /* Bit 31 Overflow Interrupt Identifier */ 90 #define COV15II (1 << 6) /* Bit 15 Overflow Interrupt Identifier */ 91 #define CZEROII (1 << 7) /* Count to Zero Interrupt Identifier */ 92 #define CZMII (1 << 8) /* CZM Pin Interrupt Identifier */ 93 #define CZMEII (1 << 9) /* CZM Error Interrupt Identifier */ 94 #define CZMZII (1 << 10) /* CZM Zeroes Counter Interrupt Identifier */ 95 96 /* CNT_COMMAND bitmasks */ 97 #define W1LCNT 0xf /* Load Counter Register */ 98 #define W1LMIN 0xf0 /* Load Min Register */ 99 #define W1LMAX 0xf00 /* Load Max Register */ 100 #define W1ZMONCE (1 << 12) /* Enable CZM Clear Counter Once */ 101 102 #define W1LCNT_ZERO (1 << 0) /* write 1 to load CNT_COUNTER with zero */ 103 #define W1LCNT_MIN (1 << 2) /* write 1 to load CNT_COUNTER from CNT_MIN */ 104 #define W1LCNT_MAX (1 << 3) /* write 1 to load CNT_COUNTER from CNT_MAX */ 105 106 #define W1LMIN_ZERO (1 << 4) /* write 1 to load CNT_MIN with zero */ 107 #define W1LMIN_CNT (1 << 5) /* write 1 to load CNT_MIN from CNT_COUNTER */ 108 #define W1LMIN_MAX (1 << 7) /* write 1 to load CNT_MIN from CNT_MAX */ 109 110 #define W1LMAX_ZERO (1 << 8) /* write 1 to load CNT_MAX with zero */ 111 #define W1LMAX_CNT (1 << 9) /* write 1 to load CNT_MAX from CNT_COUNTER */ 112 #define W1LMAX_MIN (1 << 10) /* write 1 to load CNT_MAX from CNT_MIN */ 113 114 /* CNT_DEBOUNCE bitmasks */ 115 #define DPRESCALE 0xf /* Load Counter Register */ 116 117 #endif 118