1 /* 2 * USB 338x super/high/full speed USB device controller. 3 * Unlike many such controllers, this one talks PCI. 4 * 5 * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com) 6 * Copyright (C) 2003 David Brownell 7 * Copyright (C) 2014 Ricardo Ribalda - Qtechnology/AS 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 */ 20 21 #ifndef __LINUX_USB_USB338X_H 22 #define __LINUX_USB_USB338X_H 23 24 #include <linux/usb/net2280.h> 25 26 /* 27 * Extra defined bits for net2280 registers 28 */ 29 #define SCRATCH 0x0b 30 31 #define DEFECT7374_FSM_FIELD 28 32 #define SUPER_SPEED 8 33 #define DMA_REQUEST_OUTSTANDING 5 34 #define DMA_PAUSE_DONE_INTERRUPT 26 35 #define SET_ISOCHRONOUS_DELAY 24 36 #define SET_SEL 22 37 #define SUPER_SPEED_MODE 8 38 39 /*ep_cfg*/ 40 #define MAX_BURST_SIZE 24 41 #define EP_FIFO_BYTE_COUNT 16 42 #define IN_ENDPOINT_ENABLE 14 43 #define IN_ENDPOINT_TYPE 12 44 #define OUT_ENDPOINT_ENABLE 10 45 #define OUT_ENDPOINT_TYPE 8 46 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \ 47 BIT(IN_ENDPOINT_ENABLE)) 48 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \ 49 BIT(OUT_ENDPOINT_ENABLE)) 50 51 struct usb338x_usb_ext_regs { 52 u32 usbclass; 53 #define DEVICE_PROTOCOL 16 54 #define DEVICE_SUB_CLASS 8 55 #define DEVICE_CLASS 0 56 u32 ss_sel; 57 #define U2_SYSTEM_EXIT_LATENCY 8 58 #define U1_SYSTEM_EXIT_LATENCY 0 59 u32 ss_del; 60 #define U2_DEVICE_EXIT_LATENCY 8 61 #define U1_DEVICE_EXIT_LATENCY 0 62 u32 usb2lpm; 63 #define USB_L1_LPM_HIRD 2 64 #define USB_L1_LPM_REMOTE_WAKE 1 65 #define USB_L1_LPM_SUPPORT 0 66 u32 usb3belt; 67 #define BELT_MULTIPLIER 10 68 #define BEST_EFFORT_LATENCY_TOLERANCE 0 69 u32 usbctl2; 70 #define LTM_ENABLE 7 71 #define U2_ENABLE 6 72 #define U1_ENABLE 5 73 #define FUNCTION_SUSPEND 4 74 #define USB3_CORE_ENABLE 3 75 #define USB2_CORE_ENABLE 2 76 #define SERIAL_NUMBER_STRING_ENABLE 0 77 u32 in_timeout; 78 #define GPEP3_TIMEOUT 19 79 #define GPEP2_TIMEOUT 18 80 #define GPEP1_TIMEOUT 17 81 #define GPEP0_TIMEOUT 16 82 #define GPEP3_TIMEOUT_VALUE 13 83 #define GPEP3_TIMEOUT_ENABLE 12 84 #define GPEP2_TIMEOUT_VALUE 9 85 #define GPEP2_TIMEOUT_ENABLE 8 86 #define GPEP1_TIMEOUT_VALUE 5 87 #define GPEP1_TIMEOUT_ENABLE 4 88 #define GPEP0_TIMEOUT_VALUE 1 89 #define GPEP0_TIMEOUT_ENABLE 0 90 u32 isodelay; 91 #define ISOCHRONOUS_DELAY 0 92 } __packed; 93 94 struct usb338x_fifo_regs { 95 /* offset 0x0500, 0x0520, 0x0540, 0x0560, 0x0580 */ 96 u32 ep_fifo_size_base; 97 #define IN_FIFO_BASE_ADDRESS 22 98 #define IN_FIFO_SIZE 16 99 #define OUT_FIFO_BASE_ADDRESS 6 100 #define OUT_FIFO_SIZE 0 101 u32 ep_fifo_out_wrptr; 102 u32 ep_fifo_out_rdptr; 103 u32 ep_fifo_in_wrptr; 104 u32 ep_fifo_in_rdptr; 105 u32 unused[3]; 106 } __packed; 107 108 109 /* Link layer */ 110 struct usb338x_ll_regs { 111 /* offset 0x700 */ 112 u32 ll_ltssm_ctrl1; 113 u32 ll_ltssm_ctrl2; 114 u32 ll_ltssm_ctrl3; 115 u32 unused[2]; 116 u32 ll_general_ctrl0; 117 u32 ll_general_ctrl1; 118 #define PM_U3_AUTO_EXIT 29 119 #define PM_U2_AUTO_EXIT 28 120 #define PM_U1_AUTO_EXIT 27 121 #define PM_FORCE_U2_ENTRY 26 122 #define PM_FORCE_U1_ENTRY 25 123 #define PM_LGO_COLLISION_SEND_LAU 24 124 #define PM_DIR_LINK_REJECT 23 125 #define PM_FORCE_LINK_ACCEPT 22 126 #define PM_DIR_ENTRY_U3 20 127 #define PM_DIR_ENTRY_U2 19 128 #define PM_DIR_ENTRY_U1 18 129 #define PM_U2_ENABLE 17 130 #define PM_U1_ENABLE 16 131 #define SKP_THRESHOLD_ADJUST_FMW 8 132 #define RESEND_DPP_ON_LRTY_FMW 7 133 #define DL_BIT_VALUE_FMW 6 134 #define FORCE_DL_BIT 5 135 u32 ll_general_ctrl2; 136 #define SELECT_INVERT_LANE_POLARITY 7 137 #define FORCE_INVERT_LANE_POLARITY 6 138 u32 ll_general_ctrl3; 139 u32 ll_general_ctrl4; 140 u32 ll_error_gen; 141 } __packed; 142 143 struct usb338x_ll_lfps_regs { 144 /* offset 0x748 */ 145 u32 ll_lfps_5; 146 #define TIMER_LFPS_6US 16 147 u32 ll_lfps_6; 148 #define TIMER_LFPS_80US 0 149 } __packed; 150 151 struct usb338x_ll_tsn_regs { 152 /* offset 0x77C */ 153 u32 ll_tsn_counters_2; 154 #define HOT_TX_NORESET_TS2 24 155 u32 ll_tsn_counters_3; 156 #define HOT_RX_RESET_TS2 0 157 } __packed; 158 159 struct usb338x_ll_chi_regs { 160 /* offset 0x79C */ 161 u32 ll_tsn_chicken_bit; 162 #define RECOVERY_IDLE_TO_RECOVER_FMW 3 163 } __packed; 164 165 /* protocol layer */ 166 struct usb338x_pl_regs { 167 /* offset 0x800 */ 168 u32 pl_reg_1; 169 u32 pl_reg_2; 170 u32 pl_reg_3; 171 u32 pl_reg_4; 172 u32 pl_ep_ctrl; 173 /* Protocol Layer Endpoint Control*/ 174 #define PL_EP_CTRL 0x810 175 #define ENDPOINT_SELECT 0 176 /* [4:0] */ 177 #define EP_INITIALIZED 16 178 #define SEQUENCE_NUMBER_RESET 17 179 #define CLEAR_ACK_ERROR_CODE 20 180 u32 pl_reg_6; 181 u32 pl_reg_7; 182 u32 pl_reg_8; 183 u32 pl_ep_status_1; 184 /* Protocol Layer Endpoint Status 1*/ 185 #define PL_EP_STATUS_1 0x820 186 #define STATE 16 187 #define ACK_GOOD_NORMAL 0x11 188 #define ACK_GOOD_MORE_ACKS_TO_COME 0x16 189 u32 pl_ep_status_2; 190 u32 pl_ep_status_3; 191 /* Protocol Layer Endpoint Status 3*/ 192 #define PL_EP_STATUS_3 0x828 193 #define SEQUENCE_NUMBER 0 194 u32 pl_ep_status_4; 195 /* Protocol Layer Endpoint Status 4*/ 196 #define PL_EP_STATUS_4 0x82c 197 u32 pl_ep_cfg_4; 198 /* Protocol Layer Endpoint Configuration 4*/ 199 #define PL_EP_CFG_4 0x830 200 #define NON_CTRL_IN_TOLERATE_BAD_DIR 6 201 } __packed; 202 203 #endif /* __LINUX_USB_USB338X_H */ 204