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1/*
2 * Device Tree include file for SolidRun Clearfog 88F6828 based boards
3 *
4 *  Copyright (C) 2015 Russell King
5 *
6 * This board is in development; the contents of this file work with
7 * the A1 rev 2.0 of the board, which does not represent final
8 * production board.  Things will change, don't expect this file to
9 * remain compatible info the future.
10 *
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 *  a) This file is free software; you can redistribute it and/or
17 *     modify it under the terms of the GNU General Public License
18 *     version 2 as published by the Free Software Foundation.
19 *
20 *     This file is distributed in the hope that it will be useful
21 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
22 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23 *     GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 *  b) Permission is hereby granted, free of charge, to any person
28 *     obtaining a copy of this software and associated documentation
29 *     files (the "Software"), to deal in the Software without
30 *     restriction, including without limitation the rights to use
31 *     copy, modify, merge, publish, distribute, sublicense, and/or
32 *     sell copies of the Software, and to permit persons to whom the
33 *     Software is furnished to do so, subject to the following
34 *     conditions:
35 *
36 *     The above copyright notice and this permission notice shall be
37 *     included in all copies or substantial portions of the Software.
38 *
39 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 *     OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49#include "armada-388.dtsi"
50#include "armada-38x-solidrun-microsom.dtsi"
51
52/ {
53	aliases {
54		/* So that mvebu u-boot can update the MAC addresses */
55		ethernet1 = &eth0;
56		ethernet2 = &eth1;
57		ethernet3 = &eth2;
58	};
59
60	chosen {
61		stdout-path = "serial0:115200n8";
62	};
63
64	reg_3p3v: regulator-3p3v {
65		compatible = "regulator-fixed";
66		regulator-name = "3P3V";
67		regulator-min-microvolt = <3300000>;
68		regulator-max-microvolt = <3300000>;
69		regulator-always-on;
70	};
71
72	soc {
73		internal-regs {
74			sata@a8000 {
75				/* pinctrl? */
76				status = "okay";
77			};
78
79			sata@e0000 {
80				/* pinctrl? */
81				status = "okay";
82			};
83
84			sdhci@d8000 {
85				bus-width = <4>;
86				cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
87				no-1-8-v;
88				pinctrl-0 = <&microsom_sdhci_pins
89					     &clearfog_sdhci_cd_pins>;
90				pinctrl-names = "default";
91				status = "okay";
92				vmmc-supply = <&reg_3p3v>;
93				wp-inverted;
94			};
95
96			usb@58000 {
97				/* CON3, nearest  power. */
98				status = "okay";
99			};
100
101			usb3@f8000 {
102				/* CON7 */
103				status = "okay";
104			};
105		};
106
107		pcie {
108			status = "okay";
109			/*
110			 * The two PCIe units are accessible through
111			 * the mini-PCIe connectors on the board.
112			 */
113			pcie@2,0 {
114				/* Port 1, Lane 0. CON3, nearest power. */
115				reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
116				status = "okay";
117			};
118		};
119	};
120};
121
122&eth1 {
123	/* ethernet@30000 */
124	bm,pool-long = <2>;
125	bm,pool-short = <1>;
126	buffer-manager = <&bm>;
127	phy-mode = "sgmii";
128	status = "okay";
129};
130
131&eth2 {
132	/* ethernet@34000 */
133	bm,pool-long = <3>;
134	bm,pool-short = <1>;
135	buffer-manager = <&bm>;
136	phy-mode = "sgmii";
137	status = "okay";
138
139	fixed-link {
140		speed = <1000>;
141		full-duplex;
142	};
143};
144
145&i2c0 {
146	/* Is there anything on this? */
147	clock-frequency = <100000>;
148	pinctrl-0 = <&i2c0_pins>;
149	pinctrl-names = "default";
150	status = "okay";
151
152	/*
153	 * PCA9655 GPIO expander, up to 1MHz clock.
154	 *  0-CON3 CLKREQ#
155	 *  1-CON3 PERST#
156	 *  2-
157	 *  3-CON3 W_DISABLE
158	 *  4-
159	 *  5-USB3 overcurrent
160	 *  6-USB3 power
161	 *  7-
162	 *  8-JP4 P1
163	 *  9-JP4 P4
164	 * 10-JP4 P5
165	 * 11-m.2 DEVSLP
166	 * 12-SFP_LOS
167	 * 13-SFP_TX_FAULT
168	 * 14-SFP_TX_DISABLE
169	 * 15-SFP_MOD_DEF0
170	 */
171	expander0: gpio-expander@20 {
172		/*
173		 * This is how it should be:
174		 * compatible = "onnn,pca9655", "nxp,pca9555";
175		 * but you can't do this because of the way I2C works.
176		 */
177		compatible = "nxp,pca9555";
178		gpio-controller;
179		#gpio-cells = <2>;
180		reg = <0x20>;
181
182		pcie1_0_clkreq {
183			gpio-hog;
184			gpios = <0 GPIO_ACTIVE_LOW>;
185			input;
186			line-name = "pcie1.0-clkreq";
187		};
188		pcie1_0_w_disable {
189			gpio-hog;
190			gpios = <3 GPIO_ACTIVE_LOW>;
191			output-low;
192			line-name = "pcie1.0-w-disable";
193		};
194		usb3_ilimit {
195			gpio-hog;
196			gpios = <5 GPIO_ACTIVE_LOW>;
197			input;
198			line-name = "usb3-current-limit";
199		};
200		usb3_power {
201			gpio-hog;
202			gpios = <6 GPIO_ACTIVE_HIGH>;
203			output-high;
204			line-name = "usb3-power";
205		};
206		m2_devslp {
207			gpio-hog;
208			gpios = <11 GPIO_ACTIVE_HIGH>;
209			output-low;
210			line-name = "m.2 devslp";
211		};
212		sfp_los {
213			/* SFP loss of signal */
214			gpio-hog;
215			gpios = <12 GPIO_ACTIVE_HIGH>;
216			input;
217			line-name = "sfp-los";
218		};
219		sfp_tx_fault {
220			/* SFP laser fault */
221			gpio-hog;
222			gpios = <13 GPIO_ACTIVE_HIGH>;
223			input;
224			line-name = "sfp-tx-fault";
225		};
226		sfp_tx_disable {
227			/* SFP transmit disable */
228			gpio-hog;
229			gpios = <14 GPIO_ACTIVE_HIGH>;
230			output-low;
231			line-name = "sfp-tx-disable";
232		};
233		sfp_mod_def0 {
234			/* SFP module present */
235			gpio-hog;
236			gpios = <15 GPIO_ACTIVE_LOW>;
237			input;
238			line-name = "sfp-mod-def0";
239		};
240	};
241
242	/* The MCP3021 is 100kHz clock only */
243	mikrobus_adc: mcp3021@4c {
244		compatible = "microchip,mcp3021";
245		reg = <0x4c>;
246	};
247
248	/* Also something at 0x64 */
249};
250
251&i2c1 {
252	/*
253	 * Routed to SFP, mikrobus, and PCIe.
254	 * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with
255	 *  address pins tied low, which takes addresses 0x50 and 0x51.
256	 * Mikrobus doesn't specify beyond an I2C bus being present.
257	 * PCIe uses ARP to assign addresses, or 0x63-0x64.
258	 */
259	clock-frequency = <100000>;
260	pinctrl-0 = <&clearfog_i2c1_pins>;
261	pinctrl-names = "default";
262	status = "okay";
263};
264
265&pinctrl {
266	clearfog_i2c1_pins: i2c1-pins {
267		/* SFP, PCIe, mSATA, mikrobus */
268		marvell,pins = "mpp26", "mpp27";
269		marvell,function = "i2c1";
270	};
271	clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
272		marvell,pins = "mpp20";
273		marvell,function = "gpio";
274	};
275	mikro_pins: mikro-pins {
276		/* int: mpp22 rst: mpp29 */
277		marvell,pins = "mpp22", "mpp29";
278		marvell,function = "gpio";
279	};
280	mikro_spi_pins: mikro-spi-pins {
281		marvell,pins = "mpp43";
282		marvell,function = "spi1";
283	};
284	mikro_uart_pins: mikro-uart-pins {
285		marvell,pins = "mpp24", "mpp25";
286		marvell,function = "ua1";
287	};
288};
289
290&spi1 {
291	/*
292	 * Add SPI CS pins for clearfog:
293	 * CS0: W25Q32 (not populated on uSOM)
294	 * CS1: PIC microcontroller (Pro models)
295	 * CS2: mikrobus
296	 */
297	pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
298	pinctrl-names = "default";
299	status = "okay";
300};
301
302&uart1 {
303	/* mikrobus uart */
304	pinctrl-0 = <&mikro_uart_pins>;
305	pinctrl-names = "default";
306	status = "okay";
307};
308