1/* 2 * Device Tree Include file for Marvell Armada 38x family of SoCs. 3 * 4 * Copyright (C) 2014 Marvell 5 * 6 * Lior Amsalem <alior@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * 10 * This file is dual-licensed: you can use it either under the terms 11 * of the GPL or the X11 license, at your option. Note that this dual 12 * licensing only applies to this file, and not this project as a 13 * whole. 14 * 15 * a) This file is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of the 18 * License, or (at your option) any later version. 19 * 20 * This file is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * Or, alternatively, 26 * 27 * b) Permission is hereby granted, free of charge, to any person 28 * obtaining a copy of this software and associated documentation 29 * files (the "Software"), to deal in the Software without 30 * restriction, including without limitation the rights to use, 31 * copy, modify, merge, publish, distribute, sublicense, and/or 32 * sell copies of the Software, and to permit persons to whom the 33 * Software is furnished to do so, subject to the following 34 * conditions: 35 * 36 * The above copyright notice and this permission notice shall be 37 * included in all copies or substantial portions of the Software. 38 * 39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46 * OTHER DEALINGS IN THE SOFTWARE. 47 */ 48 49#include "skeleton.dtsi" 50#include <dt-bindings/interrupt-controller/arm-gic.h> 51#include <dt-bindings/interrupt-controller/irq.h> 52 53#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 54 55/ { 56 model = "Marvell Armada 38x family SoC"; 57 compatible = "marvell,armada380"; 58 59 aliases { 60 gpio0 = &gpio0; 61 gpio1 = &gpio1; 62 serial0 = &uart0; 63 serial1 = &uart1; 64 }; 65 66 pmu { 67 compatible = "arm,cortex-a9-pmu"; 68 interrupts-extended = <&mpic 3>; 69 }; 70 71 soc { 72 compatible = "marvell,armada380-mbus", "simple-bus"; 73 #address-cells = <2>; 74 #size-cells = <1>; 75 controller = <&mbusc>; 76 interrupt-parent = <&gic>; 77 pcie-mem-aperture = <0xe0000000 0x8000000>; 78 pcie-io-aperture = <0xe8000000 0x100000>; 79 80 bootrom { 81 compatible = "marvell,bootrom"; 82 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 83 }; 84 85 devbus_bootcs: devbus-bootcs { 86 compatible = "marvell,mvebu-devbus"; 87 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; 88 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 clocks = <&coreclk 0>; 92 status = "disabled"; 93 }; 94 95 devbus_cs0: devbus-cs0 { 96 compatible = "marvell,mvebu-devbus"; 97 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; 98 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 clocks = <&coreclk 0>; 102 status = "disabled"; 103 }; 104 105 devbus_cs1: devbus-cs1 { 106 compatible = "marvell,mvebu-devbus"; 107 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; 108 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 clocks = <&coreclk 0>; 112 status = "disabled"; 113 }; 114 115 devbus_cs2: devbus-cs2 { 116 compatible = "marvell,mvebu-devbus"; 117 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; 118 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; 119 #address-cells = <1>; 120 #size-cells = <1>; 121 clocks = <&coreclk 0>; 122 status = "disabled"; 123 }; 124 125 devbus_cs3: devbus-cs3 { 126 compatible = "marvell,mvebu-devbus"; 127 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; 128 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 clocks = <&coreclk 0>; 132 status = "disabled"; 133 }; 134 135 internal-regs { 136 compatible = "simple-bus"; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 140 141 L2: cache-controller@8000 { 142 compatible = "arm,pl310-cache"; 143 reg = <0x8000 0x1000>; 144 cache-unified; 145 cache-level = <2>; 146 arm,double-linefill-incr = <0>; 147 arm,double-linefill-wrap = <0>; 148 arm,double-linefill = <0>; 149 prefetch-data = <1>; 150 }; 151 152 scu@c000 { 153 compatible = "arm,cortex-a9-scu"; 154 reg = <0xc000 0x58>; 155 }; 156 157 timer@c200 { 158 compatible = "arm,cortex-a9-global-timer"; 159 reg = <0xc200 0x20>; 160 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 161 clocks = <&coreclk 2>; 162 }; 163 164 timer@c600 { 165 compatible = "arm,cortex-a9-twd-timer"; 166 reg = <0xc600 0x20>; 167 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 168 clocks = <&coreclk 2>; 169 }; 170 171 gic: interrupt-controller@d000 { 172 compatible = "arm,cortex-a9-gic"; 173 #interrupt-cells = <3>; 174 #size-cells = <0>; 175 interrupt-controller; 176 reg = <0xd000 0x1000>, 177 <0xc100 0x100>; 178 }; 179 180 i2c0: i2c@11000 { 181 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; 182 reg = <0x11000 0x20>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 186 timeout-ms = <1000>; 187 clocks = <&coreclk 0>; 188 status = "disabled"; 189 }; 190 191 i2c1: i2c@11100 { 192 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; 193 reg = <0x11100 0x20>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 197 timeout-ms = <1000>; 198 clocks = <&coreclk 0>; 199 status = "disabled"; 200 }; 201 202 uart0: serial@12000 { 203 compatible = "snps,dw-apb-uart"; 204 reg = <0x12000 0x100>; 205 reg-shift = <2>; 206 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 207 reg-io-width = <1>; 208 clocks = <&coreclk 0>; 209 status = "disabled"; 210 }; 211 212 uart1: serial@12100 { 213 compatible = "snps,dw-apb-uart"; 214 reg = <0x12100 0x100>; 215 reg-shift = <2>; 216 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 217 reg-io-width = <1>; 218 clocks = <&coreclk 0>; 219 status = "disabled"; 220 }; 221 222 pinctrl: pinctrl@18000 { 223 reg = <0x18000 0x20>; 224 225 ge0_rgmii_pins: ge-rgmii-pins-0 { 226 marvell,pins = "mpp6", "mpp7", "mpp8", 227 "mpp9", "mpp10", "mpp11", 228 "mpp12", "mpp13", "mpp14", 229 "mpp15", "mpp16", "mpp17"; 230 marvell,function = "ge0"; 231 }; 232 233 ge1_rgmii_pins: ge-rgmii-pins-1 { 234 marvell,pins = "mpp21", "mpp27", "mpp28", 235 "mpp29", "mpp30", "mpp31", 236 "mpp32", "mpp37", "mpp38", 237 "mpp39", "mpp40", "mpp41"; 238 marvell,function = "ge1"; 239 }; 240 241 i2c0_pins: i2c-pins-0 { 242 marvell,pins = "mpp2", "mpp3"; 243 marvell,function = "i2c0"; 244 }; 245 246 mdio_pins: mdio-pins { 247 marvell,pins = "mpp4", "mpp5"; 248 marvell,function = "ge"; 249 }; 250 251 ref_clk0_pins: ref-clk-pins-0 { 252 marvell,pins = "mpp45"; 253 marvell,function = "ref"; 254 }; 255 256 ref_clk1_pins: ref-clk-pins-1 { 257 marvell,pins = "mpp46"; 258 marvell,function = "ref"; 259 }; 260 261 spi0_pins: spi-pins-0 { 262 marvell,pins = "mpp22", "mpp23", "mpp24", 263 "mpp25"; 264 marvell,function = "spi0"; 265 }; 266 267 spi1_pins: spi-pins-1 { 268 marvell,pins = "mpp56", "mpp57", "mpp58", 269 "mpp59"; 270 marvell,function = "spi1"; 271 }; 272 273 nand_pins: nand-pins { 274 marvell,pins = "mpp22", "mpp34", "mpp23", 275 "mpp33", "mpp38", "mpp28", 276 "mpp40", "mpp42", "mpp35", 277 "mpp36", "mpp25", "mpp30", 278 "mpp32"; 279 marvell,function = "dev"; 280 }; 281 282 uart0_pins: uart-pins-0 { 283 marvell,pins = "mpp0", "mpp1"; 284 marvell,function = "ua0"; 285 }; 286 287 uart1_pins: uart-pins-1 { 288 marvell,pins = "mpp19", "mpp20"; 289 marvell,function = "ua1"; 290 }; 291 292 sdhci_pins: sdhci-pins { 293 marvell,pins = "mpp48", "mpp49", "mpp50", 294 "mpp52", "mpp53", "mpp54", 295 "mpp55", "mpp57", "mpp58", 296 "mpp59"; 297 marvell,function = "sd0"; 298 }; 299 300 sata0_pins: sata-pins-0 { 301 marvell,pins = "mpp20"; 302 marvell,function = "sata0"; 303 }; 304 305 sata1_pins: sata-pins-1 { 306 marvell,pins = "mpp19"; 307 marvell,function = "sata1"; 308 }; 309 310 sata2_pins: sata-pins-2 { 311 marvell,pins = "mpp47"; 312 marvell,function = "sata2"; 313 }; 314 315 sata3_pins: sata-pins-3 { 316 marvell,pins = "mpp44"; 317 marvell,function = "sata3"; 318 }; 319 }; 320 321 gpio0: gpio@18100 { 322 compatible = "marvell,armada-370-gpio", 323 "marvell,orion-gpio"; 324 reg = <0x18100 0x40>, <0x181c0 0x08>; 325 reg-names = "gpio", "pwm"; 326 ngpios = <32>; 327 gpio-controller; 328 #gpio-cells = <2>; 329 #pwm-cells = <2>; 330 interrupt-controller; 331 #interrupt-cells = <2>; 332 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&coreclk 0>; 337 }; 338 339 gpio1: gpio@18140 { 340 compatible = "marvell,armada-370-gpio", 341 "marvell,orion-gpio"; 342 reg = <0x18140 0x40>, <0x181c8 0x08>; 343 reg-names = "gpio", "pwm"; 344 ngpios = <28>; 345 gpio-controller; 346 #gpio-cells = <2>; 347 #pwm-cells = <2>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&coreclk 0>; 355 }; 356 357 systemc: system-controller@18200 { 358 compatible = "marvell,armada-380-system-controller", 359 "marvell,armada-370-xp-system-controller"; 360 reg = <0x18200 0x100>; 361 }; 362 363 gateclk: clock-gating-control@18220 { 364 compatible = "marvell,armada-380-gating-clock"; 365 reg = <0x18220 0x4>; 366 clocks = <&coreclk 0>; 367 #clock-cells = <1>; 368 }; 369 370 coreclk: mvebu-sar@18600 { 371 compatible = "marvell,armada-380-core-clock"; 372 reg = <0x18600 0x04>; 373 #clock-cells = <1>; 374 }; 375 376 mbusc: mbus-controller@20000 { 377 compatible = "marvell,mbus-controller"; 378 reg = <0x20000 0x100>, <0x20180 0x20>, 379 <0x20250 0x8>; 380 }; 381 382 mpic: interrupt-controller@20a00 { 383 compatible = "marvell,mpic"; 384 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 385 #interrupt-cells = <1>; 386 #size-cells = <1>; 387 interrupt-controller; 388 msi-controller; 389 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 390 }; 391 392 timer: timer@20300 { 393 compatible = "marvell,armada-380-timer", 394 "marvell,armada-xp-timer"; 395 reg = <0x20300 0x30>, <0x21040 0x30>; 396 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 397 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 398 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 399 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 400 <&mpic 5>, 401 <&mpic 6>; 402 clocks = <&coreclk 2>, <&refclk>; 403 clock-names = "nbclk", "fixed"; 404 }; 405 406 watchdog: watchdog@20300 { 407 compatible = "marvell,armada-380-wdt"; 408 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; 409 clocks = <&coreclk 2>, <&refclk>; 410 clock-names = "nbclk", "fixed"; 411 }; 412 413 cpurst: cpurst@20800 { 414 compatible = "marvell,armada-370-cpu-reset"; 415 reg = <0x20800 0x10>; 416 }; 417 418 mpcore-soc-ctrl@20d20 { 419 compatible = "marvell,armada-380-mpcore-soc-ctrl"; 420 reg = <0x20d20 0x6c>; 421 }; 422 423 coherencyfab: coherency-fabric@21010 { 424 compatible = "marvell,armada-380-coherency-fabric"; 425 reg = <0x21010 0x1c>; 426 }; 427 428 pmsu: pmsu@22000 { 429 compatible = "marvell,armada-380-pmsu"; 430 reg = <0x22000 0x1000>; 431 }; 432 433 /* 434 * As a special exception to the "order by 435 * register address" rule, the eth0 node is 436 * placed here to ensure that it gets 437 * registered as the first interface, since 438 * the network subsystem doesn't allow naming 439 * interfaces using DT aliases. Without this, 440 * the ordering of interfaces is different 441 * from the one used in U-Boot and the 442 * labeling of interfaces on the boards, which 443 * is very confusing for users. 444 */ 445 eth0: ethernet@70000 { 446 compatible = "marvell,armada-370-neta"; 447 reg = <0x70000 0x4000>; 448 interrupts-extended = <&mpic 8>; 449 clocks = <&gateclk 4>; 450 tx-csum-limit = <9800>; 451 status = "disabled"; 452 }; 453 454 eth1: ethernet@30000 { 455 compatible = "marvell,armada-370-neta"; 456 reg = <0x30000 0x4000>; 457 interrupts-extended = <&mpic 10>; 458 clocks = <&gateclk 3>; 459 status = "disabled"; 460 }; 461 462 eth2: ethernet@34000 { 463 compatible = "marvell,armada-370-neta"; 464 reg = <0x34000 0x4000>; 465 interrupts-extended = <&mpic 12>; 466 clocks = <&gateclk 2>; 467 status = "disabled"; 468 }; 469 470 usb0: usb@58000 { 471 compatible = "marvell,orion-ehci"; 472 reg = <0x58000 0x500>; 473 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&gateclk 18>; 475 status = "disabled"; 476 }; 477 478 xor0: xor@60800 { 479 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 480 reg = <0x60800 0x100 481 0x60a00 0x100>; 482 clocks = <&gateclk 22>; 483 status = "okay"; 484 485 xor00 { 486 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 487 dmacap,memcpy; 488 dmacap,xor; 489 }; 490 xor01 { 491 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 492 dmacap,memcpy; 493 dmacap,xor; 494 dmacap,memset; 495 }; 496 }; 497 498 xor1: xor@60900 { 499 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 500 reg = <0x60900 0x100 501 0x60b00 0x100>; 502 clocks = <&gateclk 28>; 503 status = "okay"; 504 505 xor10 { 506 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 507 dmacap,memcpy; 508 dmacap,xor; 509 }; 510 xor11 { 511 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 512 dmacap,memcpy; 513 dmacap,xor; 514 dmacap,memset; 515 }; 516 }; 517 518 mdio: mdio@72004 { 519 #address-cells = <1>; 520 #size-cells = <0>; 521 compatible = "marvell,orion-mdio"; 522 reg = <0x72004 0x4>; 523 clocks = <&gateclk 4>; 524 }; 525 526 cesa: crypto@90000 { 527 compatible = "marvell,armada-38x-crypto"; 528 reg = <0x90000 0x10000>; 529 reg-names = "regs"; 530 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&gateclk 23>, <&gateclk 21>, 533 <&gateclk 14>, <&gateclk 16>; 534 clock-names = "cesa0", "cesa1", 535 "cesaz0", "cesaz1"; 536 marvell,crypto-srams = <&crypto_sram0>, 537 <&crypto_sram1>; 538 marvell,crypto-sram-size = <0x800>; 539 }; 540 541 rtc: rtc@a3800 { 542 compatible = "marvell,armada-380-rtc"; 543 reg = <0xa3800 0x20>, <0x184a0 0x0c>; 544 reg-names = "rtc", "rtc-soc"; 545 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 546 }; 547 548 ahci0: sata@a8000 { 549 compatible = "marvell,armada-380-ahci"; 550 reg = <0xa8000 0x2000>; 551 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&gateclk 15>; 553 status = "disabled"; 554 }; 555 556 bm: bm@c8000 { 557 compatible = "marvell,armada-380-neta-bm"; 558 reg = <0xc8000 0xac>; 559 clocks = <&gateclk 13>; 560 internal-mem = <&bm_bppi>; 561 status = "disabled"; 562 }; 563 564 ahci1: sata@e0000 { 565 compatible = "marvell,armada-380-ahci"; 566 reg = <0xe0000 0x2000>; 567 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&gateclk 30>; 569 status = "disabled"; 570 }; 571 572 coredivclk: clock@e4250 { 573 compatible = "marvell,armada-380-corediv-clock"; 574 reg = <0xe4250 0xc>; 575 #clock-cells = <1>; 576 clocks = <&mainpll>; 577 clock-output-names = "nand"; 578 }; 579 580 thermal: thermal@e8078 { 581 compatible = "marvell,armada380-thermal"; 582 reg = <0xe4078 0x4>, <0xe4074 0x4>; 583 status = "okay"; 584 }; 585 586 nand: flash@d0000 { 587 compatible = "marvell,armada370-nand"; 588 reg = <0xd0000 0x54>; 589 #address-cells = <1>; 590 #size-cells = <1>; 591 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&coredivclk 0>; 593 status = "disabled"; 594 }; 595 596 sdhci: sdhci@d8000 { 597 compatible = "marvell,armada-380-sdhci"; 598 reg-names = "sdhci", "mbus", "conf-sdio3"; 599 reg = <0xd8000 0x1000>, 600 <0xdc000 0x100>, 601 <0x18454 0x4>; 602 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&gateclk 17>; 604 mrvl,clk-delay-cycles = <0x1F>; 605 status = "disabled"; 606 }; 607 608 usb3_0: usb3@f0000 { 609 compatible = "marvell,armada-380-xhci"; 610 reg = <0xf0000 0x4000>,<0xf4000 0x4000>; 611 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&gateclk 9>; 613 status = "disabled"; 614 }; 615 616 usb3_1: usb3@f8000 { 617 compatible = "marvell,armada-380-xhci"; 618 reg = <0xf8000 0x4000>,<0xfc000 0x4000>; 619 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&gateclk 10>; 621 status = "disabled"; 622 }; 623 }; 624 625 crypto_sram0: sa-sram0 { 626 compatible = "mmio-sram"; 627 reg = <MBUS_ID(0x09, 0x19) 0 0x800>; 628 clocks = <&gateclk 23>; 629 #address-cells = <1>; 630 #size-cells = <1>; 631 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>; 632 }; 633 634 crypto_sram1: sa-sram1 { 635 compatible = "mmio-sram"; 636 reg = <MBUS_ID(0x09, 0x15) 0 0x800>; 637 clocks = <&gateclk 21>; 638 #address-cells = <1>; 639 #size-cells = <1>; 640 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>; 641 }; 642 643 bm_bppi: bm-bppi { 644 compatible = "mmio-sram"; 645 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>; 646 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; 647 #address-cells = <1>; 648 #size-cells = <1>; 649 clocks = <&gateclk 13>; 650 no-memory-wc; 651 status = "disabled"; 652 }; 653 654 spi0: spi@10600 { 655 compatible = "marvell,armada-380-spi", 656 "marvell,orion-spi"; 657 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>; 658 #address-cells = <1>; 659 #size-cells = <0>; 660 cell-index = <0>; 661 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&coreclk 0>; 663 status = "disabled"; 664 }; 665 666 spi1: spi@10680 { 667 compatible = "marvell,armada-380-spi", 668 "marvell,orion-spi"; 669 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 cell-index = <1>; 673 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&coreclk 0>; 675 status = "disabled"; 676 }; 677 }; 678 679 clocks { 680 /* 1 GHz fixed main PLL */ 681 mainpll: mainpll { 682 compatible = "fixed-clock"; 683 #clock-cells = <0>; 684 clock-frequency = <1000000000>; 685 }; 686 687 /* 25 MHz reference crystal */ 688 refclk: oscillator { 689 compatible = "fixed-clock"; 690 #clock-cells = <0>; 691 clock-frequency = <25000000>; 692 }; 693 }; 694}; 695