1/* 2 * Device Tree Source for the Axis ARTPEC-6 SoC 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/interrupt-controller/arm-gic.h> 44#include <dt-bindings/clock/axis,artpec6-clkctrl.h> 45#include "skeleton.dtsi" 46 47/ { 48 compatible = "axis,artpec6"; 49 interrupt-parent = <&intc>; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 55 cpu0: cpu@0 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a9"; 58 reg = <0>; 59 next-level-cache = <&pl310>; 60 }; 61 62 cpu1: cpu@1 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a9"; 65 reg = <1>; 66 next-level-cache = <&pl310>; 67 }; 68 }; 69 70 syscon: syscon@f8000000 { 71 compatible = "axis,artpec6-syscon", "syscon"; 72 reg = <0xf8000000 0x48>; 73 }; 74 75 psci { 76 compatible = "arm,psci-0.2", "arm,psci"; 77 method = "smc"; 78 psci_version = <0x84000000>; 79 cpu_on = <0x84000003>; 80 system_reset = <0x84000009>; 81 }; 82 83 scu@faf00000 { 84 compatible = "arm,cortex-a9-scu"; 85 reg = <0xfaf00000 0x58>; 86 }; 87 88 /* Main external clock driving CPU and peripherals */ 89 ext_clk: ext_clk { 90 #clock-cells = <0>; 91 compatible = "fixed-clock"; 92 clock-frequency = <50000000>; 93 }; 94 95 eth_phy_ref_clk: eth_phy_ref_clk { 96 #clock-cells = <0>; 97 compatible = "fixed-clock"; 98 clock-frequency = <125000000>; 99 }; 100 101 clkctrl: clkctrl@0xf8000000 { 102 #clock-cells = <1>; 103 compatible = "axis,artpec6-clkctrl"; 104 reg = <0xf8000000 0x48>; 105 clocks = <&ext_clk>; 106 clock-names = "sys_refclk"; 107 }; 108 109 gtimer@faf00200 { 110 compatible = "arm,cortex-a9-global-timer"; 111 reg = <0xfaf00200 0x20>; 112 interrupts = <GIC_PPI 11 0xf01>; 113 clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; 114 }; 115 116 timer@faf00600 { 117 compatible = "arm,cortex-a9-twd-timer"; 118 reg = <0xfaf00600 0x20>; 119 interrupts = <GIC_PPI 13 0xf04>; 120 clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; 121 status = "disabled"; 122 }; 123 124 intc: interrupt-controller@faf01000 { 125 interrupt-controller; 126 compatible = "arm,cortex-a9-gic"; 127 #interrupt-cells = <3>; 128 reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >; 129 }; 130 131 pl310: cache-controller@faf10000 { 132 compatible = "arm,pl310-cache"; 133 cache-unified; 134 cache-level = <2>; 135 reg = <0xfaf10000 0x1000>; 136 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 137 arm,data-latency = <1 1 1>; 138 arm,tag-latency = <1 1 1>; 139 arm,filter-ranges = <0x0 0x80000000>; 140 arm,double-linefill = <1>; 141 arm,double-linefill-incr = <0>; 142 arm,double-linefill-wrap = <0>; 143 prefetch-data = <1>; 144 prefetch-instr = <1>; 145 arm,prefetch-offset = <0>; 146 arm,prefetch-drop = <1>; 147 }; 148 149 pmu { 150 compatible = "arm,cortex-a9-pmu"; 151 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 153 interrupt-affinity = <&cpu0>, <&cpu1>; 154 interrupt-parent = <&intc>; 155 }; 156 157 pcie: pcie@f8050000 { 158 compatible = "axis,artpec6-pcie", "snps,dw-pcie"; 159 reg = <0xf8050000 0x2000 160 0xf8040000 0x1000 161 0xc0000000 0x2000>; 162 reg-names = "dbi", "phy", "config"; 163 #address-cells = <3>; 164 #size-cells = <2>; 165 device_type = "pci"; 166 /* downstream I/O */ 167 ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 168 /* non-prefetchable memory */ 169 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; 170 num-lanes = <2>; 171 bus-range = <0x00 0xff>; 172 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 173 interrupt-names = "msi"; 174 #interrupt-cells = <1>; 175 interrupt-map-mask = <0 0 0 0x7>; 176 interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 177 <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 178 <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 179 <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 180 axis,syscon-pcie = <&syscon>; 181 status = "disabled"; 182 }; 183 184 amba@0 { 185 compatible = "simple-bus"; 186 #address-cells = <0x1>; 187 #size-cells = <0x1>; 188 interrupt-parent = <&intc>; 189 ranges; 190 dma-ranges = <0x80000000 0x00000000 0x40000000>; 191 dma-coherent; 192 193 ethernet: ethernet@f8010000 { 194 clock-names = "phy_ref_clk", "apb_pclk"; 195 clocks = <ð_phy_ref_clk>, 196 <&clkctrl ARTPEC6_CLK_ETH_ACLK>; 197 compatible = "snps,dwc-qos-ethernet-4.10"; 198 interrupt-parent = <&intc>; 199 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 200 reg = <0xf8010000 0x4000>; 201 202 snps,write-requests = <2>; 203 snps,read-requests = <16>; 204 snps,txpbl = <8>; 205 snps,rxpbl = <2>; 206 207 status = "disabled"; 208 }; 209 210 uart0: serial@f8036000 { 211 compatible = "arm,pl011", "arm,primecell"; 212 reg = <0xf8036000 0x1000>; 213 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 214 clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, 215 <&clkctrl ARTPEC6_CLK_UART_PCLK>; 216 clock-names = "uart_clk", "apb_pclk"; 217 status = "disabled"; 218 }; 219 uart1: serial@f8037000 { 220 compatible = "arm,pl011", "arm,primecell"; 221 reg = <0xf8037000 0x1000>; 222 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, 224 <&clkctrl ARTPEC6_CLK_UART_PCLK>; 225 clock-names = "uart_clk", "apb_pclk"; 226 status = "disabled"; 227 }; 228 uart2: serial@f8038000 { 229 compatible = "arm,pl011", "arm,primecell"; 230 reg = <0xf8038000 0x1000>; 231 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, 233 <&clkctrl ARTPEC6_CLK_UART_PCLK>; 234 clock-names = "uart_clk", "apb_pclk"; 235 status = "disabled"; 236 }; 237 uart3: serial@f8039000 { 238 compatible = "arm,pl011", "arm,primecell"; 239 reg = <0xf8039000 0x1000>; 240 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, 242 <&clkctrl ARTPEC6_CLK_UART_PCLK>; 243 clock-names = "uart_clk", "apb_pclk"; 244 status = "disabled"; 245 }; 246 }; 247}; 248