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1/*
2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
3 *                   applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
4 *                   AT91SAM9X25, AT91SAM9X35 SoC
5 *
6 *  Copyright (C) 2012 Atmel,
7 *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12#include "skeleton.dtsi"
13#include <dt-bindings/dma/at91.h>
14#include <dt-bindings/pinctrl/at91.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/clock/at91.h>
18
19/ {
20	model = "Atmel AT91SAM9x5 family SoC";
21	compatible = "atmel,at91sam9x5";
22	interrupt-parent = <&aic>;
23
24	aliases {
25		serial0 = &dbgu;
26		serial1 = &usart0;
27		serial2 = &usart1;
28		serial3 = &usart2;
29		gpio0 = &pioA;
30		gpio1 = &pioB;
31		gpio2 = &pioC;
32		gpio3 = &pioD;
33		tcb0 = &tcb0;
34		tcb1 = &tcb1;
35		i2c0 = &i2c0;
36		i2c1 = &i2c1;
37		i2c2 = &i2c2;
38		ssc0 = &ssc0;
39		pwm0 = &pwm0;
40	};
41	cpus {
42		#address-cells = <0>;
43		#size-cells = <0>;
44
45		cpu {
46			compatible = "arm,arm926ej-s";
47			device_type = "cpu";
48		};
49	};
50
51	memory {
52		reg = <0x20000000 0x10000000>;
53	};
54
55	clocks {
56		slow_xtal: slow_xtal {
57			compatible = "fixed-clock";
58			#clock-cells = <0>;
59			clock-frequency = <0>;
60		};
61
62		main_xtal: main_xtal {
63			compatible = "fixed-clock";
64			#clock-cells = <0>;
65			clock-frequency = <0>;
66		};
67
68		adc_op_clk: adc_op_clk{
69			compatible = "fixed-clock";
70			#clock-cells = <0>;
71			clock-frequency = <1000000>;
72		};
73	};
74
75	sram: sram@00300000 {
76		compatible = "mmio-sram";
77		reg = <0x00300000 0x8000>;
78	};
79
80	ahb {
81		compatible = "simple-bus";
82		#address-cells = <1>;
83		#size-cells = <1>;
84		ranges;
85
86		apb {
87			compatible = "simple-bus";
88			#address-cells = <1>;
89			#size-cells = <1>;
90			ranges;
91
92			aic: interrupt-controller@fffff000 {
93				#interrupt-cells = <3>;
94				compatible = "atmel,at91rm9200-aic";
95				interrupt-controller;
96				reg = <0xfffff000 0x200>;
97				atmel,external-irqs = <31>;
98			};
99
100			matrix: matrix@ffffde00 {
101				compatible = "atmel,at91sam9x5-matrix", "syscon";
102				reg = <0xffffde00 0x100>;
103			};
104
105			pmecc: ecc-engine@ffffe000 {
106				compatible = "atmel,at91sam9g45-pmecc";
107				reg = <0xffffe000 0x600>,
108				      <0xffffe600 0x200>;
109			};
110
111			ramc0: ramc@ffffe800 {
112				compatible = "atmel,at91sam9g45-ddramc";
113				reg = <0xffffe800 0x200>;
114				clocks = <&ddrck>;
115				clock-names = "ddrck";
116			};
117
118			smc: smc@ffffea00 {
119				compatible = "atmel,at91sam9260-smc", "syscon";
120				reg = <0xffffea00 0x200>;
121			};
122
123			pmc: pmc@fffffc00 {
124				compatible = "atmel,at91sam9x5-pmc", "syscon";
125				reg = <0xfffffc00 0x200>;
126				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
127				interrupt-controller;
128				#address-cells = <1>;
129				#size-cells = <0>;
130				#interrupt-cells = <1>;
131
132				main_rc_osc: main_rc_osc {
133					compatible = "atmel,at91sam9x5-clk-main-rc-osc";
134					#clock-cells = <0>;
135					interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
136					clock-frequency = <12000000>;
137					clock-accuracy = <50000000>;
138				};
139
140				main_osc: main_osc {
141					compatible = "atmel,at91rm9200-clk-main-osc";
142					#clock-cells = <0>;
143					interrupts-extended = <&pmc AT91_PMC_MOSCS>;
144					clocks = <&main_xtal>;
145				};
146
147				main: mainck {
148					compatible = "atmel,at91sam9x5-clk-main";
149					#clock-cells = <0>;
150					interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
151					clocks = <&main_rc_osc>, <&main_osc>;
152				};
153
154				plla: pllack {
155					compatible = "atmel,at91rm9200-clk-pll";
156					#clock-cells = <0>;
157					interrupts-extended = <&pmc AT91_PMC_LOCKA>;
158					clocks = <&main>;
159					reg = <0>;
160					atmel,clk-input-range = <2000000 32000000>;
161					#atmel,pll-clk-output-range-cells = <4>;
162					atmel,pll-clk-output-ranges = <745000000 800000000 0 0
163								       695000000 750000000 1 0
164								       645000000 700000000 2 0
165								       595000000 650000000 3 0
166								       545000000 600000000 0 1
167								       495000000 555000000 1 1
168								       445000000 500000000 2 1
169								       400000000 450000000 3 1>;
170				};
171
172				plladiv: plladivck {
173					compatible = "atmel,at91sam9x5-clk-plldiv";
174					#clock-cells = <0>;
175					clocks = <&plla>;
176				};
177
178				utmi: utmick {
179					compatible = "atmel,at91sam9x5-clk-utmi";
180					#clock-cells = <0>;
181					interrupts-extended = <&pmc AT91_PMC_LOCKU>;
182					clocks = <&main>;
183				};
184
185				mck: masterck {
186					compatible = "atmel,at91sam9x5-clk-master";
187					#clock-cells = <0>;
188					interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
189					clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
190					atmel,clk-output-range = <0 133333333>;
191					atmel,clk-divisors = <1 2 4 3>;
192					atmel,master-clk-have-div3-pres;
193				};
194
195				usb: usbck {
196					compatible = "atmel,at91sam9x5-clk-usb";
197					#clock-cells = <0>;
198					clocks = <&plladiv>, <&utmi>;
199				};
200
201				prog: progck {
202					compatible = "atmel,at91sam9x5-clk-programmable";
203					#address-cells = <1>;
204					#size-cells = <0>;
205					interrupt-parent = <&pmc>;
206					clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
207
208					prog0: prog0 {
209						#clock-cells = <0>;
210						reg = <0>;
211						interrupts = <AT91_PMC_PCKRDY(0)>;
212					};
213
214					prog1: prog1 {
215						#clock-cells = <0>;
216						reg = <1>;
217						interrupts = <AT91_PMC_PCKRDY(1)>;
218					};
219				};
220
221				smd: smdclk {
222					compatible = "atmel,at91sam9x5-clk-smd";
223					#clock-cells = <0>;
224					clocks = <&plladiv>, <&utmi>;
225				};
226
227				systemck {
228					compatible = "atmel,at91rm9200-clk-system";
229					#address-cells = <1>;
230					#size-cells = <0>;
231
232					ddrck: ddrck {
233						#clock-cells = <0>;
234						reg = <2>;
235						clocks = <&mck>;
236					};
237
238					smdck: smdck {
239						#clock-cells = <0>;
240						reg = <4>;
241						clocks = <&smd>;
242					};
243
244					uhpck: uhpck {
245						#clock-cells = <0>;
246						reg = <6>;
247						clocks = <&usb>;
248					};
249
250					udpck: udpck {
251						#clock-cells = <0>;
252						reg = <7>;
253						clocks = <&usb>;
254					};
255
256					pck0: pck0 {
257						#clock-cells = <0>;
258						reg = <8>;
259						clocks = <&prog0>;
260					};
261
262					pck1: pck1 {
263						#clock-cells = <0>;
264						reg = <9>;
265						clocks = <&prog1>;
266					};
267				};
268
269				periphck {
270					compatible = "atmel,at91sam9x5-clk-peripheral";
271					#address-cells = <1>;
272					#size-cells = <0>;
273					clocks = <&mck>;
274
275					pioAB_clk: pioAB_clk {
276						#clock-cells = <0>;
277						reg = <2>;
278					};
279
280					pioCD_clk: pioCD_clk {
281						#clock-cells = <0>;
282						reg = <3>;
283					};
284
285					smd_clk: smd_clk {
286						#clock-cells = <0>;
287						reg = <4>;
288					};
289
290					usart0_clk: usart0_clk {
291						#clock-cells = <0>;
292						reg = <5>;
293					};
294
295					usart1_clk: usart1_clk {
296						#clock-cells = <0>;
297						reg = <6>;
298					};
299
300					usart2_clk: usart2_clk {
301						#clock-cells = <0>;
302						reg = <7>;
303					};
304
305					twi0_clk: twi0_clk {
306						reg = <9>;
307						#clock-cells = <0>;
308					};
309
310					twi1_clk: twi1_clk {
311						#clock-cells = <0>;
312						reg = <10>;
313					};
314
315					twi2_clk: twi2_clk {
316						#clock-cells = <0>;
317						reg = <11>;
318					};
319
320					mci0_clk: mci0_clk {
321						#clock-cells = <0>;
322						reg = <12>;
323					};
324
325					spi0_clk: spi0_clk {
326						#clock-cells = <0>;
327						reg = <13>;
328					};
329
330					spi1_clk: spi1_clk {
331						#clock-cells = <0>;
332						reg = <14>;
333					};
334
335					uart0_clk: uart0_clk {
336						#clock-cells = <0>;
337						reg = <15>;
338					};
339
340					uart1_clk: uart1_clk {
341						#clock-cells = <0>;
342						reg = <16>;
343					};
344
345					tcb0_clk: tcb0_clk {
346						#clock-cells = <0>;
347						reg = <17>;
348					};
349
350					pwm_clk: pwm_clk {
351						#clock-cells = <0>;
352						reg = <18>;
353					};
354
355					adc_clk: adc_clk {
356						#clock-cells = <0>;
357						reg = <19>;
358					};
359
360					dma0_clk: dma0_clk {
361						#clock-cells = <0>;
362						reg = <20>;
363					};
364
365					dma1_clk: dma1_clk {
366						#clock-cells = <0>;
367						reg = <21>;
368					};
369
370					uhphs_clk: uhphs_clk {
371						#clock-cells = <0>;
372						reg = <22>;
373					};
374
375					udphs_clk: udphs_clk {
376						#clock-cells = <0>;
377						reg = <23>;
378					};
379
380					mci1_clk: mci1_clk {
381						#clock-cells = <0>;
382						reg = <26>;
383					};
384
385					ssc0_clk: ssc0_clk {
386						#clock-cells = <0>;
387						reg = <28>;
388					};
389				};
390			};
391
392			rstc@fffffe00 {
393				compatible = "atmel,at91sam9g45-rstc";
394				reg = <0xfffffe00 0x10>;
395				clocks = <&clk32k>;
396			};
397
398			shdwc@fffffe10 {
399				compatible = "atmel,at91sam9x5-shdwc";
400				reg = <0xfffffe10 0x10>;
401				clocks = <&clk32k>;
402			};
403
404			pit: timer@fffffe30 {
405				compatible = "atmel,at91sam9260-pit";
406				reg = <0xfffffe30 0xf>;
407				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
408				clocks = <&mck>;
409			};
410
411			sckc@fffffe50 {
412				compatible = "atmel,at91sam9x5-sckc";
413				reg = <0xfffffe50 0x4>;
414
415				slow_osc: slow_osc {
416					compatible = "atmel,at91sam9x5-clk-slow-osc";
417					#clock-cells = <0>;
418					clocks = <&slow_xtal>;
419				};
420
421				slow_rc_osc: slow_rc_osc {
422					compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
423					#clock-cells = <0>;
424					clock-frequency = <32768>;
425					clock-accuracy = <50000000>;
426				};
427
428				clk32k: slck {
429					compatible = "atmel,at91sam9x5-clk-slow";
430					#clock-cells = <0>;
431					clocks = <&slow_rc_osc>, <&slow_osc>;
432				};
433			};
434
435			tcb0: timer@f8008000 {
436				compatible = "atmel,at91sam9x5-tcb";
437				reg = <0xf8008000 0x100>;
438				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
439				clocks = <&tcb0_clk>, <&clk32k>;
440				clock-names = "t0_clk", "slow_clk";
441			};
442
443			tcb1: timer@f800c000 {
444				compatible = "atmel,at91sam9x5-tcb";
445				reg = <0xf800c000 0x100>;
446				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
447				clocks = <&tcb0_clk>, <&clk32k>;
448				clock-names = "t0_clk", "slow_clk";
449			};
450
451			dma0: dma-controller@ffffec00 {
452				compatible = "atmel,at91sam9g45-dma";
453				reg = <0xffffec00 0x200>;
454				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
455				#dma-cells = <2>;
456				clocks = <&dma0_clk>;
457				clock-names = "dma_clk";
458			};
459
460			dma1: dma-controller@ffffee00 {
461				compatible = "atmel,at91sam9g45-dma";
462				reg = <0xffffee00 0x200>;
463				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
464				#dma-cells = <2>;
465				clocks = <&dma1_clk>;
466				clock-names = "dma_clk";
467			};
468
469			pinctrl@fffff400 {
470				#address-cells = <1>;
471				#size-cells = <1>;
472				compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
473				ranges = <0xfffff400 0xfffff400 0x800>;
474
475				/* shared pinctrl settings */
476				dbgu {
477					pinctrl_dbgu: dbgu-0 {
478						atmel,pins =
479							<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
480							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
481					};
482				};
483
484				ebi {
485					pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
486						atmel,pins =
487							<AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
488							 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
489							 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
490							 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
491							 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
492							 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
493							 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
494							 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
495					};
496
497					pinctrl_ebi_data_8_15: ebi-data-msb-0 {
498						atmel,pins =
499							<AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
500							 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
501							 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
502							 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
503							 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
504							 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
505							 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
506							 AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
507					};
508
509					pinctrl_ebi_addr_nand: ebi-addr-0 {
510						atmel,pins =
511							<AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE
512							 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
513					};
514				};
515
516				usart0 {
517					pinctrl_usart0: usart0-0 {
518						atmel,pins =
519							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA0 periph A with pullup */
520							 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA1 periph A */
521					};
522
523					pinctrl_usart0_rts: usart0_rts-0 {
524						atmel,pins =
525							<AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA2 periph A */
526					};
527
528					pinctrl_usart0_cts: usart0_cts-0 {
529						atmel,pins =
530							<AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA3 periph A */
531					};
532
533					pinctrl_usart0_sck: usart0_sck-0 {
534						atmel,pins =
535							<AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA4 periph A */
536					};
537				};
538
539				usart1 {
540					pinctrl_usart1: usart1-0 {
541						atmel,pins =
542							<AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA5 periph A with pullup */
543							 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA6 periph A */
544					};
545
546					pinctrl_usart1_rts: usart1_rts-0 {
547						atmel,pins =
548							<AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC27 periph C */
549					};
550
551					pinctrl_usart1_cts: usart1_cts-0 {
552						atmel,pins =
553							<AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC28 periph C */
554					};
555
556					pinctrl_usart1_sck: usart1_sck-0 {
557						atmel,pins =
558							<AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC29 periph C */
559					};
560				};
561
562				usart2 {
563					pinctrl_usart2: usart2-0 {
564						atmel,pins =
565							<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA7 periph A with pullup */
566							 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA8 periph A */
567					};
568
569					pinctrl_usart2_rts: usart2_rts-0 {
570						atmel,pins =
571							<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB0 periph B */
572					};
573
574					pinctrl_usart2_cts: usart2_cts-0 {
575						atmel,pins =
576							<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB1 periph B */
577					};
578
579					pinctrl_usart2_sck: usart2_sck-0 {
580						atmel,pins =
581							<AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB2 periph B */
582					};
583				};
584
585				uart0 {
586					pinctrl_uart0: uart0-0 {
587						atmel,pins =
588							<AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PC8 periph C */
589							 AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;	/* PC9 periph C with pullup */
590					};
591				};
592
593				uart1 {
594					pinctrl_uart1: uart1-0 {
595						atmel,pins =
596							<AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PC16 periph C */
597							 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;	/* PC17 periph C with pullup */
598					};
599				};
600
601				nand {
602					pinctrl_nand_oe_we: nand-oe-we-0 {
603						atmel,pins =
604							<AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE
605							 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
606					};
607
608					pinctrl_nand_rb: nand-rb-0 {
609						atmel,pins =
610							<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
611					};
612
613					pinctrl_nand_cs: nand-cs-0 {
614						atmel,pins =
615							<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
616					};
617				};
618
619				mmc0 {
620					pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
621						atmel,pins =
622							<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA17 periph A */
623							 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA16 periph A with pullup */
624							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA15 periph A with pullup */
625					};
626
627					pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
628						atmel,pins =
629							<AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA18 periph A with pullup */
630							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA19 periph A with pullup */
631							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA20 periph A with pullup */
632					};
633				};
634
635				mmc1 {
636					pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
637						atmel,pins =
638							<AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA13 periph B */
639							 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA12 periph B with pullup */
640							 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PA11 periph B with pullup */
641					};
642
643					pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
644						atmel,pins =
645							<AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA2 periph B with pullup */
646							 AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA3 periph B with pullup */
647							 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PA4 periph B with pullup */
648					};
649				};
650
651				ssc0 {
652					pinctrl_ssc0_tx: ssc0_tx-0 {
653						atmel,pins =
654							<AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA24 periph B */
655							 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA25 periph B */
656							 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA26 periph B */
657					};
658
659					pinctrl_ssc0_rx: ssc0_rx-0 {
660						atmel,pins =
661							<AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA27 periph B */
662							 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA28 periph B */
663							 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA29 periph B */
664					};
665				};
666
667				spi0 {
668					pinctrl_spi0: spi0-0 {
669						atmel,pins =
670							<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA11 periph A SPI0_MISO pin */
671							 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA12 periph A SPI0_MOSI pin */
672							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA13 periph A SPI0_SPCK pin */
673					};
674				};
675
676				spi1 {
677					pinctrl_spi1: spi1-0 {
678						atmel,pins =
679							<AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA21 periph B SPI1_MISO pin */
680							 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA22 periph B SPI1_MOSI pin */
681							 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA23 periph B SPI1_SPCK pin */
682					};
683				};
684
685				i2c0 {
686					pinctrl_i2c0: i2c0-0 {
687						atmel,pins =
688							<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA30 periph A I2C0 data */
689							 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA31 periph A I2C0 clock */
690					};
691				};
692
693				i2c1 {
694					pinctrl_i2c1: i2c1-0 {
695						atmel,pins =
696							<AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PC0 periph C I2C1 data */
697							 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC1 periph C I2C1 clock */
698					};
699				};
700
701				i2c2 {
702					pinctrl_i2c2: i2c2-0 {
703						atmel,pins =
704							<AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB4 periph B I2C2 data */
705							 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB5 periph B I2C2 clock */
706					};
707				};
708
709				i2c_gpio0 {
710					pinctrl_i2c_gpio0: i2c_gpio0-0 {
711						atmel,pins =
712							<AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE	/* PA30 gpio multidrive I2C0 data */
713							 AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;	/* PA31 gpio multidrive I2C0 clock */
714					};
715				};
716
717				i2c_gpio1 {
718					pinctrl_i2c_gpio1: i2c_gpio1-0 {
719						atmel,pins =
720							<AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE	/* PC0 gpio multidrive I2C1 data */
721							 AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;	/* PC1 gpio multidrive I2C1 clock */
722					};
723				};
724
725				i2c_gpio2 {
726					pinctrl_i2c_gpio2: i2c_gpio2-0 {
727						atmel,pins =
728							<AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE	/* PB4 gpio multidrive I2C2 data */
729							 AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;	/* PB5 gpio multidrive I2C2 clock */
730					};
731				};
732
733				pwm0 {
734					pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
735						atmel,pins =
736							<AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
737					};
738					pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 {
739						atmel,pins =
740							<AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE>;
741					};
742					pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 {
743						atmel,pins =
744							<AT91_PIOC 18 AT91_PERIPH_C AT91_PINCTRL_NONE>;
745					};
746
747					pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
748						atmel,pins =
749							<AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
750					};
751					pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 {
752						atmel,pins =
753							<AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE>;
754					};
755					pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 {
756						atmel,pins =
757							<AT91_PIOC 19 AT91_PERIPH_C AT91_PINCTRL_NONE>;
758					};
759
760					pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
761						atmel,pins =
762							<AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
763					};
764					pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 {
765						atmel,pins =
766							<AT91_PIOC 20 AT91_PERIPH_C AT91_PINCTRL_NONE>;
767					};
768
769					pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
770						atmel,pins =
771							<AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
772					};
773					pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 {
774						atmel,pins =
775							<AT91_PIOC 21 AT91_PERIPH_C AT91_PINCTRL_NONE>;
776					};
777				};
778
779				tcb0 {
780					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
781						atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
782					};
783
784					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
785						atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
786					};
787
788					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
789						atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
790					};
791
792					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
793						atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
794					};
795
796					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
797						atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
798					};
799
800					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
801						atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
802					};
803
804					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
805						atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
806					};
807
808					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
809						atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
810					};
811
812					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
813						atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
814					};
815				};
816
817				tcb1 {
818					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
819						atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
820					};
821
822					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
823						atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
824					};
825
826					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
827						atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
828					};
829
830					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
831						atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
832					};
833
834					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
835						atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
836					};
837
838					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
839						atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
840					};
841
842					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
843						atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
844					};
845
846					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
847						atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
848					};
849
850					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
851						atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
852					};
853				};
854
855				pioA: gpio@fffff400 {
856					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
857					reg = <0xfffff400 0x200>;
858					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
859					#gpio-cells = <2>;
860					gpio-controller;
861					interrupt-controller;
862					#interrupt-cells = <2>;
863					clocks = <&pioAB_clk>;
864				};
865
866				pioB: gpio@fffff600 {
867					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
868					reg = <0xfffff600 0x200>;
869					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
870					#gpio-cells = <2>;
871					gpio-controller;
872					#gpio-lines = <19>;
873					interrupt-controller;
874					#interrupt-cells = <2>;
875					clocks = <&pioAB_clk>;
876				};
877
878				pioC: gpio@fffff800 {
879					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
880					reg = <0xfffff800 0x200>;
881					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
882					#gpio-cells = <2>;
883					gpio-controller;
884					interrupt-controller;
885					#interrupt-cells = <2>;
886					clocks = <&pioCD_clk>;
887				};
888
889				pioD: gpio@fffffa00 {
890					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
891					reg = <0xfffffa00 0x200>;
892					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
893					#gpio-cells = <2>;
894					gpio-controller;
895					#gpio-lines = <22>;
896					interrupt-controller;
897					#interrupt-cells = <2>;
898					clocks = <&pioCD_clk>;
899				};
900			};
901
902			ssc0: ssc@f0010000 {
903				compatible = "atmel,at91sam9g45-ssc";
904				reg = <0xf0010000 0x4000>;
905				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
906				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>,
907				       <&dma0 1 AT91_DMA_CFG_PER_ID(14)>;
908				dma-names = "tx", "rx";
909				pinctrl-names = "default";
910				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
911				clocks = <&ssc0_clk>;
912				clock-names = "pclk";
913				status = "disabled";
914			};
915
916			mmc0: mmc@f0008000 {
917				compatible = "atmel,hsmci";
918				reg = <0xf0008000 0x600>;
919				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
920				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
921				dma-names = "rxtx";
922				pinctrl-names = "default";
923				clocks = <&mci0_clk>;
924				clock-names = "mci_clk";
925				#address-cells = <1>;
926				#size-cells = <0>;
927				status = "disabled";
928			};
929
930			mmc1: mmc@f000c000 {
931				compatible = "atmel,hsmci";
932				reg = <0xf000c000 0x600>;
933				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
934				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
935				dma-names = "rxtx";
936				pinctrl-names = "default";
937				clocks = <&mci1_clk>;
938				clock-names = "mci_clk";
939				#address-cells = <1>;
940				#size-cells = <0>;
941				status = "disabled";
942			};
943
944			dbgu: serial@fffff200 {
945				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
946				reg = <0xfffff200 0x200>;
947				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
948				pinctrl-names = "default";
949				pinctrl-0 = <&pinctrl_dbgu>;
950				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,
951				       <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
952				dma-names = "tx", "rx";
953				clocks = <&mck>;
954				clock-names = "usart";
955				status = "disabled";
956			};
957
958			usart0: serial@f801c000 {
959				compatible = "atmel,at91sam9260-usart";
960				reg = <0xf801c000 0x200>;
961				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
962				pinctrl-names = "default";
963				pinctrl-0 = <&pinctrl_usart0>;
964				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>,
965				       <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
966				dma-names = "tx", "rx";
967				clocks = <&usart0_clk>;
968				clock-names = "usart";
969				status = "disabled";
970			};
971
972			usart1: serial@f8020000 {
973				compatible = "atmel,at91sam9260-usart";
974				reg = <0xf8020000 0x200>;
975				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
976				pinctrl-names = "default";
977				pinctrl-0 = <&pinctrl_usart1>;
978				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>,
979				       <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
980				dma-names = "tx", "rx";
981				clocks = <&usart1_clk>;
982				clock-names = "usart";
983				status = "disabled";
984			};
985
986			usart2: serial@f8024000 {
987				compatible = "atmel,at91sam9260-usart";
988				reg = <0xf8024000 0x200>;
989				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
990				pinctrl-names = "default";
991				pinctrl-0 = <&pinctrl_usart2>;
992				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>,
993				       <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
994				dma-names = "tx", "rx";
995				clocks = <&usart2_clk>;
996				clock-names = "usart";
997				status = "disabled";
998			};
999
1000			i2c0: i2c@f8010000 {
1001				compatible = "atmel,at91sam9x5-i2c";
1002				reg = <0xf8010000 0x100>;
1003				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
1004				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>,
1005				       <&dma0 1 AT91_DMA_CFG_PER_ID(8)>;
1006				dma-names = "tx", "rx";
1007				#address-cells = <1>;
1008				#size-cells = <0>;
1009				pinctrl-names = "default";
1010				pinctrl-0 = <&pinctrl_i2c0>;
1011				clocks = <&twi0_clk>;
1012				status = "disabled";
1013			};
1014
1015			i2c1: i2c@f8014000 {
1016				compatible = "atmel,at91sam9x5-i2c";
1017				reg = <0xf8014000 0x100>;
1018				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
1019				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>,
1020				       <&dma1 1 AT91_DMA_CFG_PER_ID(6)>;
1021				dma-names = "tx", "rx";
1022				#address-cells = <1>;
1023				#size-cells = <0>;
1024				pinctrl-names = "default";
1025				pinctrl-0 = <&pinctrl_i2c1>;
1026				clocks = <&twi1_clk>;
1027				status = "disabled";
1028			};
1029
1030			i2c2: i2c@f8018000 {
1031				compatible = "atmel,at91sam9x5-i2c";
1032				reg = <0xf8018000 0x100>;
1033				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
1034				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>,
1035				       <&dma0 1 AT91_DMA_CFG_PER_ID(10)>;
1036				dma-names = "tx", "rx";
1037				#address-cells = <1>;
1038				#size-cells = <0>;
1039				pinctrl-names = "default";
1040				pinctrl-0 = <&pinctrl_i2c2>;
1041				clocks = <&twi2_clk>;
1042				status = "disabled";
1043			};
1044
1045			uart0: serial@f8040000 {
1046				compatible = "atmel,at91sam9260-usart";
1047				reg = <0xf8040000 0x200>;
1048				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
1049				pinctrl-names = "default";
1050				pinctrl-0 = <&pinctrl_uart0>;
1051				clocks = <&uart0_clk>;
1052				clock-names = "usart";
1053				status = "disabled";
1054			};
1055
1056			uart1: serial@f8044000 {
1057				compatible = "atmel,at91sam9260-usart";
1058				reg = <0xf8044000 0x200>;
1059				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
1060				pinctrl-names = "default";
1061				pinctrl-0 = <&pinctrl_uart1>;
1062				clocks = <&uart1_clk>;
1063				clock-names = "usart";
1064				status = "disabled";
1065			};
1066
1067			adc0: adc@f804c000 {
1068				#address-cells = <1>;
1069				#size-cells = <0>;
1070				compatible = "atmel,at91sam9x5-adc";
1071				reg = <0xf804c000 0x100>;
1072				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
1073				clocks = <&adc_clk>,
1074					 <&adc_op_clk>;
1075				clock-names = "adc_clk", "adc_op_clk";
1076				atmel,adc-use-external-triggers;
1077				atmel,adc-channels-used = <0xffff>;
1078				atmel,adc-vref = <3300>;
1079				atmel,adc-startup-time = <40>;
1080				atmel,adc-sample-hold-time = <11>;
1081				atmel,adc-res = <8 10>;
1082				atmel,adc-res-names = "lowres", "highres";
1083				atmel,adc-use-res = "highres";
1084
1085				trigger0 {
1086					trigger-name = "external-rising";
1087					trigger-value = <0x1>;
1088					trigger-external;
1089				};
1090
1091				trigger1 {
1092					trigger-name = "external-falling";
1093					trigger-value = <0x2>;
1094					trigger-external;
1095				};
1096
1097				trigger2 {
1098					trigger-name = "external-any";
1099					trigger-value = <0x3>;
1100					trigger-external;
1101				};
1102
1103				trigger3 {
1104					trigger-name = "continuous";
1105					trigger-value = <0x6>;
1106				};
1107			};
1108
1109			spi0: spi@f0000000 {
1110				#address-cells = <1>;
1111				#size-cells = <0>;
1112				compatible = "atmel,at91rm9200-spi";
1113				reg = <0xf0000000 0x100>;
1114				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
1115				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>,
1116				       <&dma0 1 AT91_DMA_CFG_PER_ID(2)>;
1117				dma-names = "tx", "rx";
1118				pinctrl-names = "default";
1119				pinctrl-0 = <&pinctrl_spi0>;
1120				clocks = <&spi0_clk>;
1121				clock-names = "spi_clk";
1122				status = "disabled";
1123			};
1124
1125			spi1: spi@f0004000 {
1126				#address-cells = <1>;
1127				#size-cells = <0>;
1128				compatible = "atmel,at91rm9200-spi";
1129				reg = <0xf0004000 0x100>;
1130				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
1131				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>,
1132				       <&dma1 1 AT91_DMA_CFG_PER_ID(2)>;
1133				dma-names = "tx", "rx";
1134				pinctrl-names = "default";
1135				pinctrl-0 = <&pinctrl_spi1>;
1136				clocks = <&spi1_clk>;
1137				clock-names = "spi_clk";
1138				status = "disabled";
1139			};
1140
1141			usb2: gadget@f803c000 {
1142				#address-cells = <1>;
1143				#size-cells = <0>;
1144				compatible = "atmel,at91sam9g45-udc";
1145				reg = <0x00500000 0x80000
1146				       0xf803c000 0x400>;
1147				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
1148				clocks = <&utmi>, <&udphs_clk>;
1149				clock-names = "hclk", "pclk";
1150				status = "disabled";
1151
1152				ep@0 {
1153					reg = <0>;
1154					atmel,fifo-size = <64>;
1155					atmel,nb-banks = <1>;
1156				};
1157
1158				ep@1 {
1159					reg = <1>;
1160					atmel,fifo-size = <1024>;
1161					atmel,nb-banks = <2>;
1162					atmel,can-dma;
1163					atmel,can-isoc;
1164				};
1165
1166				ep@2 {
1167					reg = <2>;
1168					atmel,fifo-size = <1024>;
1169					atmel,nb-banks = <2>;
1170					atmel,can-dma;
1171					atmel,can-isoc;
1172				};
1173
1174				ep@3 {
1175					reg = <3>;
1176					atmel,fifo-size = <1024>;
1177					atmel,nb-banks = <3>;
1178					atmel,can-dma;
1179				};
1180
1181				ep@4 {
1182					reg = <4>;
1183					atmel,fifo-size = <1024>;
1184					atmel,nb-banks = <3>;
1185					atmel,can-dma;
1186				};
1187
1188				ep@5 {
1189					reg = <5>;
1190					atmel,fifo-size = <1024>;
1191					atmel,nb-banks = <3>;
1192					atmel,can-dma;
1193					atmel,can-isoc;
1194				};
1195
1196				ep@6 {
1197					reg = <6>;
1198					atmel,fifo-size = <1024>;
1199					atmel,nb-banks = <3>;
1200					atmel,can-dma;
1201					atmel,can-isoc;
1202				};
1203			};
1204
1205			watchdog@fffffe40 {
1206				compatible = "atmel,at91sam9260-wdt";
1207				reg = <0xfffffe40 0x10>;
1208				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1209				clocks = <&clk32k>;
1210				atmel,watchdog-type = "hardware";
1211				atmel,reset-type = "all";
1212				atmel,dbg-halt;
1213				status = "disabled";
1214			};
1215
1216			rtc@fffffeb0 {
1217				compatible = "atmel,at91sam9x5-rtc";
1218				reg = <0xfffffeb0 0x40>;
1219				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1220				clocks = <&clk32k>;
1221				status = "disabled";
1222			};
1223
1224			pwm0: pwm@f8034000 {
1225				compatible = "atmel,at91sam9rl-pwm";
1226				reg = <0xf8034000 0x300>;
1227				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
1228				clocks = <&pwm_clk>;
1229				#pwm-cells = <3>;
1230				status = "disabled";
1231			};
1232		};
1233
1234		usb0: ohci@00600000 {
1235			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1236			reg = <0x00600000 0x100000>;
1237			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1238			clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1239			clock-names = "ohci_clk", "hclk", "uhpck";
1240			status = "disabled";
1241		};
1242
1243		usb1: ehci@00700000 {
1244			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1245			reg = <0x00700000 0x100000>;
1246			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1247			clocks = <&utmi>, <&uhphs_clk>;
1248			clock-names = "usb_clk", "ehci_clk";
1249			status = "disabled";
1250		};
1251
1252		ebi: ebi@10000000 {
1253			compatible = "atmel,at91sam9x5-ebi";
1254			#address-cells = <2>;
1255			#size-cells = <1>;
1256			atmel,smc = <&smc>;
1257			atmel,matrix = <&matrix>;
1258			reg = <0x10000000 0x60000000>;
1259			ranges = <0x0 0x0 0x10000000 0x10000000
1260				  0x1 0x0 0x20000000 0x10000000
1261				  0x2 0x0 0x30000000 0x10000000
1262				  0x3 0x0 0x40000000 0x10000000
1263				  0x4 0x0 0x50000000 0x10000000
1264				  0x5 0x0 0x60000000 0x10000000>;
1265			clocks = <&mck>;
1266			status = "disabled";
1267
1268			nand_controller: nand-controller {
1269				compatible = "atmel,at91sam9g45-nand-controller";
1270				ecc-engine = <&pmecc>;
1271				#address-cells = <2>;
1272				#size-cells = <1>;
1273				ranges;
1274				status = "disabled";
1275			};
1276		};
1277	};
1278
1279	i2c-gpio-0 {
1280		compatible = "i2c-gpio";
1281		gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
1282			 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
1283			>;
1284		i2c-gpio,sda-open-drain;
1285		i2c-gpio,scl-open-drain;
1286		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
1287		#address-cells = <1>;
1288		#size-cells = <0>;
1289		pinctrl-names = "default";
1290		pinctrl-0 = <&pinctrl_i2c_gpio0>;
1291		status = "disabled";
1292	};
1293
1294	i2c-gpio-1 {
1295		compatible = "i2c-gpio";
1296		gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
1297			 &pioC 1 GPIO_ACTIVE_HIGH /* scl */
1298			>;
1299		i2c-gpio,sda-open-drain;
1300		i2c-gpio,scl-open-drain;
1301		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
1302		#address-cells = <1>;
1303		#size-cells = <0>;
1304		pinctrl-names = "default";
1305		pinctrl-0 = <&pinctrl_i2c_gpio1>;
1306		status = "disabled";
1307	};
1308
1309	i2c-gpio-2 {
1310		compatible = "i2c-gpio";
1311		gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
1312			 &pioB 5 GPIO_ACTIVE_HIGH /* scl */
1313			>;
1314		i2c-gpio,sda-open-drain;
1315		i2c-gpio,scl-open-drain;
1316		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
1317		#address-cells = <1>;
1318		#size-cells = <0>;
1319		pinctrl-names = "default";
1320		pinctrl-0 = <&pinctrl_i2c_gpio2>;
1321		status = "disabled";
1322	};
1323};
1324