1/* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Broadcom Corporation nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <dt-bindings/interrupt-controller/arm-gic.h> 34#include <dt-bindings/interrupt-controller/irq.h> 35#include <dt-bindings/clock/bcm-cygnus.h> 36 37#include "skeleton.dtsi" 38 39/ { 40 compatible = "brcm,cygnus"; 41 model = "Broadcom Cygnus SoC"; 42 interrupt-parent = <&gic>; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a9"; 51 next-level-cache = <&L2>; 52 reg = <0x0>; 53 }; 54 }; 55 56 /include/ "bcm-cygnus-clock.dtsi" 57 58 pmu { 59 compatible = "arm,cortex-a9-pmu"; 60 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 61 }; 62 63 core { 64 compatible = "simple-bus"; 65 ranges = <0x00000000 0x19000000 0x1000000>; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 69 timer@20200 { 70 compatible = "arm,cortex-a9-global-timer"; 71 reg = <0x20200 0x100>; 72 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 73 clocks = <&periph_clk>; 74 }; 75 76 gic: interrupt-controller@21000 { 77 compatible = "arm,cortex-a9-gic"; 78 #interrupt-cells = <3>; 79 #address-cells = <0>; 80 interrupt-controller; 81 reg = <0x21000 0x1000>, 82 <0x20100 0x100>; 83 }; 84 85 L2: l2-cache { 86 compatible = "arm,pl310-cache"; 87 reg = <0x22000 0x1000>; 88 cache-unified; 89 cache-level = <2>; 90 }; 91 }; 92 93 axi { 94 compatible = "simple-bus"; 95 ranges; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 99 otp: otp@0301c800 { 100 compatible = "brcm,ocotp"; 101 reg = <0x0301c800 0x2c>; 102 brcm,ocotp-size = <2048>; 103 status = "disabled"; 104 }; 105 106 pcie_phy: phy@0301d0a0 { 107 compatible = "brcm,cygnus-pcie-phy"; 108 reg = <0x0301d0a0 0x14>; 109 #address-cells = <1>; 110 #size-cells = <0>; 111 112 pcie0_phy: phy@0 { 113 reg = <0>; 114 #phy-cells = <0>; 115 }; 116 117 pcie1_phy: phy@1 { 118 reg = <1>; 119 #phy-cells = <0>; 120 }; 121 }; 122 123 pinctrl: pinctrl@0301d0c8 { 124 compatible = "brcm,cygnus-pinmux"; 125 reg = <0x0301d0c8 0x30>, 126 <0x0301d24c 0x2c>; 127 128 spi_0: spi_0 { 129 function = "spi0"; 130 groups = "spi0_grp"; 131 }; 132 133 spi_1: spi_1 { 134 function = "spi1"; 135 groups = "spi1_grp"; 136 }; 137 138 spi_2: spi_2 { 139 function = "spi2"; 140 groups = "spi2_grp"; 141 }; 142 }; 143 144 mailbox: mailbox@03024024 { 145 compatible = "brcm,iproc-mailbox"; 146 reg = <0x03024024 0x40>; 147 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 148 #interrupt-cells = <1>; 149 interrupt-controller; 150 #mbox-cells = <1>; 151 }; 152 153 gpio_crmu: gpio@03024800 { 154 compatible = "brcm,cygnus-crmu-gpio"; 155 reg = <0x03024800 0x50>, 156 <0x03024008 0x18>; 157 ngpios = <6>; 158 #gpio-cells = <2>; 159 gpio-controller; 160 interrupt-controller; 161 interrupt-parent = <&mailbox>; 162 interrupts = <0>; 163 }; 164 165 mdio: mdio@18002000 { 166 compatible = "brcm,iproc-mdio"; 167 reg = <0x18002000 0x8>; 168 #size-cells = <0>; 169 #address-cells = <1>; 170 status = "disabled"; 171 172 gphy0: ethernet-phy@0 { 173 reg = <0>; 174 }; 175 176 gphy1: ethernet-phy@1 { 177 reg = <1>; 178 }; 179 }; 180 181 switch: switch@18007000 { 182 compatible = "brcm,bcm11360-srab", "brcm,cygnus-srab"; 183 reg = <0x18007000 0x1000>; 184 status = "disabled"; 185 186 ports { 187 #address-cells = <1>; 188 #size-cells = <0>; 189 190 port@0 { 191 reg = <0>; 192 phy-handle = <&gphy0>; 193 phy-mode = "rgmii"; 194 }; 195 196 port@1 { 197 reg = <1>; 198 phy-handle = <&gphy1>; 199 phy-mode = "rgmii"; 200 }; 201 202 port@8 { 203 reg = <8>; 204 label = "cpu"; 205 ethernet = <ð0>; 206 fixed-link { 207 speed = <1000>; 208 full-duplex; 209 }; 210 }; 211 }; 212 }; 213 214 i2c0: i2c@18008000 { 215 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; 216 reg = <0x18008000 0x100>; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 220 clock-frequency = <100000>; 221 status = "disabled"; 222 }; 223 224 wdt0: wdt@18009000 { 225 compatible = "arm,sp805" , "arm,primecell"; 226 reg = <0x18009000 0x1000>; 227 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&axi81_clk>; 229 clock-names = "apb_pclk"; 230 }; 231 232 gpio_ccm: gpio@1800a000 { 233 compatible = "brcm,cygnus-ccm-gpio"; 234 reg = <0x1800a000 0x50>, 235 <0x0301d164 0x20>; 236 ngpios = <24>; 237 #gpio-cells = <2>; 238 gpio-controller; 239 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 240 interrupt-controller; 241 }; 242 243 i2c1: i2c@1800b000 { 244 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; 245 reg = <0x1800b000 0x100>; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 249 clock-frequency = <100000>; 250 status = "disabled"; 251 }; 252 253 pcie0: pcie@18012000 { 254 compatible = "brcm,iproc-pcie"; 255 reg = <0x18012000 0x1000>; 256 257 #interrupt-cells = <1>; 258 interrupt-map-mask = <0 0 0 0>; 259 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 260 261 linux,pci-domain = <0>; 262 263 bus-range = <0x00 0xff>; 264 265 #address-cells = <3>; 266 #size-cells = <2>; 267 device_type = "pci"; 268 ranges = <0x81000000 0 0 0x28000000 0 0x00010000 269 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; 270 271 phys = <&pcie0_phy>; 272 phy-names = "pcie-phy"; 273 274 status = "disabled"; 275 276 msi-parent = <&msi0>; 277 msi0: msi-controller { 278 compatible = "brcm,iproc-msi"; 279 msi-controller; 280 interrupt-parent = <&gic>; 281 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 285 }; 286 }; 287 288 pcie1: pcie@18013000 { 289 compatible = "brcm,iproc-pcie"; 290 reg = <0x18013000 0x1000>; 291 292 #interrupt-cells = <1>; 293 interrupt-map-mask = <0 0 0 0>; 294 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 295 296 linux,pci-domain = <1>; 297 298 bus-range = <0x00 0xff>; 299 300 #address-cells = <3>; 301 #size-cells = <2>; 302 device_type = "pci"; 303 ranges = <0x81000000 0 0 0x48000000 0 0x00010000 304 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; 305 306 phys = <&pcie1_phy>; 307 phy-names = "pcie-phy"; 308 309 status = "disabled"; 310 311 msi-parent = <&msi1>; 312 msi1: msi-controller { 313 compatible = "brcm,iproc-msi"; 314 msi-controller; 315 interrupt-parent = <&gic>; 316 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 320 }; 321 }; 322 323 dma0: dma@18018000 { 324 compatible = "arm,pl330", "arm,primecell"; 325 reg = <0x18018000 0x1000>; 326 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&apb_clk>; 336 clock-names = "apb_pclk"; 337 #dma-cells = <1>; 338 }; 339 340 uart0: serial@18020000 { 341 compatible = "snps,dw-apb-uart"; 342 reg = <0x18020000 0x100>; 343 reg-shift = <2>; 344 reg-io-width = <4>; 345 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&axi81_clk>; 347 clock-frequency = <100000000>; 348 status = "disabled"; 349 }; 350 351 uart1: serial@18021000 { 352 compatible = "snps,dw-apb-uart"; 353 reg = <0x18021000 0x100>; 354 reg-shift = <2>; 355 reg-io-width = <4>; 356 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&axi81_clk>; 358 clock-frequency = <100000000>; 359 status = "disabled"; 360 }; 361 362 uart2: serial@18022000 { 363 compatible = "snps,dw-apb-uart"; 364 reg = <0x18022000 0x100>; 365 reg-shift = <2>; 366 reg-io-width = <4>; 367 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&axi81_clk>; 369 clock-frequency = <100000000>; 370 status = "disabled"; 371 }; 372 373 uart3: serial@18023000 { 374 compatible = "snps,dw-apb-uart"; 375 reg = <0x18023000 0x100>; 376 reg-shift = <2>; 377 reg-io-width = <4>; 378 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&axi81_clk>; 380 clock-frequency = <100000000>; 381 status = "disabled"; 382 }; 383 384 spi0: spi@18028000 { 385 compatible = "arm,pl022", "arm,primecell"; 386 reg = <0x18028000 0x1000>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 390 pinctrl-0 = <&spi_0>; 391 clocks = <&axi81_clk>; 392 clock-names = "apb_pclk"; 393 status = "disabled"; 394 }; 395 396 spi1: spi@18029000 { 397 compatible = "arm,pl022", "arm,primecell"; 398 reg = <0x18029000 0x1000>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 402 pinctrl-0 = <&spi_1>; 403 clocks = <&axi81_clk>; 404 clock-names = "apb_pclk"; 405 status = "disabled"; 406 }; 407 408 spi2: spi@1802a000 { 409 compatible = "arm,pl022", "arm,primecell"; 410 reg = <0x1802a000 0x1000>; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 414 pinctrl-0 = <&spi_2>; 415 clocks = <&axi81_clk>; 416 clock-names = "apb_pclk"; 417 status = "disabled"; 418 }; 419 420 sdhci0: sdhci@18041000 { 421 compatible = "brcm,sdhci-iproc-cygnus"; 422 reg = <0x18041000 0x100>; 423 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>; 425 bus-width = <4>; 426 sdhci,auto-cmd12; 427 status = "disabled"; 428 }; 429 430 eth0: ethernet@18042000 { 431 compatible = "brcm,amac"; 432 reg = <0x18042000 0x1000>, 433 <0x18110000 0x1000>; 434 reg-names = "amac_base", "idm_base"; 435 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 436 status = "disabled"; 437 }; 438 439 sdhci1: sdhci@18043000 { 440 compatible = "brcm,sdhci-iproc-cygnus"; 441 reg = <0x18043000 0x100>; 442 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>; 444 bus-width = <4>; 445 sdhci,auto-cmd12; 446 status = "disabled"; 447 }; 448 449 nand: nand@18046000 { 450 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; 451 reg = <0x18046000 0x600>, <0xf8105408 0x600>, 452 <0x18046f00 0x20>; 453 reg-names = "nand", "iproc-idm", "iproc-ext"; 454 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 455 456 #address-cells = <1>; 457 #size-cells = <0>; 458 459 brcm,nand-has-wp; 460 }; 461 462 ehci0: usb@18048000 { 463 compatible = "generic-ehci"; 464 reg = <0x18048000 0x100>; 465 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 466 status = "disabled"; 467 }; 468 469 ohci0: usb@18048800 { 470 compatible = "generic-ohci"; 471 reg = <0x18048800 0x100>; 472 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 473 status = "disabled"; 474 }; 475 476 v3d: v3d@180a2000 { 477 compatible = "brcm,cygnus-v3d"; 478 reg = <0x180a2000 0x1000>; 479 clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>; 480 clock-names = "v3d_clk"; 481 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 482 status = "disabled"; 483 }; 484 485 vc4: gpu { 486 compatible = "brcm,cygnus-vc4"; 487 }; 488 489 gpio_asiu: gpio@180a5000 { 490 compatible = "brcm,cygnus-asiu-gpio"; 491 reg = <0x180a5000 0x668>; 492 ngpios = <146>; 493 #gpio-cells = <2>; 494 gpio-controller; 495 496 interrupt-controller; 497 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 498 gpio-ranges = <&pinctrl 0 42 1>, 499 <&pinctrl 1 44 3>, 500 <&pinctrl 4 48 1>, 501 <&pinctrl 5 50 3>, 502 <&pinctrl 8 126 1>, 503 <&pinctrl 9 155 1>, 504 <&pinctrl 10 152 1>, 505 <&pinctrl 11 154 1>, 506 <&pinctrl 12 153 1>, 507 <&pinctrl 13 127 3>, 508 <&pinctrl 16 140 1>, 509 <&pinctrl 17 145 7>, 510 <&pinctrl 24 130 10>, 511 <&pinctrl 34 141 4>, 512 <&pinctrl 38 54 1>, 513 <&pinctrl 39 56 3>, 514 <&pinctrl 42 60 3>, 515 <&pinctrl 45 64 3>, 516 <&pinctrl 48 68 2>, 517 <&pinctrl 50 84 6>, 518 <&pinctrl 56 94 6>, 519 <&pinctrl 62 72 1>, 520 <&pinctrl 63 70 1>, 521 <&pinctrl 64 80 1>, 522 <&pinctrl 65 74 3>, 523 <&pinctrl 68 78 1>, 524 <&pinctrl 69 82 1>, 525 <&pinctrl 70 156 17>, 526 <&pinctrl 87 104 12>, 527 <&pinctrl 99 102 2>, 528 <&pinctrl 101 90 4>, 529 <&pinctrl 105 116 6>, 530 <&pinctrl 111 100 2>, 531 <&pinctrl 113 122 4>, 532 <&pinctrl 123 11 1>, 533 <&pinctrl 124 38 4>, 534 <&pinctrl 128 43 1>, 535 <&pinctrl 129 47 1>, 536 <&pinctrl 130 49 1>, 537 <&pinctrl 131 53 1>, 538 <&pinctrl 132 55 1>, 539 <&pinctrl 133 59 1>, 540 <&pinctrl 134 63 1>, 541 <&pinctrl 135 67 1>, 542 <&pinctrl 136 71 1>, 543 <&pinctrl 137 73 1>, 544 <&pinctrl 138 77 1>, 545 <&pinctrl 139 79 1>, 546 <&pinctrl 140 81 1>, 547 <&pinctrl 141 83 1>, 548 <&pinctrl 142 10 1>; 549 }; 550 551 ts_adc_syscon: ts_adc_syscon@180a6000 { 552 compatible = "brcm,iproc-ts-adc-syscon", "syscon"; 553 reg = <0x180a6000 0xc30>; 554 }; 555 556 touchscreen: touchscreen@180a6000 { 557 compatible = "brcm,iproc-touchscreen"; 558 #address-cells = <1>; 559 #size-cells = <1>; 560 ts_syscon = <&ts_adc_syscon>; 561 clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; 562 clock-names = "tsc_clk"; 563 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 564 status = "disabled"; 565 }; 566 567 adc: adc@180a6000 { 568 compatible = "brcm,iproc-static-adc"; 569 #io-channel-cells = <1>; 570 io-channel-ranges; 571 adc-syscon = <&ts_adc_syscon>; 572 clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; 573 clock-names = "tsc_clk"; 574 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 575 status = "disabled"; 576 }; 577 578 keypad: keypad@180ac000 { 579 compatible = "brcm,bcm-keypad"; 580 reg = <0x180ac000 0x14c>; 581 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&asiu_clks BCM_CYGNUS_ASIU_KEYPAD_CLK>; 583 clock-names = "peri_clk"; 584 clock-frequency = <31250>; 585 pull-up-enabled; 586 col-debounce-filter-period = <0>; 587 status-debounce-filter-period = <0>; 588 row-output-enabled; 589 status = "disabled"; 590 }; 591 }; 592}; 593