1/* 2 * Broadcom BCM470X / BCM5301X ARM platform code. 3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, 4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs 5 * 6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11#include <dt-bindings/clock/bcm-nsp.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/input/input.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include "skeleton.dtsi" 17 18/ { 19 interrupt-parent = <&gic>; 20 21 chipcommonA { 22 compatible = "simple-bus"; 23 ranges = <0x00000000 0x18000000 0x00001000>; 24 #address-cells = <1>; 25 #size-cells = <1>; 26 27 uart0: serial@0300 { 28 compatible = "ns16550"; 29 reg = <0x0300 0x100>; 30 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 31 clocks = <&iprocslow>; 32 status = "disabled"; 33 }; 34 35 uart1: serial@0400 { 36 compatible = "ns16550"; 37 reg = <0x0400 0x100>; 38 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 39 clocks = <&iprocslow>; 40 status = "disabled"; 41 }; 42 }; 43 44 mpcore { 45 compatible = "simple-bus"; 46 ranges = <0x00000000 0x19000000 0x00023000>; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 50 a9pll: arm_clk@00000 { 51 #clock-cells = <0>; 52 compatible = "brcm,nsp-armpll"; 53 clocks = <&osc>; 54 reg = <0x00000 0x1000>; 55 }; 56 57 scu@20000 { 58 compatible = "arm,cortex-a9-scu"; 59 reg = <0x20000 0x100>; 60 }; 61 62 timer@20200 { 63 compatible = "arm,cortex-a9-global-timer"; 64 reg = <0x20200 0x100>; 65 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 66 clocks = <&periph_clk>; 67 }; 68 69 timer@20600 { 70 compatible = "arm,cortex-a9-twd-timer"; 71 reg = <0x20600 0x20>; 72 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 73 IRQ_TYPE_EDGE_RISING)>; 74 clocks = <&periph_clk>; 75 }; 76 77 watchdog@20620 { 78 compatible = "arm,cortex-a9-twd-wdt"; 79 reg = <0x20620 0x20>; 80 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 81 IRQ_TYPE_EDGE_RISING)>; 82 clocks = <&periph_clk>; 83 }; 84 85 gic: interrupt-controller@21000 { 86 compatible = "arm,cortex-a9-gic"; 87 #interrupt-cells = <3>; 88 #address-cells = <0>; 89 interrupt-controller; 90 reg = <0x21000 0x1000>, 91 <0x20100 0x100>; 92 }; 93 94 L2: cache-controller@22000 { 95 compatible = "arm,pl310-cache"; 96 reg = <0x22000 0x1000>; 97 cache-unified; 98 arm,shared-override; 99 prefetch-data = <1>; 100 prefetch-instr = <1>; 101 cache-level = <2>; 102 }; 103 }; 104 105 pmu { 106 compatible = "arm,cortex-a9-pmu"; 107 interrupts = 108 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 110 }; 111 112 clocks { 113 #address-cells = <1>; 114 #size-cells = <1>; 115 ranges; 116 117 osc: oscillator { 118 #clock-cells = <0>; 119 compatible = "fixed-clock"; 120 clock-frequency = <25000000>; 121 }; 122 123 iprocmed: iprocmed { 124 #clock-cells = <0>; 125 compatible = "fixed-factor-clock"; 126 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; 127 clock-div = <2>; 128 clock-mult = <1>; 129 }; 130 131 iprocslow: iprocslow { 132 #clock-cells = <0>; 133 compatible = "fixed-factor-clock"; 134 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; 135 clock-div = <4>; 136 clock-mult = <1>; 137 }; 138 139 periph_clk: periph_clk { 140 #clock-cells = <0>; 141 compatible = "fixed-factor-clock"; 142 clocks = <&a9pll>; 143 clock-div = <2>; 144 clock-mult = <1>; 145 }; 146 }; 147 148 usb2_phy: usb2-phy { 149 compatible = "brcm,ns-usb2-phy"; 150 reg = <0x1800c000 0x1000>; 151 reg-names = "dmu"; 152 #phy-cells = <0>; 153 clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; 154 clock-names = "phy-ref-clk"; 155 }; 156 157 usb3_phy: usb3-phy { 158 compatible = "brcm,ns-ax-usb3-phy"; 159 reg = <0x18105000 0x1000>, <0x18003000 0x1000>; 160 reg-names = "dmp", "ccb-mii"; 161 #phy-cells = <0>; 162 }; 163 164 axi@18000000 { 165 compatible = "brcm,bus-axi"; 166 reg = <0x18000000 0x1000>; 167 ranges = <0x00000000 0x18000000 0x00100000>; 168 #address-cells = <1>; 169 #size-cells = <1>; 170 171 #interrupt-cells = <1>; 172 interrupt-map-mask = <0x000fffff 0xffff>; 173 interrupt-map = 174 /* ChipCommon */ 175 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 176 177 /* Switch Register Access Block */ 178 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 179 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 180 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 181 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 182 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 183 <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 184 <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 185 <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 186 <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 187 <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 188 <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 189 <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 190 <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 191 192 /* PCIe Controller 0 */ 193 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 194 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 195 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 196 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 197 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 198 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 199 200 /* PCIe Controller 1 */ 201 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 202 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 203 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 204 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 205 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 206 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 207 208 /* PCIe Controller 2 */ 209 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 210 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 211 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 212 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 213 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 214 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 215 216 /* USB 2.0 Controller */ 217 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 218 219 /* USB 3.0 Controller */ 220 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 221 222 /* Ethernet Controller 0 */ 223 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 224 225 /* Ethernet Controller 1 */ 226 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 227 228 /* Ethernet Controller 2 */ 229 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 230 231 /* Ethernet Controller 3 */ 232 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 233 234 /* NAND Controller */ 235 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 236 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 237 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 238 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 239 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 240 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 241 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 242 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 243 244 chipcommon: chipcommon@0 { 245 reg = <0x00000000 0x1000>; 246 247 gpio-controller; 248 #gpio-cells = <2>; 249 }; 250 251 pcie0: pcie@12000 { 252 reg = <0x00012000 0x1000>; 253 }; 254 255 pcie1: pcie@13000 { 256 reg = <0x00013000 0x1000>; 257 }; 258 259 usb2: usb2@21000 { 260 reg = <0x00021000 0x1000>; 261 262 #address-cells = <1>; 263 #size-cells = <1>; 264 ranges; 265 266 interrupt-parent = <&gic>; 267 268 ehci: ehci@21000 { 269 #usb-cells = <0>; 270 271 compatible = "generic-ehci"; 272 reg = <0x00021000 0x1000>; 273 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 274 phys = <&usb2_phy>; 275 276 #address-cells = <1>; 277 #size-cells = <0>; 278 279 ehci_port1: port@1 { 280 reg = <1>; 281 #trigger-source-cells = <0>; 282 }; 283 284 ehci_port2: port@2 { 285 reg = <2>; 286 #trigger-source-cells = <0>; 287 }; 288 }; 289 290 ohci: ohci@22000 { 291 #usb-cells = <0>; 292 293 compatible = "generic-ohci"; 294 reg = <0x00022000 0x1000>; 295 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 296 297 #address-cells = <1>; 298 #size-cells = <0>; 299 300 ohci_port1: port@1 { 301 reg = <1>; 302 #trigger-source-cells = <0>; 303 }; 304 305 ohci_port2: port@2 { 306 reg = <2>; 307 #trigger-source-cells = <0>; 308 }; 309 }; 310 }; 311 312 usb3: usb3@23000 { 313 reg = <0x00023000 0x1000>; 314 315 #address-cells = <1>; 316 #size-cells = <1>; 317 ranges; 318 319 interrupt-parent = <&gic>; 320 321 xhci: xhci@23000 { 322 #usb-cells = <0>; 323 324 compatible = "generic-xhci"; 325 reg = <0x00023000 0x1000>; 326 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 327 phys = <&usb3_phy>; 328 phy-names = "usb"; 329 330 #address-cells = <1>; 331 #size-cells = <0>; 332 333 xhci_port1: port@1 { 334 reg = <1>; 335 #trigger-source-cells = <0>; 336 }; 337 }; 338 }; 339 340 gmac0: ethernet@24000 { 341 reg = <0x24000 0x800>; 342 }; 343 344 gmac1: ethernet@25000 { 345 reg = <0x25000 0x800>; 346 }; 347 348 gmac2: ethernet@26000 { 349 reg = <0x26000 0x800>; 350 }; 351 352 gmac3: ethernet@27000 { 353 reg = <0x27000 0x800>; 354 }; 355 }; 356 357 mdio: mdio@18003000 { 358 compatible = "brcm,iproc-mdio"; 359 reg = <0x18003000 0x8>; 360 #size-cells = <1>; 361 #address-cells = <0>; 362 status = "disabled"; 363 }; 364 365 i2c0: i2c@18009000 { 366 compatible = "brcm,iproc-i2c"; 367 reg = <0x18009000 0x50>; 368 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 clock-frequency = <100000>; 372 status = "disabled"; 373 }; 374 375 lcpll0: lcpll0@1800c100 { 376 #clock-cells = <1>; 377 compatible = "brcm,nsp-lcpll0"; 378 reg = <0x1800c100 0x14>; 379 clocks = <&osc>; 380 clock-output-names = "lcpll0", "pcie_phy", "sdio", 381 "ddr_phy"; 382 }; 383 384 genpll: genpll@1800c140 { 385 #clock-cells = <1>; 386 compatible = "brcm,nsp-genpll"; 387 reg = <0x1800c140 0x24>; 388 clocks = <&osc>; 389 clock-output-names = "genpll", "phy", "ethernetclk", 390 "usbclk", "iprocfast", "sata1", 391 "sata2"; 392 }; 393 394 thermal: thermal@1800c2c0 { 395 compatible = "brcm,ns-thermal"; 396 reg = <0x1800c2c0 0x10>; 397 #thermal-sensor-cells = <0>; 398 }; 399 400 srab: srab@18007000 { 401 compatible = "brcm,bcm5301x-srab"; 402 reg = <0x18007000 0x1000>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 406 status = "disabled"; 407 408 /* ports are defined in board DTS */ 409 }; 410 411 rng: rng@18004000 { 412 compatible = "brcm,bcm5301x-rng"; 413 reg = <0x18004000 0x14>; 414 }; 415 416 nand: nand@18028000 { 417 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; 418 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; 419 reg-names = "nand", "iproc-idm", "iproc-ext"; 420 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 421 422 #address-cells = <1>; 423 #size-cells = <0>; 424 425 brcm,nand-has-wp; 426 }; 427 428 spi@18029200 { 429 compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; 430 reg = <0x18029200 0x184>, 431 <0x18029000 0x124>, 432 <0x1811b408 0x004>, 433 <0x180293a0 0x01c>; 434 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; 435 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 442 interrupt-names = "spi_lr_fullness_reached", 443 "spi_lr_session_aborted", 444 "spi_lr_impatient", 445 "spi_lr_session_done", 446 "spi_lr_overhead", 447 "mspi_done", 448 "mspi_halted"; 449 clocks = <&iprocmed>; 450 clock-names = "iprocmed"; 451 num-cs = <2>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 455 spi_nor: spi-nor@0 { 456 compatible = "jedec,spi-nor"; 457 reg = <0>; 458 spi-max-frequency = <20000000>; 459 linux,part-probe = "ofpart", "bcm47xxpart"; 460 status = "disabled"; 461 }; 462 }; 463 464 thermal-zones { 465 cpu_thermal: cpu-thermal { 466 polling-delay-passive = <0>; 467 polling-delay = <1000>; 468 coefficients = <(-556) 418000>; 469 thermal-sensors = <&thermal>; 470 471 trips { 472 cpu-crit { 473 temperature = <125000>; 474 hysteresis = <0>; 475 type = "critical"; 476 }; 477 }; 478 479 cooling-maps { 480 }; 481 }; 482 }; 483}; 484