1/* 2 * Copyright 2012 DENX Software Engineering GmbH 3 * Heiko Schocher <hs@denx.de> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 */ 10#include "skeleton.dtsi" 11#include <dt-bindings/interrupt-controller/irq.h> 12 13/ { 14 arm { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 ranges; 18 intc: interrupt-controller@fffee000 { 19 compatible = "ti,cp-intc"; 20 interrupt-controller; 21 #interrupt-cells = <1>; 22 ti,intc-size = <101>; 23 reg = <0xfffee000 0x2000>; 24 }; 25 }; 26 soc@1c00000 { 27 compatible = "simple-bus"; 28 model = "da850"; 29 #address-cells = <1>; 30 #size-cells = <1>; 31 ranges = <0x0 0x01c00000 0x400000>; 32 interrupt-parent = <&intc>; 33 34 pmx_core: pinmux@14120 { 35 compatible = "pinctrl-single"; 36 reg = <0x14120 0x50>; 37 #pinctrl-cells = <2>; 38 pinctrl-single,bit-per-mux; 39 pinctrl-single,register-width = <32>; 40 pinctrl-single,function-mask = <0xf>; 41 status = "disabled"; 42 43 serial0_rtscts_pins: pinmux_serial0_rtscts_pins { 44 pinctrl-single,bits = < 45 /* UART0_RTS UART0_CTS */ 46 0x0c 0x22000000 0xff000000 47 >; 48 }; 49 serial0_rxtx_pins: pinmux_serial0_rxtx_pins { 50 pinctrl-single,bits = < 51 /* UART0_TXD UART0_RXD */ 52 0x0c 0x00220000 0x00ff0000 53 >; 54 }; 55 serial1_rtscts_pins: pinmux_serial1_rtscts_pins { 56 pinctrl-single,bits = < 57 /* UART1_CTS UART1_RTS */ 58 0x00 0x00440000 0x00ff0000 59 >; 60 }; 61 serial1_rxtx_pins: pinmux_serial1_rxtx_pins { 62 pinctrl-single,bits = < 63 /* UART1_TXD UART1_RXD */ 64 0x10 0x22000000 0xff000000 65 >; 66 }; 67 serial2_rtscts_pins: pinmux_serial2_rtscts_pins { 68 pinctrl-single,bits = < 69 /* UART2_CTS UART2_RTS */ 70 0x00 0x44000000 0xff000000 71 >; 72 }; 73 serial2_rxtx_pins: pinmux_serial2_rxtx_pins { 74 pinctrl-single,bits = < 75 /* UART2_TXD UART2_RXD */ 76 0x10 0x00220000 0x00ff0000 77 >; 78 }; 79 i2c0_pins: pinmux_i2c0_pins { 80 pinctrl-single,bits = < 81 /* I2C0_SDA,I2C0_SCL */ 82 0x10 0x00002200 0x0000ff00 83 >; 84 }; 85 i2c1_pins: pinmux_i2c1_pins { 86 pinctrl-single,bits = < 87 /* I2C1_SDA, I2C1_SCL */ 88 0x10 0x00440000 0x00ff0000 89 >; 90 }; 91 mmc0_pins: pinmux_mmc_pins { 92 pinctrl-single,bits = < 93 /* MMCSD0_DAT[3] MMCSD0_DAT[2] 94 * MMCSD0_DAT[1] MMCSD0_DAT[0] 95 * MMCSD0_CMD MMCSD0_CLK 96 */ 97 0x28 0x00222222 0x00ffffff 98 >; 99 }; 100 ehrpwm0a_pins: pinmux_ehrpwm0a_pins { 101 pinctrl-single,bits = < 102 /* EPWM0A */ 103 0xc 0x00000002 0x0000000f 104 >; 105 }; 106 ehrpwm0b_pins: pinmux_ehrpwm0b_pins { 107 pinctrl-single,bits = < 108 /* EPWM0B */ 109 0xc 0x00000020 0x000000f0 110 >; 111 }; 112 ehrpwm1a_pins: pinmux_ehrpwm1a_pins { 113 pinctrl-single,bits = < 114 /* EPWM1A */ 115 0x14 0x00000002 0x0000000f 116 >; 117 }; 118 ehrpwm1b_pins: pinmux_ehrpwm1b_pins { 119 pinctrl-single,bits = < 120 /* EPWM1B */ 121 0x14 0x00000020 0x000000f0 122 >; 123 }; 124 ecap0_pins: pinmux_ecap0_pins { 125 pinctrl-single,bits = < 126 /* ECAP0_APWM0 */ 127 0x8 0x20000000 0xf0000000 128 >; 129 }; 130 ecap1_pins: pinmux_ecap1_pins { 131 pinctrl-single,bits = < 132 /* ECAP1_APWM1 */ 133 0x4 0x40000000 0xf0000000 134 >; 135 }; 136 ecap2_pins: pinmux_ecap2_pins { 137 pinctrl-single,bits = < 138 /* ECAP2_APWM2 */ 139 0x4 0x00000004 0x0000000f 140 >; 141 }; 142 spi0_pins: pinmux_spi0_pins { 143 pinctrl-single,bits = < 144 /* SIMO, SOMI, CLK */ 145 0xc 0x00001101 0x0000ff0f 146 >; 147 }; 148 spi0_cs0_pin: pinmux_spi0_cs0 { 149 pinctrl-single,bits = < 150 /* CS0 */ 151 0x10 0x00000010 0x000000f0 152 >; 153 }; 154 spi0_cs3_pin: pinmux_spi0_cs3_pin { 155 pinctrl-single,bits = < 156 /* CS3 */ 157 0xc 0x01000000 0x0f000000 158 >; 159 }; 160 spi1_pins: pinmux_spi1_pins { 161 pinctrl-single,bits = < 162 /* SIMO, SOMI, CLK */ 163 0x14 0x00110100 0x00ff0f00 164 >; 165 }; 166 spi1_cs0_pin: pinmux_spi1_cs0 { 167 pinctrl-single,bits = < 168 /* CS0 */ 169 0x14 0x00000010 0x000000f0 170 >; 171 }; 172 mdio_pins: pinmux_mdio_pins { 173 pinctrl-single,bits = < 174 /* MDIO_CLK, MDIO_D */ 175 0x10 0x00000088 0x000000ff 176 >; 177 }; 178 mii_pins: pinmux_mii_pins { 179 pinctrl-single,bits = < 180 /* 181 * MII_TXEN, MII_TXCLK, MII_COL 182 * MII_TXD_3, MII_TXD_2, MII_TXD_1 183 * MII_TXD_0 184 */ 185 0x8 0x88888880 0xfffffff0 186 /* 187 * MII_RXER, MII_CRS, MII_RXCLK 188 * MII_RXDV, MII_RXD_3, MII_RXD_2 189 * MII_RXD_1, MII_RXD_0 190 */ 191 0xc 0x88888888 0xffffffff 192 >; 193 }; 194 lcd_pins: pinmux_lcd_pins { 195 pinctrl-single,bits = < 196 /* 197 * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5], 198 * LCD_D[6], LCD_D[7] 199 */ 200 0x40 0x22222200 0xffffff00 201 /* 202 * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13], 203 * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1] 204 */ 205 0x44 0x22222222 0xffffffff 206 /* LCD_D[8], LCD_D[9] */ 207 0x48 0x00000022 0x000000ff 208 209 /* LCD_PCLK */ 210 0x48 0x02000000 0x0f000000 211 /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */ 212 0x4c 0x02000022 0x0f0000ff 213 >; 214 }; 215 vpif_capture_pins: vpif_capture_pins { 216 pinctrl-single,bits = < 217 /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */ 218 0x38 0x11111111 0xffffffff 219 /* VP_DIN[10..15,0..1] */ 220 0x3c 0x11111111 0xffffffff 221 /* VP_DIN[8..9] */ 222 0x40 0x00000011 0x000000ff 223 >; 224 }; 225 vpif_display_pins: vpif_display_pins { 226 pinctrl-single,bits = < 227 /* VP_DOUT[2..7] */ 228 0x40 0x11111100 0xffffff00 229 /* VP_DOUT[10..15,0..1] */ 230 0x44 0x11111111 0xffffffff 231 /* VP_DOUT[8..9] */ 232 0x48 0x00000011 0x000000ff 233 /* 234 * VP_CLKOUT3, VP_CLKIN3, 235 * VP_CLKOUT2, VP_CLKIN2 236 */ 237 0x4c 0x00111100 0x00ffff00 238 >; 239 }; 240 }; 241 prictrl: priority-controller@14110 { 242 compatible = "ti,da850-mstpri"; 243 reg = <0x14110 0x0c>; 244 status = "disabled"; 245 }; 246 cfgchip: chip-controller@1417c { 247 compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; 248 reg = <0x1417c 0x14>; 249 250 usb_phy: usb-phy { 251 compatible = "ti,da830-usb-phy"; 252 #phy-cells = <1>; 253 status = "disabled"; 254 }; 255 }; 256 edma0: edma@0 { 257 compatible = "ti,edma3-tpcc"; 258 /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */ 259 reg = <0x0 0x8000>; 260 reg-names = "edma3_cc"; 261 interrupts = <11 12>; 262 interrupt-names = "edma3_ccint", "edma3_ccerrint"; 263 #dma-cells = <2>; 264 265 ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; 266 }; 267 edma0_tptc0: tptc@8000 { 268 compatible = "ti,edma3-tptc"; 269 reg = <0x8000 0x400>; 270 interrupts = <13>; 271 interrupt-names = "edm3_tcerrint"; 272 }; 273 edma0_tptc1: tptc@8400 { 274 compatible = "ti,edma3-tptc"; 275 reg = <0x8400 0x400>; 276 interrupts = <32>; 277 interrupt-names = "edm3_tcerrint"; 278 }; 279 edma1: edma@230000 { 280 compatible = "ti,edma3-tpcc"; 281 /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */ 282 reg = <0x230000 0x8000>; 283 reg-names = "edma3_cc"; 284 interrupts = <93 94>; 285 interrupt-names = "edma3_ccint", "edma3_ccerrint"; 286 #dma-cells = <2>; 287 288 ti,tptcs = <&edma1_tptc0 7>; 289 }; 290 edma1_tptc0: tptc@238000 { 291 compatible = "ti,edma3-tptc"; 292 reg = <0x238000 0x400>; 293 interrupts = <95>; 294 interrupt-names = "edm3_tcerrint"; 295 }; 296 serial0: serial@42000 { 297 compatible = "ti,da830-uart", "ns16550a"; 298 reg = <0x42000 0x100>; 299 reg-io-width = <4>; 300 reg-shift = <2>; 301 interrupts = <25>; 302 status = "disabled"; 303 }; 304 serial1: serial@10c000 { 305 compatible = "ti,da830-uart", "ns16550a"; 306 reg = <0x10c000 0x100>; 307 reg-io-width = <4>; 308 reg-shift = <2>; 309 interrupts = <53>; 310 status = "disabled"; 311 }; 312 serial2: serial@10d000 { 313 compatible = "ti,da830-uart", "ns16550a"; 314 reg = <0x10d000 0x100>; 315 reg-io-width = <4>; 316 reg-shift = <2>; 317 interrupts = <61>; 318 status = "disabled"; 319 }; 320 rtc0: rtc@23000 { 321 compatible = "ti,da830-rtc"; 322 reg = <0x23000 0x1000>; 323 interrupts = <19 324 19>; 325 status = "disabled"; 326 }; 327 i2c0: i2c@22000 { 328 compatible = "ti,davinci-i2c"; 329 reg = <0x22000 0x1000>; 330 interrupts = <15>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 status = "disabled"; 334 }; 335 i2c1: i2c@228000 { 336 compatible = "ti,davinci-i2c"; 337 reg = <0x228000 0x1000>; 338 interrupts = <51>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 status = "disabled"; 342 }; 343 wdt: wdt@21000 { 344 compatible = "ti,davinci-wdt"; 345 reg = <0x21000 0x1000>; 346 status = "disabled"; 347 }; 348 mmc0: mmc@40000 { 349 compatible = "ti,da830-mmc"; 350 reg = <0x40000 0x1000>; 351 cap-sd-highspeed; 352 cap-mmc-highspeed; 353 interrupts = <16>; 354 dmas = <&edma0 16 0>, <&edma0 17 0>; 355 dma-names = "rx", "tx"; 356 status = "disabled"; 357 }; 358 vpif: video@217000 { 359 compatible = "ti,da850-vpif"; 360 reg = <0x217000 0x1000>; 361 interrupts = <92>; 362 status = "disabled"; 363 364 /* VPIF capture port */ 365 port@0 { 366 #address-cells = <1>; 367 #size-cells = <0>; 368 }; 369 370 /* VPIF display port */ 371 port@1 { 372 #address-cells = <1>; 373 #size-cells = <0>; 374 }; 375 }; 376 mmc1: mmc@21b000 { 377 compatible = "ti,da830-mmc"; 378 reg = <0x21b000 0x1000>; 379 cap-sd-highspeed; 380 cap-mmc-highspeed; 381 interrupts = <72>; 382 dmas = <&edma1 28 0>, <&edma1 29 0>; 383 dma-names = "rx", "tx"; 384 status = "disabled"; 385 }; 386 ehrpwm0: pwm@300000 { 387 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", 388 "ti,am33xx-ehrpwm"; 389 #pwm-cells = <3>; 390 reg = <0x300000 0x2000>; 391 status = "disabled"; 392 }; 393 ehrpwm1: pwm@302000 { 394 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", 395 "ti,am33xx-ehrpwm"; 396 #pwm-cells = <3>; 397 reg = <0x302000 0x2000>; 398 status = "disabled"; 399 }; 400 ecap0: ecap@306000 { 401 compatible = "ti,da850-ecap", "ti,am3352-ecap", 402 "ti,am33xx-ecap"; 403 #pwm-cells = <3>; 404 reg = <0x306000 0x80>; 405 status = "disabled"; 406 }; 407 ecap1: ecap@307000 { 408 compatible = "ti,da850-ecap", "ti,am3352-ecap", 409 "ti,am33xx-ecap"; 410 #pwm-cells = <3>; 411 reg = <0x307000 0x80>; 412 status = "disabled"; 413 }; 414 ecap2: ecap@308000 { 415 compatible = "ti,da850-ecap", "ti,am3352-ecap", 416 "ti,am33xx-ecap"; 417 #pwm-cells = <3>; 418 reg = <0x308000 0x80>; 419 status = "disabled"; 420 }; 421 spi0: spi@41000 { 422 #address-cells = <1>; 423 #size-cells = <0>; 424 compatible = "ti,da830-spi"; 425 reg = <0x41000 0x1000>; 426 num-cs = <6>; 427 ti,davinci-spi-intr-line = <1>; 428 interrupts = <20>; 429 dmas = <&edma0 14 0>, <&edma0 15 0>; 430 dma-names = "rx", "tx"; 431 status = "disabled"; 432 }; 433 spi1: spi@30e000 { 434 #address-cells = <1>; 435 #size-cells = <0>; 436 compatible = "ti,da830-spi"; 437 reg = <0x30e000 0x1000>; 438 num-cs = <4>; 439 ti,davinci-spi-intr-line = <1>; 440 interrupts = <56>; 441 dmas = <&edma0 18 0>, <&edma0 19 0>; 442 dma-names = "rx", "tx"; 443 status = "disabled"; 444 }; 445 usb0: usb@200000 { 446 compatible = "ti,da830-musb"; 447 reg = <0x200000 0x1000>; 448 ranges; 449 interrupts = <58>; 450 interrupt-names = "mc"; 451 dr_mode = "otg"; 452 phys = <&usb_phy 0>; 453 phy-names = "usb-phy"; 454 status = "disabled"; 455 456 #address-cells = <1>; 457 #size-cells = <1>; 458 459 dmas = <&cppi41dma 0 0 &cppi41dma 1 0 460 &cppi41dma 2 0 &cppi41dma 3 0 461 &cppi41dma 0 1 &cppi41dma 1 1 462 &cppi41dma 2 1 &cppi41dma 3 1>; 463 dma-names = 464 "rx1", "rx2", "rx3", "rx4", 465 "tx1", "tx2", "tx3", "tx4"; 466 467 cppi41dma: dma-controller@201000 { 468 compatible = "ti,da830-cppi41"; 469 reg = <0x201000 0x1000 470 0x202000 0x1000 471 0x204000 0x4000>; 472 reg-names = "controller", 473 "scheduler", "queuemgr"; 474 interrupts = <58>; 475 #dma-cells = <2>; 476 #dma-channels = <4>; 477 status = "okay"; 478 }; 479 }; 480 sata: sata@218000 { 481 compatible = "ti,da850-ahci"; 482 reg = <0x218000 0x2000>, <0x22c018 0x4>; 483 interrupts = <67>; 484 status = "disabled"; 485 }; 486 mdio: mdio@224000 { 487 compatible = "ti,davinci_mdio"; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 reg = <0x224000 0x1000>; 491 status = "disabled"; 492 }; 493 eth0: ethernet@220000 { 494 compatible = "ti,davinci-dm6467-emac"; 495 reg = <0x220000 0x4000>; 496 ti,davinci-ctrl-reg-offset = <0x3000>; 497 ti,davinci-ctrl-mod-reg-offset = <0x2000>; 498 ti,davinci-ctrl-ram-offset = <0>; 499 ti,davinci-ctrl-ram-size = <0x2000>; 500 local-mac-address = [ 00 00 00 00 00 00 ]; 501 interrupts = <33 502 34 503 35 504 36 505 >; 506 status = "disabled"; 507 }; 508 usb1: usb@225000 { 509 compatible = "ti,da830-ohci"; 510 reg = <0x225000 0x1000>; 511 interrupts = <59>; 512 phys = <&usb_phy 1>; 513 phy-names = "usb-phy"; 514 status = "disabled"; 515 }; 516 gpio: gpio@226000 { 517 compatible = "ti,dm6441-gpio"; 518 gpio-controller; 519 #gpio-cells = <2>; 520 reg = <0x226000 0x1000>; 521 interrupts = <42 43 44 45 46 47 48 49 50>; 522 ti,ngpio = <144>; 523 ti,davinci-gpio-unbanked = <0>; 524 status = "disabled"; 525 interrupt-controller; 526 #interrupt-cells = <2>; 527 }; 528 pinconf: pin-controller@22c00c { 529 compatible = "ti,da850-pupd"; 530 reg = <0x22c00c 0x8>; 531 status = "disabled"; 532 }; 533 534 mcasp0: mcasp@100000 { 535 compatible = "ti,da830-mcasp-audio"; 536 reg = <0x100000 0x2000>, 537 <0x102000 0x400000>; 538 reg-names = "mpu", "dat"; 539 interrupts = <54>; 540 interrupt-names = "common"; 541 status = "disabled"; 542 dmas = <&edma0 1 1>, 543 <&edma0 0 1>; 544 dma-names = "tx", "rx"; 545 }; 546 547 lcdc: display@213000 { 548 compatible = "ti,da850-tilcdc"; 549 reg = <0x213000 0x1000>; 550 interrupts = <52>; 551 max-pixelclock = <37500>; 552 status = "disabled"; 553 }; 554 }; 555 aemif: aemif@68000000 { 556 compatible = "ti,da850-aemif"; 557 #address-cells = <2>; 558 #size-cells = <1>; 559 560 reg = <0x68000000 0x00008000>; 561 ranges = <0 0 0x60000000 0x08000000 562 1 0 0x68000000 0x00008000>; 563 status = "disabled"; 564 }; 565 memctrl: memory-controller@b0000000 { 566 compatible = "ti,da850-ddr-controller"; 567 reg = <0xb0000000 0xe8>; 568 status = "disabled"; 569 }; 570}; 571