1/* 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * Based on "omap4.dtsi" 8 */ 9 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/dra.h> 12 13#define MAX_SOURCES 400 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 compatible = "ti,dra7xx"; 20 interrupt-parent = <&crossbar_mpu>; 21 chosen { }; 22 23 aliases { 24 i2c0 = &i2c1; 25 i2c1 = &i2c2; 26 i2c2 = &i2c3; 27 i2c3 = &i2c4; 28 i2c4 = &i2c5; 29 serial0 = &uart1; 30 serial1 = &uart2; 31 serial2 = &uart3; 32 serial3 = &uart4; 33 serial4 = &uart5; 34 serial5 = &uart6; 35 serial6 = &uart7; 36 serial7 = &uart8; 37 serial8 = &uart9; 38 serial9 = &uart10; 39 ethernet0 = &cpsw_emac0; 40 ethernet1 = &cpsw_emac1; 41 d_can0 = &dcan1; 42 d_can1 = &dcan2; 43 spi0 = &qspi; 44 }; 45 46 timer { 47 compatible = "arm,armv7-timer"; 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 52 interrupt-parent = <&gic>; 53 }; 54 55 gic: interrupt-controller@48211000 { 56 compatible = "arm,cortex-a15-gic"; 57 interrupt-controller; 58 #interrupt-cells = <3>; 59 reg = <0x0 0x48211000 0x0 0x1000>, 60 <0x0 0x48212000 0x0 0x2000>, 61 <0x0 0x48214000 0x0 0x2000>, 62 <0x0 0x48216000 0x0 0x2000>; 63 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 64 interrupt-parent = <&gic>; 65 }; 66 67 wakeupgen: interrupt-controller@48281000 { 68 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 69 interrupt-controller; 70 #interrupt-cells = <3>; 71 reg = <0x0 0x48281000 0x0 0x1000>; 72 interrupt-parent = <&gic>; 73 }; 74 75 cpus { 76 #address-cells = <1>; 77 #size-cells = <0>; 78 79 cpu0: cpu@0 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a15"; 82 reg = <0>; 83 84 operating-points-v2 = <&cpu0_opp_table>; 85 86 clocks = <&dpll_mpu_ck>; 87 clock-names = "cpu"; 88 89 clock-latency = <300000>; /* From omap-cpufreq driver */ 90 91 /* cooling options */ 92 cooling-min-level = <0>; 93 cooling-max-level = <2>; 94 #cooling-cells = <2>; /* min followed by max */ 95 }; 96 }; 97 98 cpu0_opp_table: opp-table { 99 compatible = "operating-points-v2-ti-cpu"; 100 syscon = <&scm_wkup>; 101 102 opp_nom-1000000000 { 103 opp-hz = /bits/ 64 <1000000000>; 104 opp-microvolt = <1060000 850000 1150000>; 105 opp-supported-hw = <0xFF 0x01>; 106 opp-suspend; 107 }; 108 109 opp_od-1176000000 { 110 opp-hz = /bits/ 64 <1176000000>; 111 opp-microvolt = <1160000 885000 1160000>; 112 opp-supported-hw = <0xFF 0x02>; 113 }; 114 }; 115 116 /* 117 * The soc node represents the soc top level view. It is used for IPs 118 * that are not memory mapped in the MPU view or for the MPU itself. 119 */ 120 soc { 121 compatible = "ti,omap-infra"; 122 mpu { 123 compatible = "ti,omap5-mpu"; 124 ti,hwmods = "mpu"; 125 }; 126 }; 127 128 /* 129 * XXX: Use a flat representation of the SOC interconnect. 130 * The real OMAP interconnect network is quite complex. 131 * Since it will not bring real advantage to represent that in DT for 132 * the moment, just use a fake OCP bus entry to represent the whole bus 133 * hierarchy. 134 */ 135 ocp { 136 compatible = "ti,dra7-l3-noc", "simple-bus"; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 ranges = <0x0 0x0 0x0 0xc0000000>; 140 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; 141 ti,hwmods = "l3_main_1", "l3_main_2"; 142 reg = <0x0 0x44000000 0x0 0x1000000>, 143 <0x0 0x45000000 0x0 0x1000>; 144 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 145 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 146 147 l4_cfg: l4@4a000000 { 148 compatible = "ti,dra7-l4-cfg", "simple-bus"; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 ranges = <0 0x4a000000 0x22c000>; 152 153 scm: scm@2000 { 154 compatible = "ti,dra7-scm-core", "simple-bus"; 155 reg = <0x2000 0x2000>; 156 #address-cells = <1>; 157 #size-cells = <1>; 158 ranges = <0 0x2000 0x2000>; 159 160 scm_conf: scm_conf@0 { 161 compatible = "syscon", "simple-bus"; 162 reg = <0x0 0x1400>; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 ranges = <0 0x0 0x1400>; 166 167 pbias_regulator: pbias_regulator@e00 { 168 compatible = "ti,pbias-dra7", "ti,pbias-omap"; 169 reg = <0xe00 0x4>; 170 syscon = <&scm_conf>; 171 pbias_mmc_reg: pbias_mmc_omap5 { 172 regulator-name = "pbias_mmc_omap5"; 173 regulator-min-microvolt = <1800000>; 174 regulator-max-microvolt = <3000000>; 175 }; 176 }; 177 178 scm_conf_clocks: clocks { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 }; 182 }; 183 184 dra7_pmx_core: pinmux@1400 { 185 compatible = "ti,dra7-padconf", 186 "pinctrl-single"; 187 reg = <0x1400 0x0468>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 #pinctrl-cells = <1>; 191 #interrupt-cells = <1>; 192 interrupt-controller; 193 pinctrl-single,register-width = <32>; 194 pinctrl-single,function-mask = <0x3fffffff>; 195 }; 196 197 scm_conf1: scm_conf@1c04 { 198 compatible = "syscon"; 199 reg = <0x1c04 0x0020>; 200 #syscon-cells = <2>; 201 }; 202 203 scm_conf_pcie: scm_conf@1c24 { 204 compatible = "syscon"; 205 reg = <0x1c24 0x0024>; 206 }; 207 208 sdma_xbar: dma-router@b78 { 209 compatible = "ti,dra7-dma-crossbar"; 210 reg = <0xb78 0xfc>; 211 #dma-cells = <1>; 212 dma-requests = <205>; 213 ti,dma-safe-map = <0>; 214 dma-masters = <&sdma>; 215 }; 216 217 edma_xbar: dma-router@c78 { 218 compatible = "ti,dra7-dma-crossbar"; 219 reg = <0xc78 0x7c>; 220 #dma-cells = <2>; 221 dma-requests = <204>; 222 ti,dma-safe-map = <0>; 223 dma-masters = <&edma>; 224 }; 225 }; 226 227 cm_core_aon: cm_core_aon@5000 { 228 compatible = "ti,dra7-cm-core-aon"; 229 reg = <0x5000 0x2000>; 230 231 cm_core_aon_clocks: clocks { 232 #address-cells = <1>; 233 #size-cells = <0>; 234 }; 235 236 cm_core_aon_clockdomains: clockdomains { 237 }; 238 }; 239 240 cm_core: cm_core@8000 { 241 compatible = "ti,dra7-cm-core"; 242 reg = <0x8000 0x3000>; 243 244 cm_core_clocks: clocks { 245 #address-cells = <1>; 246 #size-cells = <0>; 247 }; 248 249 cm_core_clockdomains: clockdomains { 250 }; 251 }; 252 }; 253 254 l4_wkup: l4@4ae00000 { 255 compatible = "ti,dra7-l4-wkup", "simple-bus"; 256 #address-cells = <1>; 257 #size-cells = <1>; 258 ranges = <0 0x4ae00000 0x3f000>; 259 260 counter32k: counter@4000 { 261 compatible = "ti,omap-counter32k"; 262 reg = <0x4000 0x40>; 263 ti,hwmods = "counter_32k"; 264 }; 265 266 prm: prm@6000 { 267 compatible = "ti,dra7-prm"; 268 reg = <0x6000 0x3000>; 269 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 270 271 prm_clocks: clocks { 272 #address-cells = <1>; 273 #size-cells = <0>; 274 }; 275 276 prm_clockdomains: clockdomains { 277 }; 278 }; 279 280 scm_wkup: scm_conf@c000 { 281 compatible = "syscon"; 282 reg = <0xc000 0x1000>; 283 }; 284 }; 285 286 axi@0 { 287 compatible = "simple-bus"; 288 #size-cells = <1>; 289 #address-cells = <1>; 290 ranges = <0x51000000 0x51000000 0x3000 291 0x0 0x20000000 0x10000000>; 292 /** 293 * To enable PCI endpoint mode, disable the pcie1_rc 294 * node and enable pcie1_ep mode. 295 */ 296 pcie1_rc: pcie@51000000 { 297 compatible = "ti,dra7-pcie"; 298 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; 299 reg-names = "rc_dbics", "ti_conf", "config"; 300 interrupts = <0 232 0x4>, <0 233 0x4>; 301 #address-cells = <3>; 302 #size-cells = <2>; 303 device_type = "pci"; 304 ranges = <0x81000000 0 0 0x03000 0 0x00010000 305 0x82000000 0 0x20013000 0x13000 0 0xffed000>; 306 dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>; 307 bus-range = <0x00 0xff>; 308 #interrupt-cells = <1>; 309 num-lanes = <1>; 310 linux,pci-domain = <0>; 311 ti,hwmods = "pcie1"; 312 phys = <&pcie1_phy>; 313 phy-names = "pcie-phy0"; 314 interrupt-map-mask = <0 0 0 7>; 315 interrupt-map = <0 0 0 1 &pcie1_intc 1>, 316 <0 0 0 2 &pcie1_intc 2>, 317 <0 0 0 3 &pcie1_intc 3>, 318 <0 0 0 4 &pcie1_intc 4>; 319 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; 320 status = "disabled"; 321 pcie1_intc: interrupt-controller { 322 interrupt-controller; 323 #address-cells = <0>; 324 #interrupt-cells = <1>; 325 }; 326 }; 327 328 pcie1_ep: pcie_ep@51000000 { 329 compatible = "ti,dra7-pcie-ep"; 330 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; 331 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; 332 interrupts = <0 232 0x4>; 333 num-lanes = <1>; 334 num-ib-windows = <4>; 335 num-ob-windows = <16>; 336 ti,hwmods = "pcie1"; 337 phys = <&pcie1_phy>; 338 phy-names = "pcie-phy0"; 339 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; 340 status = "disabled"; 341 }; 342 }; 343 344 axi@1 { 345 compatible = "simple-bus"; 346 #size-cells = <1>; 347 #address-cells = <1>; 348 ranges = <0x51800000 0x51800000 0x3000 349 0x0 0x30000000 0x10000000>; 350 status = "disabled"; 351 pcie@51800000 { 352 compatible = "ti,dra7-pcie"; 353 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; 354 reg-names = "rc_dbics", "ti_conf", "config"; 355 interrupts = <0 355 0x4>, <0 356 0x4>; 356 #address-cells = <3>; 357 #size-cells = <2>; 358 device_type = "pci"; 359 ranges = <0x81000000 0 0 0x03000 0 0x00010000 360 0x82000000 0 0x30013000 0x13000 0 0xffed000>; 361 dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>; 362 bus-range = <0x00 0xff>; 363 #interrupt-cells = <1>; 364 num-lanes = <1>; 365 linux,pci-domain = <1>; 366 ti,hwmods = "pcie2"; 367 phys = <&pcie2_phy>; 368 phy-names = "pcie-phy0"; 369 interrupt-map-mask = <0 0 0 7>; 370 interrupt-map = <0 0 0 1 &pcie2_intc 1>, 371 <0 0 0 2 &pcie2_intc 2>, 372 <0 0 0 3 &pcie2_intc 3>, 373 <0 0 0 4 &pcie2_intc 4>; 374 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; 375 pcie2_intc: interrupt-controller { 376 interrupt-controller; 377 #address-cells = <0>; 378 #interrupt-cells = <1>; 379 }; 380 }; 381 }; 382 383 ocmcram1: ocmcram@40300000 { 384 compatible = "mmio-sram"; 385 reg = <0x40300000 0x80000>; 386 ranges = <0x0 0x40300000 0x80000>; 387 #address-cells = <1>; 388 #size-cells = <1>; 389 /* 390 * This is a placeholder for an optional reserved 391 * region for use by secure software. The size 392 * of this region is not known until runtime so it 393 * is set as zero to either be updated to reserve 394 * space or left unchanged to leave all SRAM for use. 395 * On HS parts that that require the reserved region 396 * either the bootloader can update the size to 397 * the required amount or the node can be overridden 398 * from the board dts file for the secure platform. 399 */ 400 sram-hs@0 { 401 compatible = "ti,secure-ram"; 402 reg = <0x0 0x0>; 403 }; 404 }; 405 406 /* 407 * NOTE: ocmcram2 and ocmcram3 are not available on all 408 * DRA7xx and AM57xx variants. Confirm availability in 409 * the data manual for the exact part number in use 410 * before enabling these nodes in the board dts file. 411 */ 412 ocmcram2: ocmcram@40400000 { 413 status = "disabled"; 414 compatible = "mmio-sram"; 415 reg = <0x40400000 0x100000>; 416 ranges = <0x0 0x40400000 0x100000>; 417 #address-cells = <1>; 418 #size-cells = <1>; 419 }; 420 421 ocmcram3: ocmcram@40500000 { 422 status = "disabled"; 423 compatible = "mmio-sram"; 424 reg = <0x40500000 0x100000>; 425 ranges = <0x0 0x40500000 0x100000>; 426 #address-cells = <1>; 427 #size-cells = <1>; 428 }; 429 430 bandgap: bandgap@4a0021e0 { 431 reg = <0x4a0021e0 0xc 432 0x4a00232c 0xc 433 0x4a002380 0x2c 434 0x4a0023C0 0x3c 435 0x4a002564 0x8 436 0x4a002574 0x50>; 437 compatible = "ti,dra752-bandgap"; 438 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 439 #thermal-sensor-cells = <1>; 440 }; 441 442 dsp1_system: dsp_system@40d00000 { 443 compatible = "syscon"; 444 reg = <0x40d00000 0x100>; 445 }; 446 447 dra7_iodelay_core: padconf@4844a000 { 448 compatible = "ti,dra7-iodelay"; 449 reg = <0x4844a000 0x0d1c>; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 #pinctrl-cells = <2>; 453 }; 454 455 sdma: dma-controller@4a056000 { 456 compatible = "ti,omap4430-sdma"; 457 reg = <0x4a056000 0x1000>; 458 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 462 #dma-cells = <1>; 463 dma-channels = <32>; 464 dma-requests = <127>; 465 }; 466 467 edma: edma@43300000 { 468 compatible = "ti,edma3-tpcc"; 469 ti,hwmods = "tpcc"; 470 reg = <0x43300000 0x100000>; 471 reg-names = "edma3_cc"; 472 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 475 interrupt-names = "edma3_ccint", "edma3_mperr", 476 "edma3_ccerrint"; 477 dma-requests = <64>; 478 #dma-cells = <2>; 479 480 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; 481 482 /* 483 * memcpy is disabled, can be enabled with: 484 * ti,edma-memcpy-channels = <20 21>; 485 * for example. Note that these channels need to be 486 * masked in the xbar as well. 487 */ 488 }; 489 490 edma_tptc0: tptc@43400000 { 491 compatible = "ti,edma3-tptc"; 492 ti,hwmods = "tptc0"; 493 reg = <0x43400000 0x100000>; 494 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 495 interrupt-names = "edma3_tcerrint"; 496 }; 497 498 edma_tptc1: tptc@43500000 { 499 compatible = "ti,edma3-tptc"; 500 ti,hwmods = "tptc1"; 501 reg = <0x43500000 0x100000>; 502 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 503 interrupt-names = "edma3_tcerrint"; 504 }; 505 506 gpio1: gpio@4ae10000 { 507 compatible = "ti,omap4-gpio"; 508 reg = <0x4ae10000 0x200>; 509 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 510 ti,hwmods = "gpio1"; 511 gpio-controller; 512 #gpio-cells = <2>; 513 interrupt-controller; 514 #interrupt-cells = <2>; 515 }; 516 517 gpio2: gpio@48055000 { 518 compatible = "ti,omap4-gpio"; 519 reg = <0x48055000 0x200>; 520 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 521 ti,hwmods = "gpio2"; 522 gpio-controller; 523 #gpio-cells = <2>; 524 interrupt-controller; 525 #interrupt-cells = <2>; 526 }; 527 528 gpio3: gpio@48057000 { 529 compatible = "ti,omap4-gpio"; 530 reg = <0x48057000 0x200>; 531 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 532 ti,hwmods = "gpio3"; 533 gpio-controller; 534 #gpio-cells = <2>; 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 }; 538 539 gpio4: gpio@48059000 { 540 compatible = "ti,omap4-gpio"; 541 reg = <0x48059000 0x200>; 542 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 543 ti,hwmods = "gpio4"; 544 gpio-controller; 545 #gpio-cells = <2>; 546 interrupt-controller; 547 #interrupt-cells = <2>; 548 }; 549 550 gpio5: gpio@4805b000 { 551 compatible = "ti,omap4-gpio"; 552 reg = <0x4805b000 0x200>; 553 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 554 ti,hwmods = "gpio5"; 555 gpio-controller; 556 #gpio-cells = <2>; 557 interrupt-controller; 558 #interrupt-cells = <2>; 559 }; 560 561 gpio6: gpio@4805d000 { 562 compatible = "ti,omap4-gpio"; 563 reg = <0x4805d000 0x200>; 564 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 565 ti,hwmods = "gpio6"; 566 gpio-controller; 567 #gpio-cells = <2>; 568 interrupt-controller; 569 #interrupt-cells = <2>; 570 }; 571 572 gpio7: gpio@48051000 { 573 compatible = "ti,omap4-gpio"; 574 reg = <0x48051000 0x200>; 575 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 576 ti,hwmods = "gpio7"; 577 gpio-controller; 578 #gpio-cells = <2>; 579 interrupt-controller; 580 #interrupt-cells = <2>; 581 }; 582 583 gpio8: gpio@48053000 { 584 compatible = "ti,omap4-gpio"; 585 reg = <0x48053000 0x200>; 586 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 587 ti,hwmods = "gpio8"; 588 gpio-controller; 589 #gpio-cells = <2>; 590 interrupt-controller; 591 #interrupt-cells = <2>; 592 }; 593 594 uart1: serial@4806a000 { 595 compatible = "ti,dra742-uart", "ti,omap4-uart"; 596 reg = <0x4806a000 0x100>; 597 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 598 ti,hwmods = "uart1"; 599 clock-frequency = <48000000>; 600 status = "disabled"; 601 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; 602 dma-names = "tx", "rx"; 603 }; 604 605 uart2: serial@4806c000 { 606 compatible = "ti,dra742-uart", "ti,omap4-uart"; 607 reg = <0x4806c000 0x100>; 608 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 609 ti,hwmods = "uart2"; 610 clock-frequency = <48000000>; 611 status = "disabled"; 612 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; 613 dma-names = "tx", "rx"; 614 }; 615 616 uart3: serial@48020000 { 617 compatible = "ti,dra742-uart", "ti,omap4-uart"; 618 reg = <0x48020000 0x100>; 619 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 620 ti,hwmods = "uart3"; 621 clock-frequency = <48000000>; 622 status = "disabled"; 623 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; 624 dma-names = "tx", "rx"; 625 }; 626 627 uart4: serial@4806e000 { 628 compatible = "ti,dra742-uart", "ti,omap4-uart"; 629 reg = <0x4806e000 0x100>; 630 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 631 ti,hwmods = "uart4"; 632 clock-frequency = <48000000>; 633 status = "disabled"; 634 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; 635 dma-names = "tx", "rx"; 636 }; 637 638 uart5: serial@48066000 { 639 compatible = "ti,dra742-uart", "ti,omap4-uart"; 640 reg = <0x48066000 0x100>; 641 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 642 ti,hwmods = "uart5"; 643 clock-frequency = <48000000>; 644 status = "disabled"; 645 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; 646 dma-names = "tx", "rx"; 647 }; 648 649 uart6: serial@48068000 { 650 compatible = "ti,dra742-uart", "ti,omap4-uart"; 651 reg = <0x48068000 0x100>; 652 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 653 ti,hwmods = "uart6"; 654 clock-frequency = <48000000>; 655 status = "disabled"; 656 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; 657 dma-names = "tx", "rx"; 658 }; 659 660 uart7: serial@48420000 { 661 compatible = "ti,dra742-uart", "ti,omap4-uart"; 662 reg = <0x48420000 0x100>; 663 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 664 ti,hwmods = "uart7"; 665 clock-frequency = <48000000>; 666 status = "disabled"; 667 }; 668 669 uart8: serial@48422000 { 670 compatible = "ti,dra742-uart", "ti,omap4-uart"; 671 reg = <0x48422000 0x100>; 672 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 673 ti,hwmods = "uart8"; 674 clock-frequency = <48000000>; 675 status = "disabled"; 676 }; 677 678 uart9: serial@48424000 { 679 compatible = "ti,dra742-uart", "ti,omap4-uart"; 680 reg = <0x48424000 0x100>; 681 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 682 ti,hwmods = "uart9"; 683 clock-frequency = <48000000>; 684 status = "disabled"; 685 }; 686 687 uart10: serial@4ae2b000 { 688 compatible = "ti,dra742-uart", "ti,omap4-uart"; 689 reg = <0x4ae2b000 0x100>; 690 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 691 ti,hwmods = "uart10"; 692 clock-frequency = <48000000>; 693 status = "disabled"; 694 }; 695 696 mailbox1: mailbox@4a0f4000 { 697 compatible = "ti,omap4-mailbox"; 698 reg = <0x4a0f4000 0x200>; 699 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 702 ti,hwmods = "mailbox1"; 703 #mbox-cells = <1>; 704 ti,mbox-num-users = <3>; 705 ti,mbox-num-fifos = <8>; 706 status = "disabled"; 707 }; 708 709 mailbox2: mailbox@4883a000 { 710 compatible = "ti,omap4-mailbox"; 711 reg = <0x4883a000 0x200>; 712 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 716 ti,hwmods = "mailbox2"; 717 #mbox-cells = <1>; 718 ti,mbox-num-users = <4>; 719 ti,mbox-num-fifos = <12>; 720 status = "disabled"; 721 }; 722 723 mailbox3: mailbox@4883c000 { 724 compatible = "ti,omap4-mailbox"; 725 reg = <0x4883c000 0x200>; 726 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 730 ti,hwmods = "mailbox3"; 731 #mbox-cells = <1>; 732 ti,mbox-num-users = <4>; 733 ti,mbox-num-fifos = <12>; 734 status = "disabled"; 735 }; 736 737 mailbox4: mailbox@4883e000 { 738 compatible = "ti,omap4-mailbox"; 739 reg = <0x4883e000 0x200>; 740 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 744 ti,hwmods = "mailbox4"; 745 #mbox-cells = <1>; 746 ti,mbox-num-users = <4>; 747 ti,mbox-num-fifos = <12>; 748 status = "disabled"; 749 }; 750 751 mailbox5: mailbox@48840000 { 752 compatible = "ti,omap4-mailbox"; 753 reg = <0x48840000 0x200>; 754 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 758 ti,hwmods = "mailbox5"; 759 #mbox-cells = <1>; 760 ti,mbox-num-users = <4>; 761 ti,mbox-num-fifos = <12>; 762 status = "disabled"; 763 }; 764 765 mailbox6: mailbox@48842000 { 766 compatible = "ti,omap4-mailbox"; 767 reg = <0x48842000 0x200>; 768 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 772 ti,hwmods = "mailbox6"; 773 #mbox-cells = <1>; 774 ti,mbox-num-users = <4>; 775 ti,mbox-num-fifos = <12>; 776 status = "disabled"; 777 }; 778 779 mailbox7: mailbox@48844000 { 780 compatible = "ti,omap4-mailbox"; 781 reg = <0x48844000 0x200>; 782 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 786 ti,hwmods = "mailbox7"; 787 #mbox-cells = <1>; 788 ti,mbox-num-users = <4>; 789 ti,mbox-num-fifos = <12>; 790 status = "disabled"; 791 }; 792 793 mailbox8: mailbox@48846000 { 794 compatible = "ti,omap4-mailbox"; 795 reg = <0x48846000 0x200>; 796 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 800 ti,hwmods = "mailbox8"; 801 #mbox-cells = <1>; 802 ti,mbox-num-users = <4>; 803 ti,mbox-num-fifos = <12>; 804 status = "disabled"; 805 }; 806 807 mailbox9: mailbox@4885e000 { 808 compatible = "ti,omap4-mailbox"; 809 reg = <0x4885e000 0x200>; 810 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 814 ti,hwmods = "mailbox9"; 815 #mbox-cells = <1>; 816 ti,mbox-num-users = <4>; 817 ti,mbox-num-fifos = <12>; 818 status = "disabled"; 819 }; 820 821 mailbox10: mailbox@48860000 { 822 compatible = "ti,omap4-mailbox"; 823 reg = <0x48860000 0x200>; 824 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 828 ti,hwmods = "mailbox10"; 829 #mbox-cells = <1>; 830 ti,mbox-num-users = <4>; 831 ti,mbox-num-fifos = <12>; 832 status = "disabled"; 833 }; 834 835 mailbox11: mailbox@48862000 { 836 compatible = "ti,omap4-mailbox"; 837 reg = <0x48862000 0x200>; 838 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 842 ti,hwmods = "mailbox11"; 843 #mbox-cells = <1>; 844 ti,mbox-num-users = <4>; 845 ti,mbox-num-fifos = <12>; 846 status = "disabled"; 847 }; 848 849 mailbox12: mailbox@48864000 { 850 compatible = "ti,omap4-mailbox"; 851 reg = <0x48864000 0x200>; 852 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 856 ti,hwmods = "mailbox12"; 857 #mbox-cells = <1>; 858 ti,mbox-num-users = <4>; 859 ti,mbox-num-fifos = <12>; 860 status = "disabled"; 861 }; 862 863 mailbox13: mailbox@48802000 { 864 compatible = "ti,omap4-mailbox"; 865 reg = <0x48802000 0x200>; 866 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; 870 ti,hwmods = "mailbox13"; 871 #mbox-cells = <1>; 872 ti,mbox-num-users = <4>; 873 ti,mbox-num-fifos = <12>; 874 status = "disabled"; 875 }; 876 877 timer1: timer@4ae18000 { 878 compatible = "ti,omap5430-timer"; 879 reg = <0x4ae18000 0x80>; 880 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 881 ti,hwmods = "timer1"; 882 ti,timer-alwon; 883 }; 884 885 timer2: timer@48032000 { 886 compatible = "ti,omap5430-timer"; 887 reg = <0x48032000 0x80>; 888 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 889 ti,hwmods = "timer2"; 890 }; 891 892 timer3: timer@48034000 { 893 compatible = "ti,omap5430-timer"; 894 reg = <0x48034000 0x80>; 895 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 896 ti,hwmods = "timer3"; 897 }; 898 899 timer4: timer@48036000 { 900 compatible = "ti,omap5430-timer"; 901 reg = <0x48036000 0x80>; 902 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 903 ti,hwmods = "timer4"; 904 }; 905 906 timer5: timer@48820000 { 907 compatible = "ti,omap5430-timer"; 908 reg = <0x48820000 0x80>; 909 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 910 ti,hwmods = "timer5"; 911 }; 912 913 timer6: timer@48822000 { 914 compatible = "ti,omap5430-timer"; 915 reg = <0x48822000 0x80>; 916 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 917 ti,hwmods = "timer6"; 918 }; 919 920 timer7: timer@48824000 { 921 compatible = "ti,omap5430-timer"; 922 reg = <0x48824000 0x80>; 923 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 924 ti,hwmods = "timer7"; 925 }; 926 927 timer8: timer@48826000 { 928 compatible = "ti,omap5430-timer"; 929 reg = <0x48826000 0x80>; 930 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 931 ti,hwmods = "timer8"; 932 }; 933 934 timer9: timer@4803e000 { 935 compatible = "ti,omap5430-timer"; 936 reg = <0x4803e000 0x80>; 937 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 938 ti,hwmods = "timer9"; 939 }; 940 941 timer10: timer@48086000 { 942 compatible = "ti,omap5430-timer"; 943 reg = <0x48086000 0x80>; 944 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 945 ti,hwmods = "timer10"; 946 }; 947 948 timer11: timer@48088000 { 949 compatible = "ti,omap5430-timer"; 950 reg = <0x48088000 0x80>; 951 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 952 ti,hwmods = "timer11"; 953 }; 954 955 timer12: timer@4ae20000 { 956 compatible = "ti,omap5430-timer"; 957 reg = <0x4ae20000 0x80>; 958 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 959 ti,hwmods = "timer12"; 960 ti,timer-alwon; 961 ti,timer-secure; 962 }; 963 964 timer13: timer@48828000 { 965 compatible = "ti,omap5430-timer"; 966 reg = <0x48828000 0x80>; 967 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 968 ti,hwmods = "timer13"; 969 }; 970 971 timer14: timer@4882a000 { 972 compatible = "ti,omap5430-timer"; 973 reg = <0x4882a000 0x80>; 974 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 975 ti,hwmods = "timer14"; 976 }; 977 978 timer15: timer@4882c000 { 979 compatible = "ti,omap5430-timer"; 980 reg = <0x4882c000 0x80>; 981 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 982 ti,hwmods = "timer15"; 983 }; 984 985 timer16: timer@4882e000 { 986 compatible = "ti,omap5430-timer"; 987 reg = <0x4882e000 0x80>; 988 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 989 ti,hwmods = "timer16"; 990 }; 991 992 wdt2: wdt@4ae14000 { 993 compatible = "ti,omap3-wdt"; 994 reg = <0x4ae14000 0x80>; 995 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 996 ti,hwmods = "wd_timer2"; 997 }; 998 999 hwspinlock: spinlock@4a0f6000 { 1000 compatible = "ti,omap4-hwspinlock"; 1001 reg = <0x4a0f6000 0x1000>; 1002 ti,hwmods = "spinlock"; 1003 #hwlock-cells = <1>; 1004 }; 1005 1006 dmm@4e000000 { 1007 compatible = "ti,omap5-dmm"; 1008 reg = <0x4e000000 0x800>; 1009 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1010 ti,hwmods = "dmm"; 1011 }; 1012 1013 i2c1: i2c@48070000 { 1014 compatible = "ti,omap4-i2c"; 1015 reg = <0x48070000 0x100>; 1016 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 ti,hwmods = "i2c1"; 1020 status = "disabled"; 1021 }; 1022 1023 i2c2: i2c@48072000 { 1024 compatible = "ti,omap4-i2c"; 1025 reg = <0x48072000 0x100>; 1026 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 ti,hwmods = "i2c2"; 1030 status = "disabled"; 1031 }; 1032 1033 i2c3: i2c@48060000 { 1034 compatible = "ti,omap4-i2c"; 1035 reg = <0x48060000 0x100>; 1036 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 ti,hwmods = "i2c3"; 1040 status = "disabled"; 1041 }; 1042 1043 i2c4: i2c@4807a000 { 1044 compatible = "ti,omap4-i2c"; 1045 reg = <0x4807a000 0x100>; 1046 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 ti,hwmods = "i2c4"; 1050 status = "disabled"; 1051 }; 1052 1053 i2c5: i2c@4807c000 { 1054 compatible = "ti,omap4-i2c"; 1055 reg = <0x4807c000 0x100>; 1056 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 ti,hwmods = "i2c5"; 1060 status = "disabled"; 1061 }; 1062 1063 mmc1: mmc@4809c000 { 1064 compatible = "ti,omap4-hsmmc"; 1065 reg = <0x4809c000 0x400>; 1066 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1067 ti,hwmods = "mmc1"; 1068 ti,dual-volt; 1069 ti,needs-special-reset; 1070 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>; 1071 dma-names = "tx", "rx"; 1072 status = "disabled"; 1073 pbias-supply = <&pbias_mmc_reg>; 1074 max-frequency = <192000000>; 1075 }; 1076 1077 mmc2: mmc@480b4000 { 1078 compatible = "ti,omap4-hsmmc"; 1079 reg = <0x480b4000 0x400>; 1080 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1081 ti,hwmods = "mmc2"; 1082 ti,needs-special-reset; 1083 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; 1084 dma-names = "tx", "rx"; 1085 status = "disabled"; 1086 max-frequency = <192000000>; 1087 }; 1088 1089 mmc3: mmc@480ad000 { 1090 compatible = "ti,omap4-hsmmc"; 1091 reg = <0x480ad000 0x400>; 1092 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1093 ti,hwmods = "mmc3"; 1094 ti,needs-special-reset; 1095 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; 1096 dma-names = "tx", "rx"; 1097 status = "disabled"; 1098 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ 1099 max-frequency = <64000000>; 1100 }; 1101 1102 mmc4: mmc@480d1000 { 1103 compatible = "ti,omap4-hsmmc"; 1104 reg = <0x480d1000 0x400>; 1105 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1106 ti,hwmods = "mmc4"; 1107 ti,needs-special-reset; 1108 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; 1109 dma-names = "tx", "rx"; 1110 status = "disabled"; 1111 max-frequency = <192000000>; 1112 }; 1113 1114 mmu0_dsp1: mmu@40d01000 { 1115 compatible = "ti,dra7-dsp-iommu"; 1116 reg = <0x40d01000 0x100>; 1117 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1118 ti,hwmods = "mmu0_dsp1"; 1119 #iommu-cells = <0>; 1120 ti,syscon-mmuconfig = <&dsp1_system 0x0>; 1121 status = "disabled"; 1122 }; 1123 1124 mmu1_dsp1: mmu@40d02000 { 1125 compatible = "ti,dra7-dsp-iommu"; 1126 reg = <0x40d02000 0x100>; 1127 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1128 ti,hwmods = "mmu1_dsp1"; 1129 #iommu-cells = <0>; 1130 ti,syscon-mmuconfig = <&dsp1_system 0x1>; 1131 status = "disabled"; 1132 }; 1133 1134 mmu_ipu1: mmu@58882000 { 1135 compatible = "ti,dra7-iommu"; 1136 reg = <0x58882000 0x100>; 1137 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; 1138 ti,hwmods = "mmu_ipu1"; 1139 #iommu-cells = <0>; 1140 ti,iommu-bus-err-back; 1141 status = "disabled"; 1142 }; 1143 1144 mmu_ipu2: mmu@55082000 { 1145 compatible = "ti,dra7-iommu"; 1146 reg = <0x55082000 0x100>; 1147 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 1148 ti,hwmods = "mmu_ipu2"; 1149 #iommu-cells = <0>; 1150 ti,iommu-bus-err-back; 1151 status = "disabled"; 1152 }; 1153 1154 abb_mpu: regulator-abb-mpu { 1155 compatible = "ti,abb-v3"; 1156 regulator-name = "abb_mpu"; 1157 #address-cells = <0>; 1158 #size-cells = <0>; 1159 clocks = <&sys_clkin1>; 1160 ti,settling-time = <50>; 1161 ti,clock-cycles = <16>; 1162 1163 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, 1164 <0x4ae06014 0x4>, <0x4a003b20 0xc>, 1165 <0x4ae0c158 0x4>; 1166 reg-names = "setup-address", "control-address", 1167 "int-address", "efuse-address", 1168 "ldo-address"; 1169 ti,tranxdone-status-mask = <0x80>; 1170 /* LDOVBBMPU_FBB_MUX_CTRL */ 1171 ti,ldovbb-override-mask = <0x400>; 1172 /* LDOVBBMPU_FBB_VSET_OUT */ 1173 ti,ldovbb-vset-mask = <0x1F>; 1174 1175 /* 1176 * NOTE: only FBB mode used but actual vset will 1177 * determine final biasing 1178 */ 1179 ti,abb_info = < 1180 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1181 1060000 0 0x0 0 0x02000000 0x01F00000 1182 1160000 0 0x4 0 0x02000000 0x01F00000 1183 1210000 0 0x8 0 0x02000000 0x01F00000 1184 >; 1185 }; 1186 1187 abb_ivahd: regulator-abb-ivahd { 1188 compatible = "ti,abb-v3"; 1189 regulator-name = "abb_ivahd"; 1190 #address-cells = <0>; 1191 #size-cells = <0>; 1192 clocks = <&sys_clkin1>; 1193 ti,settling-time = <50>; 1194 ti,clock-cycles = <16>; 1195 1196 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, 1197 <0x4ae06010 0x4>, <0x4a0025cc 0xc>, 1198 <0x4a002470 0x4>; 1199 reg-names = "setup-address", "control-address", 1200 "int-address", "efuse-address", 1201 "ldo-address"; 1202 ti,tranxdone-status-mask = <0x40000000>; 1203 /* LDOVBBIVA_FBB_MUX_CTRL */ 1204 ti,ldovbb-override-mask = <0x400>; 1205 /* LDOVBBIVA_FBB_VSET_OUT */ 1206 ti,ldovbb-vset-mask = <0x1F>; 1207 1208 /* 1209 * NOTE: only FBB mode used but actual vset will 1210 * determine final biasing 1211 */ 1212 ti,abb_info = < 1213 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1214 1055000 0 0x0 0 0x02000000 0x01F00000 1215 1150000 0 0x4 0 0x02000000 0x01F00000 1216 1250000 0 0x8 0 0x02000000 0x01F00000 1217 >; 1218 }; 1219 1220 abb_dspeve: regulator-abb-dspeve { 1221 compatible = "ti,abb-v3"; 1222 regulator-name = "abb_dspeve"; 1223 #address-cells = <0>; 1224 #size-cells = <0>; 1225 clocks = <&sys_clkin1>; 1226 ti,settling-time = <50>; 1227 ti,clock-cycles = <16>; 1228 1229 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, 1230 <0x4ae06010 0x4>, <0x4a0025e0 0xc>, 1231 <0x4a00246c 0x4>; 1232 reg-names = "setup-address", "control-address", 1233 "int-address", "efuse-address", 1234 "ldo-address"; 1235 ti,tranxdone-status-mask = <0x20000000>; 1236 /* LDOVBBDSPEVE_FBB_MUX_CTRL */ 1237 ti,ldovbb-override-mask = <0x400>; 1238 /* LDOVBBDSPEVE_FBB_VSET_OUT */ 1239 ti,ldovbb-vset-mask = <0x1F>; 1240 1241 /* 1242 * NOTE: only FBB mode used but actual vset will 1243 * determine final biasing 1244 */ 1245 ti,abb_info = < 1246 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1247 1055000 0 0x0 0 0x02000000 0x01F00000 1248 1150000 0 0x4 0 0x02000000 0x01F00000 1249 1250000 0 0x8 0 0x02000000 0x01F00000 1250 >; 1251 }; 1252 1253 abb_gpu: regulator-abb-gpu { 1254 compatible = "ti,abb-v3"; 1255 regulator-name = "abb_gpu"; 1256 #address-cells = <0>; 1257 #size-cells = <0>; 1258 clocks = <&sys_clkin1>; 1259 ti,settling-time = <50>; 1260 ti,clock-cycles = <16>; 1261 1262 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, 1263 <0x4ae06010 0x4>, <0x4a003b08 0xc>, 1264 <0x4ae0c154 0x4>; 1265 reg-names = "setup-address", "control-address", 1266 "int-address", "efuse-address", 1267 "ldo-address"; 1268 ti,tranxdone-status-mask = <0x10000000>; 1269 /* LDOVBBGPU_FBB_MUX_CTRL */ 1270 ti,ldovbb-override-mask = <0x400>; 1271 /* LDOVBBGPU_FBB_VSET_OUT */ 1272 ti,ldovbb-vset-mask = <0x1F>; 1273 1274 /* 1275 * NOTE: only FBB mode used but actual vset will 1276 * determine final biasing 1277 */ 1278 ti,abb_info = < 1279 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1280 1090000 0 0x0 0 0x02000000 0x01F00000 1281 1210000 0 0x4 0 0x02000000 0x01F00000 1282 1280000 0 0x8 0 0x02000000 0x01F00000 1283 >; 1284 }; 1285 1286 mcspi1: spi@48098000 { 1287 compatible = "ti,omap4-mcspi"; 1288 reg = <0x48098000 0x200>; 1289 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 ti,hwmods = "mcspi1"; 1293 ti,spi-num-cs = <4>; 1294 dmas = <&sdma_xbar 35>, 1295 <&sdma_xbar 36>, 1296 <&sdma_xbar 37>, 1297 <&sdma_xbar 38>, 1298 <&sdma_xbar 39>, 1299 <&sdma_xbar 40>, 1300 <&sdma_xbar 41>, 1301 <&sdma_xbar 42>; 1302 dma-names = "tx0", "rx0", "tx1", "rx1", 1303 "tx2", "rx2", "tx3", "rx3"; 1304 status = "disabled"; 1305 }; 1306 1307 mcspi2: spi@4809a000 { 1308 compatible = "ti,omap4-mcspi"; 1309 reg = <0x4809a000 0x200>; 1310 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 ti,hwmods = "mcspi2"; 1314 ti,spi-num-cs = <2>; 1315 dmas = <&sdma_xbar 43>, 1316 <&sdma_xbar 44>, 1317 <&sdma_xbar 45>, 1318 <&sdma_xbar 46>; 1319 dma-names = "tx0", "rx0", "tx1", "rx1"; 1320 status = "disabled"; 1321 }; 1322 1323 mcspi3: spi@480b8000 { 1324 compatible = "ti,omap4-mcspi"; 1325 reg = <0x480b8000 0x200>; 1326 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 ti,hwmods = "mcspi3"; 1330 ti,spi-num-cs = <2>; 1331 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; 1332 dma-names = "tx0", "rx0"; 1333 status = "disabled"; 1334 }; 1335 1336 mcspi4: spi@480ba000 { 1337 compatible = "ti,omap4-mcspi"; 1338 reg = <0x480ba000 0x200>; 1339 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 ti,hwmods = "mcspi4"; 1343 ti,spi-num-cs = <1>; 1344 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; 1345 dma-names = "tx0", "rx0"; 1346 status = "disabled"; 1347 }; 1348 1349 qspi: qspi@4b300000 { 1350 compatible = "ti,dra7xxx-qspi"; 1351 reg = <0x4b300000 0x100>, 1352 <0x5c000000 0x4000000>; 1353 reg-names = "qspi_base", "qspi_mmap"; 1354 syscon-chipselects = <&scm_conf 0x558>; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 ti,hwmods = "qspi"; 1358 clocks = <&qspi_gfclk_div>; 1359 clock-names = "fck"; 1360 num-cs = <4>; 1361 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1362 status = "disabled"; 1363 }; 1364 1365 /* OCP2SCP3 */ 1366 ocp2scp@4a090000 { 1367 compatible = "ti,omap-ocp2scp"; 1368 #address-cells = <1>; 1369 #size-cells = <1>; 1370 ranges; 1371 reg = <0x4a090000 0x20>; 1372 ti,hwmods = "ocp2scp3"; 1373 sata_phy: phy@4A096000 { 1374 compatible = "ti,phy-pipe3-sata"; 1375 reg = <0x4A096000 0x80>, /* phy_rx */ 1376 <0x4A096400 0x64>, /* phy_tx */ 1377 <0x4A096800 0x40>; /* pll_ctrl */ 1378 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1379 syscon-phy-power = <&scm_conf 0x374>; 1380 clocks = <&sys_clkin1>, <&sata_ref_clk>; 1381 clock-names = "sysclk", "refclk"; 1382 syscon-pllreset = <&scm_conf 0x3fc>; 1383 #phy-cells = <0>; 1384 }; 1385 1386 pcie1_phy: pciephy@4a094000 { 1387 compatible = "ti,phy-pipe3-pcie"; 1388 reg = <0x4a094000 0x80>, /* phy_rx */ 1389 <0x4a094400 0x64>; /* phy_tx */ 1390 reg-names = "phy_rx", "phy_tx"; 1391 syscon-phy-power = <&scm_conf_pcie 0x1c>; 1392 syscon-pcs = <&scm_conf_pcie 0x10>; 1393 clocks = <&dpll_pcie_ref_ck>, 1394 <&dpll_pcie_ref_m2ldo_ck>, 1395 <&optfclk_pciephy1_32khz>, 1396 <&optfclk_pciephy1_clk>, 1397 <&optfclk_pciephy1_div_clk>, 1398 <&optfclk_pciephy_div>, 1399 <&sys_clkin1>; 1400 clock-names = "dpll_ref", "dpll_ref_m2", 1401 "wkupclk", "refclk", 1402 "div-clk", "phy-div", "sysclk"; 1403 #phy-cells = <0>; 1404 }; 1405 1406 pcie2_phy: pciephy@4a095000 { 1407 compatible = "ti,phy-pipe3-pcie"; 1408 reg = <0x4a095000 0x80>, /* phy_rx */ 1409 <0x4a095400 0x64>; /* phy_tx */ 1410 reg-names = "phy_rx", "phy_tx"; 1411 syscon-phy-power = <&scm_conf_pcie 0x20>; 1412 syscon-pcs = <&scm_conf_pcie 0x10>; 1413 clocks = <&dpll_pcie_ref_ck>, 1414 <&dpll_pcie_ref_m2ldo_ck>, 1415 <&optfclk_pciephy2_32khz>, 1416 <&optfclk_pciephy2_clk>, 1417 <&optfclk_pciephy2_div_clk>, 1418 <&optfclk_pciephy_div>, 1419 <&sys_clkin1>; 1420 clock-names = "dpll_ref", "dpll_ref_m2", 1421 "wkupclk", "refclk", 1422 "div-clk", "phy-div", "sysclk"; 1423 #phy-cells = <0>; 1424 status = "disabled"; 1425 }; 1426 }; 1427 1428 sata: sata@4a141100 { 1429 compatible = "snps,dwc-ahci"; 1430 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; 1431 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1432 phys = <&sata_phy>; 1433 phy-names = "sata-phy"; 1434 clocks = <&sata_ref_clk>; 1435 ti,hwmods = "sata"; 1436 ports-implemented = <0x1>; 1437 }; 1438 1439 rtc: rtc@48838000 { 1440 compatible = "ti,am3352-rtc"; 1441 reg = <0x48838000 0x100>; 1442 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 1444 ti,hwmods = "rtcss"; 1445 clocks = <&sys_32k_ck>; 1446 }; 1447 1448 /* OCP2SCP1 */ 1449 ocp2scp@4a080000 { 1450 compatible = "ti,omap-ocp2scp"; 1451 #address-cells = <1>; 1452 #size-cells = <1>; 1453 ranges; 1454 reg = <0x4a080000 0x20>; 1455 ti,hwmods = "ocp2scp1"; 1456 1457 usb2_phy1: phy@4a084000 { 1458 compatible = "ti,dra7x-usb2", "ti,omap-usb2"; 1459 reg = <0x4a084000 0x400>; 1460 syscon-phy-power = <&scm_conf 0x300>; 1461 clocks = <&usb_phy1_always_on_clk32k>, 1462 <&usb_otg_ss1_refclk960m>; 1463 clock-names = "wkupclk", 1464 "refclk"; 1465 #phy-cells = <0>; 1466 }; 1467 1468 usb2_phy2: phy@4a085000 { 1469 compatible = "ti,dra7x-usb2-phy2", 1470 "ti,omap-usb2"; 1471 reg = <0x4a085000 0x400>; 1472 syscon-phy-power = <&scm_conf 0xe74>; 1473 clocks = <&usb_phy2_always_on_clk32k>, 1474 <&usb_otg_ss2_refclk960m>; 1475 clock-names = "wkupclk", 1476 "refclk"; 1477 #phy-cells = <0>; 1478 }; 1479 1480 usb3_phy1: phy@4a084400 { 1481 compatible = "ti,omap-usb3"; 1482 reg = <0x4a084400 0x80>, 1483 <0x4a084800 0x64>, 1484 <0x4a084c00 0x40>; 1485 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1486 syscon-phy-power = <&scm_conf 0x370>; 1487 clocks = <&usb_phy3_always_on_clk32k>, 1488 <&sys_clkin1>, 1489 <&usb_otg_ss1_refclk960m>; 1490 clock-names = "wkupclk", 1491 "sysclk", 1492 "refclk"; 1493 #phy-cells = <0>; 1494 }; 1495 }; 1496 1497 omap_dwc3_1: omap_dwc3_1@48880000 { 1498 compatible = "ti,dwc3"; 1499 ti,hwmods = "usb_otg_ss1"; 1500 reg = <0x48880000 0x10000>; 1501 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1502 #address-cells = <1>; 1503 #size-cells = <1>; 1504 utmi-mode = <2>; 1505 ranges; 1506 usb1: usb@48890000 { 1507 compatible = "snps,dwc3"; 1508 reg = <0x48890000 0x17000>; 1509 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1512 interrupt-names = "peripheral", 1513 "host", 1514 "otg"; 1515 phys = <&usb2_phy1>, <&usb3_phy1>; 1516 phy-names = "usb2-phy", "usb3-phy"; 1517 maximum-speed = "super-speed"; 1518 dr_mode = "otg"; 1519 snps,dis_u3_susphy_quirk; 1520 snps,dis_u2_susphy_quirk; 1521 }; 1522 }; 1523 1524 omap_dwc3_2: omap_dwc3_2@488c0000 { 1525 compatible = "ti,dwc3"; 1526 ti,hwmods = "usb_otg_ss2"; 1527 reg = <0x488c0000 0x10000>; 1528 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1529 #address-cells = <1>; 1530 #size-cells = <1>; 1531 utmi-mode = <2>; 1532 ranges; 1533 usb2: usb@488d0000 { 1534 compatible = "snps,dwc3"; 1535 reg = <0x488d0000 0x17000>; 1536 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1539 interrupt-names = "peripheral", 1540 "host", 1541 "otg"; 1542 phys = <&usb2_phy2>; 1543 phy-names = "usb2-phy"; 1544 maximum-speed = "high-speed"; 1545 dr_mode = "otg"; 1546 snps,dis_u3_susphy_quirk; 1547 snps,dis_u2_susphy_quirk; 1548 snps,dis_metastability_quirk; 1549 }; 1550 }; 1551 1552 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ 1553 omap_dwc3_3: omap_dwc3_3@48900000 { 1554 compatible = "ti,dwc3"; 1555 ti,hwmods = "usb_otg_ss3"; 1556 reg = <0x48900000 0x10000>; 1557 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1558 #address-cells = <1>; 1559 #size-cells = <1>; 1560 utmi-mode = <2>; 1561 ranges; 1562 status = "disabled"; 1563 usb3: usb@48910000 { 1564 compatible = "snps,dwc3"; 1565 reg = <0x48910000 0x17000>; 1566 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1569 interrupt-names = "peripheral", 1570 "host", 1571 "otg"; 1572 maximum-speed = "high-speed"; 1573 dr_mode = "otg"; 1574 snps,dis_u3_susphy_quirk; 1575 snps,dis_u2_susphy_quirk; 1576 }; 1577 }; 1578 1579 elm: elm@48078000 { 1580 compatible = "ti,am3352-elm"; 1581 reg = <0x48078000 0xfc0>; /* device IO registers */ 1582 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1583 ti,hwmods = "elm"; 1584 status = "disabled"; 1585 }; 1586 1587 gpmc: gpmc@50000000 { 1588 compatible = "ti,am3352-gpmc"; 1589 ti,hwmods = "gpmc"; 1590 reg = <0x50000000 0x37c>; /* device IO registers */ 1591 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1592 dmas = <&edma_xbar 4 0>; 1593 dma-names = "rxtx"; 1594 gpmc,num-cs = <8>; 1595 gpmc,num-waitpins = <2>; 1596 #address-cells = <2>; 1597 #size-cells = <1>; 1598 interrupt-controller; 1599 #interrupt-cells = <2>; 1600 gpio-controller; 1601 #gpio-cells = <2>; 1602 status = "disabled"; 1603 }; 1604 1605 atl: atl@4843c000 { 1606 compatible = "ti,dra7-atl"; 1607 reg = <0x4843c000 0x3ff>; 1608 ti,hwmods = "atl"; 1609 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, 1610 <&atl_clkin2_ck>, <&atl_clkin3_ck>; 1611 clocks = <&atl_gfclk_mux>; 1612 clock-names = "fck"; 1613 status = "disabled"; 1614 }; 1615 1616 mcasp1: mcasp@48460000 { 1617 compatible = "ti,dra7-mcasp-audio"; 1618 ti,hwmods = "mcasp1"; 1619 reg = <0x48460000 0x2000>, 1620 <0x45800000 0x1000>; 1621 reg-names = "mpu","dat"; 1622 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1624 interrupt-names = "tx", "rx"; 1625 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; 1626 dma-names = "tx", "rx"; 1627 clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>, 1628 <&mcasp1_ahclkr_mux>; 1629 clock-names = "fck", "ahclkx", "ahclkr"; 1630 status = "disabled"; 1631 }; 1632 1633 mcasp2: mcasp@48464000 { 1634 compatible = "ti,dra7-mcasp-audio"; 1635 ti,hwmods = "mcasp2"; 1636 reg = <0x48464000 0x2000>, 1637 <0x45c00000 0x1000>; 1638 reg-names = "mpu","dat"; 1639 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1641 interrupt-names = "tx", "rx"; 1642 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; 1643 dma-names = "tx", "rx"; 1644 clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>, 1645 <&mcasp2_ahclkr_mux>; 1646 clock-names = "fck", "ahclkx", "ahclkr"; 1647 status = "disabled"; 1648 }; 1649 1650 mcasp3: mcasp@48468000 { 1651 compatible = "ti,dra7-mcasp-audio"; 1652 ti,hwmods = "mcasp3"; 1653 reg = <0x48468000 0x2000>, 1654 <0x46000000 0x1000>; 1655 reg-names = "mpu","dat"; 1656 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1658 interrupt-names = "tx", "rx"; 1659 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; 1660 dma-names = "tx", "rx"; 1661 clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>; 1662 clock-names = "fck", "ahclkx"; 1663 status = "disabled"; 1664 }; 1665 1666 mcasp4: mcasp@4846c000 { 1667 compatible = "ti,dra7-mcasp-audio"; 1668 ti,hwmods = "mcasp4"; 1669 reg = <0x4846c000 0x2000>, 1670 <0x48436000 0x1000>; 1671 reg-names = "mpu","dat"; 1672 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1674 interrupt-names = "tx", "rx"; 1675 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; 1676 dma-names = "tx", "rx"; 1677 clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>; 1678 clock-names = "fck", "ahclkx"; 1679 status = "disabled"; 1680 }; 1681 1682 mcasp5: mcasp@48470000 { 1683 compatible = "ti,dra7-mcasp-audio"; 1684 ti,hwmods = "mcasp5"; 1685 reg = <0x48470000 0x2000>, 1686 <0x4843a000 0x1000>; 1687 reg-names = "mpu","dat"; 1688 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1690 interrupt-names = "tx", "rx"; 1691 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; 1692 dma-names = "tx", "rx"; 1693 clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>; 1694 clock-names = "fck", "ahclkx"; 1695 status = "disabled"; 1696 }; 1697 1698 mcasp6: mcasp@48474000 { 1699 compatible = "ti,dra7-mcasp-audio"; 1700 ti,hwmods = "mcasp6"; 1701 reg = <0x48474000 0x2000>, 1702 <0x4844c000 0x1000>; 1703 reg-names = "mpu","dat"; 1704 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1706 interrupt-names = "tx", "rx"; 1707 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; 1708 dma-names = "tx", "rx"; 1709 clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>; 1710 clock-names = "fck", "ahclkx"; 1711 status = "disabled"; 1712 }; 1713 1714 mcasp7: mcasp@48478000 { 1715 compatible = "ti,dra7-mcasp-audio"; 1716 ti,hwmods = "mcasp7"; 1717 reg = <0x48478000 0x2000>, 1718 <0x48450000 0x1000>; 1719 reg-names = "mpu","dat"; 1720 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1722 interrupt-names = "tx", "rx"; 1723 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; 1724 dma-names = "tx", "rx"; 1725 clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>; 1726 clock-names = "fck", "ahclkx"; 1727 status = "disabled"; 1728 }; 1729 1730 mcasp8: mcasp@4847c000 { 1731 compatible = "ti,dra7-mcasp-audio"; 1732 ti,hwmods = "mcasp8"; 1733 reg = <0x4847c000 0x2000>, 1734 <0x48454000 0x1000>; 1735 reg-names = "mpu","dat"; 1736 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1738 interrupt-names = "tx", "rx"; 1739 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; 1740 dma-names = "tx", "rx"; 1741 clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>; 1742 clock-names = "fck", "ahclkx"; 1743 status = "disabled"; 1744 }; 1745 1746 crossbar_mpu: crossbar@4a002a48 { 1747 compatible = "ti,irq-crossbar"; 1748 reg = <0x4a002a48 0x130>; 1749 interrupt-controller; 1750 interrupt-parent = <&wakeupgen>; 1751 #interrupt-cells = <3>; 1752 ti,max-irqs = <160>; 1753 ti,max-crossbar-sources = <MAX_SOURCES>; 1754 ti,reg-size = <2>; 1755 ti,irqs-reserved = <0 1 2 3 5 6 131 132>; 1756 ti,irqs-skip = <10 133 139 140>; 1757 ti,irqs-safe-map = <0>; 1758 }; 1759 1760 mac: ethernet@48484000 { 1761 compatible = "ti,dra7-cpsw","ti,cpsw"; 1762 ti,hwmods = "gmac"; 1763 clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>; 1764 clock-names = "fck", "cpts"; 1765 cpdma_channels = <8>; 1766 ale_entries = <1024>; 1767 bd_ram_size = <0x2000>; 1768 mac_control = <0x20>; 1769 slaves = <2>; 1770 active_slave = <0>; 1771 cpts_clock_mult = <0x784CFE14>; 1772 cpts_clock_shift = <29>; 1773 reg = <0x48484000 0x1000 1774 0x48485200 0x2E00>; 1775 #address-cells = <1>; 1776 #size-cells = <1>; 1777 1778 /* 1779 * Do not allow gating of cpsw clock as workaround 1780 * for errata i877. Keeping internal clock disabled 1781 * causes the device switching characteristics 1782 * to degrade over time and eventually fail to meet 1783 * the data manual delay time/skew specs. 1784 */ 1785 ti,no-idle; 1786 1787 /* 1788 * rx_thresh_pend 1789 * rx_pend 1790 * tx_pend 1791 * misc_pend 1792 */ 1793 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 1797 ranges; 1798 syscon = <&scm_conf>; 1799 status = "disabled"; 1800 1801 davinci_mdio: mdio@48485000 { 1802 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 1803 #address-cells = <1>; 1804 #size-cells = <0>; 1805 ti,hwmods = "davinci_mdio"; 1806 bus_freq = <1000000>; 1807 reg = <0x48485000 0x100>; 1808 }; 1809 1810 cpsw_emac0: slave@48480200 { 1811 /* Filled in by U-Boot */ 1812 mac-address = [ 00 00 00 00 00 00 ]; 1813 }; 1814 1815 cpsw_emac1: slave@48480300 { 1816 /* Filled in by U-Boot */ 1817 mac-address = [ 00 00 00 00 00 00 ]; 1818 }; 1819 1820 phy_sel: cpsw-phy-sel@4a002554 { 1821 compatible = "ti,dra7xx-cpsw-phy-sel"; 1822 reg= <0x4a002554 0x4>; 1823 reg-names = "gmii-sel"; 1824 }; 1825 }; 1826 1827 dcan1: can@4ae3c000 { 1828 compatible = "ti,dra7-d_can"; 1829 ti,hwmods = "dcan1"; 1830 reg = <0x4ae3c000 0x2000>; 1831 syscon-raminit = <&scm_conf 0x558 0>; 1832 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1833 clocks = <&dcan1_sys_clk_mux>; 1834 status = "disabled"; 1835 }; 1836 1837 dcan2: can@48480000 { 1838 compatible = "ti,dra7-d_can"; 1839 ti,hwmods = "dcan2"; 1840 reg = <0x48480000 0x2000>; 1841 syscon-raminit = <&scm_conf 0x558 1>; 1842 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1843 clocks = <&sys_clkin1>; 1844 status = "disabled"; 1845 }; 1846 1847 dss: dss@58000000 { 1848 compatible = "ti,dra7-dss"; 1849 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ 1850 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ 1851 status = "disabled"; 1852 ti,hwmods = "dss_core"; 1853 /* CTRL_CORE_DSS_PLL_CONTROL */ 1854 syscon-pll-ctrl = <&scm_conf 0x538>; 1855 #address-cells = <1>; 1856 #size-cells = <1>; 1857 ranges; 1858 1859 dispc@58001000 { 1860 compatible = "ti,dra7-dispc"; 1861 reg = <0x58001000 0x1000>; 1862 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1863 ti,hwmods = "dss_dispc"; 1864 clocks = <&dss_dss_clk>; 1865 clock-names = "fck"; 1866 /* CTRL_CORE_SMA_SW_1 */ 1867 syscon-pol = <&scm_conf 0x534>; 1868 }; 1869 1870 hdmi: encoder@58060000 { 1871 compatible = "ti,dra7-hdmi"; 1872 reg = <0x58040000 0x200>, 1873 <0x58040200 0x80>, 1874 <0x58040300 0x80>, 1875 <0x58060000 0x19000>; 1876 reg-names = "wp", "pll", "phy", "core"; 1877 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1878 status = "disabled"; 1879 ti,hwmods = "dss_hdmi"; 1880 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; 1881 clock-names = "fck", "sys_clk"; 1882 }; 1883 }; 1884 1885 epwmss0: epwmss@4843e000 { 1886 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 1887 reg = <0x4843e000 0x30>; 1888 ti,hwmods = "epwmss0"; 1889 #address-cells = <1>; 1890 #size-cells = <1>; 1891 status = "disabled"; 1892 ranges; 1893 1894 ehrpwm0: pwm@4843e200 { 1895 compatible = "ti,dra746-ehrpwm", 1896 "ti,am3352-ehrpwm"; 1897 #pwm-cells = <3>; 1898 reg = <0x4843e200 0x80>; 1899 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; 1900 clock-names = "tbclk", "fck"; 1901 status = "disabled"; 1902 }; 1903 1904 ecap0: ecap@4843e100 { 1905 compatible = "ti,dra746-ecap", 1906 "ti,am3352-ecap"; 1907 #pwm-cells = <3>; 1908 reg = <0x4843e100 0x80>; 1909 clocks = <&l4_root_clk_div>; 1910 clock-names = "fck"; 1911 status = "disabled"; 1912 }; 1913 }; 1914 1915 epwmss1: epwmss@48440000 { 1916 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 1917 reg = <0x48440000 0x30>; 1918 ti,hwmods = "epwmss1"; 1919 #address-cells = <1>; 1920 #size-cells = <1>; 1921 status = "disabled"; 1922 ranges; 1923 1924 ehrpwm1: pwm@48440200 { 1925 compatible = "ti,dra746-ehrpwm", 1926 "ti,am3352-ehrpwm"; 1927 #pwm-cells = <3>; 1928 reg = <0x48440200 0x80>; 1929 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; 1930 clock-names = "tbclk", "fck"; 1931 status = "disabled"; 1932 }; 1933 1934 ecap1: ecap@48440100 { 1935 compatible = "ti,dra746-ecap", 1936 "ti,am3352-ecap"; 1937 #pwm-cells = <3>; 1938 reg = <0x48440100 0x80>; 1939 clocks = <&l4_root_clk_div>; 1940 clock-names = "fck"; 1941 status = "disabled"; 1942 }; 1943 }; 1944 1945 epwmss2: epwmss@48442000 { 1946 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 1947 reg = <0x48442000 0x30>; 1948 ti,hwmods = "epwmss2"; 1949 #address-cells = <1>; 1950 #size-cells = <1>; 1951 status = "disabled"; 1952 ranges; 1953 1954 ehrpwm2: pwm@48442200 { 1955 compatible = "ti,dra746-ehrpwm", 1956 "ti,am3352-ehrpwm"; 1957 #pwm-cells = <3>; 1958 reg = <0x48442200 0x80>; 1959 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; 1960 clock-names = "tbclk", "fck"; 1961 status = "disabled"; 1962 }; 1963 1964 ecap2: ecap@48442100 { 1965 compatible = "ti,dra746-ecap", 1966 "ti,am3352-ecap"; 1967 #pwm-cells = <3>; 1968 reg = <0x48442100 0x80>; 1969 clocks = <&l4_root_clk_div>; 1970 clock-names = "fck"; 1971 status = "disabled"; 1972 }; 1973 }; 1974 1975 aes1: aes@4b500000 { 1976 compatible = "ti,omap4-aes"; 1977 ti,hwmods = "aes1"; 1978 reg = <0x4b500000 0xa0>; 1979 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1980 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; 1981 dma-names = "tx", "rx"; 1982 clocks = <&l3_iclk_div>; 1983 clock-names = "fck"; 1984 }; 1985 1986 aes2: aes@4b700000 { 1987 compatible = "ti,omap4-aes"; 1988 ti,hwmods = "aes2"; 1989 reg = <0x4b700000 0xa0>; 1990 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1991 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; 1992 dma-names = "tx", "rx"; 1993 clocks = <&l3_iclk_div>; 1994 clock-names = "fck"; 1995 }; 1996 1997 des: des@480a5000 { 1998 compatible = "ti,omap4-des"; 1999 ti,hwmods = "des"; 2000 reg = <0x480a5000 0xa0>; 2001 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 2002 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; 2003 dma-names = "tx", "rx"; 2004 clocks = <&l3_iclk_div>; 2005 clock-names = "fck"; 2006 }; 2007 2008 sham: sham@53100000 { 2009 compatible = "ti,omap5-sham"; 2010 ti,hwmods = "sham"; 2011 reg = <0x4b101000 0x300>; 2012 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 2013 dmas = <&edma_xbar 119 0>; 2014 dma-names = "rx"; 2015 clocks = <&l3_iclk_div>; 2016 clock-names = "fck"; 2017 }; 2018 2019 rng: rng@48090000 { 2020 compatible = "ti,omap4-rng"; 2021 ti,hwmods = "rng"; 2022 reg = <0x48090000 0x2000>; 2023 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2024 clocks = <&l3_iclk_div>; 2025 clock-names = "fck"; 2026 }; 2027 }; 2028 2029 thermal_zones: thermal-zones { 2030 #include "omap4-cpu-thermal.dtsi" 2031 #include "omap5-gpu-thermal.dtsi" 2032 #include "omap5-core-thermal.dtsi" 2033 #include "dra7-dspeve-thermal.dtsi" 2034 #include "dra7-iva-thermal.dtsi" 2035 }; 2036 2037}; 2038 2039&cpu_thermal { 2040 polling-delay = <500>; /* milliseconds */ 2041 coefficients = <0 2000>; 2042}; 2043 2044&gpu_thermal { 2045 coefficients = <0 2000>; 2046}; 2047 2048&core_thermal { 2049 coefficients = <0 2000>; 2050}; 2051 2052&dspeve_thermal { 2053 coefficients = <0 2000>; 2054}; 2055 2056&iva_thermal { 2057 coefficients = <0 2000>; 2058}; 2059 2060&cpu_crit { 2061 temperature = <120000>; /* milli Celsius */ 2062}; 2063 2064/include/ "dra7xx-clocks.dtsi" 2065