1/* 2 * Device Tree Source for the EMEV2 SoC 3 * 4 * Copyright (C) 2012 Renesas Solutions Corp. 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13 14/ { 15 compatible = "renesas,emev2"; 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 gpio2 = &gpio2; 24 gpio3 = &gpio3; 25 gpio4 = &gpio4; 26 i2c0 = &iic0; 27 i2c1 = &iic1; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a9"; 37 reg = <0>; 38 clock-frequency = <533000000>; 39 }; 40 cpu1: cpu@1 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a9"; 43 reg = <1>; 44 clock-frequency = <533000000>; 45 }; 46 }; 47 48 gic: interrupt-controller@e0020000 { 49 compatible = "arm,pl390"; 50 interrupt-controller; 51 #interrupt-cells = <3>; 52 reg = <0xe0028000 0x1000>, 53 <0xe0020000 0x0100>; 54 }; 55 56 pmu { 57 compatible = "arm,cortex-a9-pmu"; 58 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 60 interrupt-affinity = <&cpu0>, <&cpu1>; 61 }; 62 63 clocks@e0110000 { 64 compatible = "renesas,emev2-smu"; 65 reg = <0xe0110000 0x10000>; 66 #address-cells = <2>; 67 #size-cells = <0>; 68 69 c32ki: c32ki { 70 compatible = "fixed-clock"; 71 clock-frequency = <32768>; 72 #clock-cells = <0>; 73 }; 74 iic0_sclkdiv: iic0_sclkdiv@624,0 { 75 compatible = "renesas,emev2-smu-clkdiv"; 76 reg = <0x624 0>; 77 clocks = <&pll3_fo>; 78 #clock-cells = <0>; 79 }; 80 iic0_sclk: iic0_sclk@48c,1 { 81 compatible = "renesas,emev2-smu-gclk"; 82 reg = <0x48c 1>; 83 clocks = <&iic0_sclkdiv>; 84 #clock-cells = <0>; 85 }; 86 iic1_sclkdiv: iic1_sclkdiv@624,16 { 87 compatible = "renesas,emev2-smu-clkdiv"; 88 reg = <0x624 16>; 89 clocks = <&pll3_fo>; 90 #clock-cells = <0>; 91 }; 92 iic1_sclk: iic1_sclk@490,1 { 93 compatible = "renesas,emev2-smu-gclk"; 94 reg = <0x490 1>; 95 clocks = <&iic1_sclkdiv>; 96 #clock-cells = <0>; 97 }; 98 pll3_fo: pll3_fo { 99 compatible = "fixed-factor-clock"; 100 clocks = <&c32ki>; 101 clock-div = <1>; 102 clock-mult = <7000>; 103 #clock-cells = <0>; 104 }; 105 usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 { 106 compatible = "renesas,emev2-smu-clkdiv"; 107 reg = <0x610 0>; 108 clocks = <&pll3_fo>; 109 #clock-cells = <0>; 110 }; 111 usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 { 112 compatible = "renesas,emev2-smu-clkdiv"; 113 reg = <0x65c 0>; 114 clocks = <&pll3_fo>; 115 #clock-cells = <0>; 116 }; 117 usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 { 118 compatible = "renesas,emev2-smu-clkdiv"; 119 reg = <0x65c 16>; 120 clocks = <&pll3_fo>; 121 #clock-cells = <0>; 122 }; 123 usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 { 124 compatible = "renesas,emev2-smu-clkdiv"; 125 reg = <0x660 0>; 126 clocks = <&pll3_fo>; 127 #clock-cells = <0>; 128 }; 129 usia_u0_sclk: usia_u0_sclk@4a0,1 { 130 compatible = "renesas,emev2-smu-gclk"; 131 reg = <0x4a0 1>; 132 clocks = <&usia_u0_sclkdiv>; 133 #clock-cells = <0>; 134 }; 135 usib_u1_sclk: usib_u1_sclk@4b8,1 { 136 compatible = "renesas,emev2-smu-gclk"; 137 reg = <0x4b8 1>; 138 clocks = <&usib_u1_sclkdiv>; 139 #clock-cells = <0>; 140 }; 141 usib_u2_sclk: usib_u2_sclk@4bc,1 { 142 compatible = "renesas,emev2-smu-gclk"; 143 reg = <0x4bc 1>; 144 clocks = <&usib_u2_sclkdiv>; 145 #clock-cells = <0>; 146 }; 147 usib_u3_sclk: usib_u3_sclk@4c0,1 { 148 compatible = "renesas,emev2-smu-gclk"; 149 reg = <0x4c0 1>; 150 clocks = <&usib_u3_sclkdiv>; 151 #clock-cells = <0>; 152 }; 153 sti_sclk: sti_sclk@528,1 { 154 compatible = "renesas,emev2-smu-gclk"; 155 reg = <0x528 1>; 156 clocks = <&c32ki>; 157 #clock-cells = <0>; 158 }; 159 }; 160 161 timer@e0180000 { 162 compatible = "renesas,em-sti"; 163 reg = <0xe0180000 0x54>; 164 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&sti_sclk>; 166 clock-names = "sclk"; 167 }; 168 169 uart0: serial@e1020000 { 170 compatible = "renesas,em-uart"; 171 reg = <0xe1020000 0x38>; 172 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 173 clocks = <&usia_u0_sclk>; 174 clock-names = "sclk"; 175 }; 176 177 uart1: serial@e1030000 { 178 compatible = "renesas,em-uart"; 179 reg = <0xe1030000 0x38>; 180 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 181 clocks = <&usib_u1_sclk>; 182 clock-names = "sclk"; 183 }; 184 185 uart2: serial@e1040000 { 186 compatible = "renesas,em-uart"; 187 reg = <0xe1040000 0x38>; 188 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&usib_u2_sclk>; 190 clock-names = "sclk"; 191 }; 192 193 uart3: serial@e1050000 { 194 compatible = "renesas,em-uart"; 195 reg = <0xe1050000 0x38>; 196 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&usib_u3_sclk>; 198 clock-names = "sclk"; 199 }; 200 201 pfc: pin-controller@e0140200 { 202 compatible = "renesas,pfc-emev2"; 203 reg = <0xe0140200 0x100>; 204 }; 205 206 gpio0: gpio@e0050000 { 207 compatible = "renesas,em-gio"; 208 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; 209 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 211 gpio-controller; 212 gpio-ranges = <&pfc 0 0 32>; 213 #gpio-cells = <2>; 214 ngpios = <32>; 215 interrupt-controller; 216 #interrupt-cells = <2>; 217 }; 218 gpio1: gpio@e0050080 { 219 compatible = "renesas,em-gio"; 220 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; 221 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 223 gpio-controller; 224 gpio-ranges = <&pfc 0 32 32>; 225 #gpio-cells = <2>; 226 ngpios = <32>; 227 interrupt-controller; 228 #interrupt-cells = <2>; 229 }; 230 gpio2: gpio@e0050100 { 231 compatible = "renesas,em-gio"; 232 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; 233 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 235 gpio-controller; 236 gpio-ranges = <&pfc 0 64 32>; 237 #gpio-cells = <2>; 238 ngpios = <32>; 239 interrupt-controller; 240 #interrupt-cells = <2>; 241 }; 242 gpio3: gpio@e0050180 { 243 compatible = "renesas,em-gio"; 244 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; 245 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 247 gpio-controller; 248 gpio-ranges = <&pfc 0 96 32>; 249 #gpio-cells = <2>; 250 ngpios = <32>; 251 interrupt-controller; 252 #interrupt-cells = <2>; 253 }; 254 gpio4: gpio@e0050200 { 255 compatible = "renesas,em-gio"; 256 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; 257 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 259 gpio-controller; 260 gpio-ranges = <&pfc 0 128 31>; 261 #gpio-cells = <2>; 262 ngpios = <31>; 263 interrupt-controller; 264 #interrupt-cells = <2>; 265 }; 266 267 iic0: i2c@e0070000 { 268 #address-cells = <1>; 269 #size-cells = <0>; 270 compatible = "renesas,iic-emev2"; 271 reg = <0xe0070000 0x28>; 272 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 273 clocks = <&iic0_sclk>; 274 clock-names = "sclk"; 275 status = "disabled"; 276 }; 277 278 iic1: i2c@e10a0000 { 279 #address-cells = <1>; 280 #size-cells = <0>; 281 compatible = "renesas,iic-emev2"; 282 reg = <0xe10a0000 0x28>; 283 interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>; 284 clocks = <&iic1_sclk>; 285 clock-names = "sclk"; 286 status = "disabled"; 287 }; 288}; 289