1/* 2 * Samsung's Exynos4210 SoC device tree source 3 * 4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * Copyright (c) 2010-2011 Linaro Ltd. 7 * www.linaro.org 8 * 9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 10 * based board files can include this file and provide values for board specfic 11 * bindings. 12 * 13 * Note: This file does not include device nodes for all the controllers in 14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional 15 * nodes can be added to this file. 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License version 2 as 19 * published by the Free Software Foundation. 20*/ 21 22#include "exynos4.dtsi" 23#include "exynos4210-pinctrl.dtsi" 24#include "exynos4-cpu-thermal.dtsi" 25 26/ { 27 compatible = "samsung,exynos4210", "samsung,exynos4"; 28 29 aliases { 30 pinctrl0 = &pinctrl_0; 31 pinctrl1 = &pinctrl_1; 32 pinctrl2 = &pinctrl_2; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu0: cpu@900 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a9"; 42 reg = <0x900>; 43 clocks = <&clock CLK_ARM_CLK>; 44 clock-names = "cpu"; 45 clock-latency = <160000>; 46 47 operating-points = < 48 1200000 1250000 49 1000000 1150000 50 800000 1075000 51 500000 975000 52 400000 975000 53 200000 950000 54 >; 55 #cooling-cells = <2>; /* min followed by max */ 56 }; 57 58 cpu@901 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a9"; 61 reg = <0x901>; 62 clocks = <&clock CLK_ARM_CLK>; 63 clock-names = "cpu"; 64 clock-latency = <160000>; 65 66 operating-points = < 67 1200000 1250000 68 1000000 1150000 69 800000 1075000 70 500000 975000 71 400000 975000 72 200000 950000 73 >; 74 #cooling-cells = <2>; /* min followed by max */ 75 }; 76 }; 77 78 sysram: sysram@02020000 { 79 compatible = "mmio-sram"; 80 reg = <0x02020000 0x20000>; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges = <0 0x02020000 0x20000>; 84 85 smp-sysram@0 { 86 compatible = "samsung,exynos4210-sysram"; 87 reg = <0x0 0x1000>; 88 }; 89 90 smp-sysram@1f000 { 91 compatible = "samsung,exynos4210-sysram-ns"; 92 reg = <0x1f000 0x1000>; 93 }; 94 }; 95 96 pd_lcd1: lcd1-power-domain@10023CA0 { 97 compatible = "samsung,exynos4210-pd"; 98 reg = <0x10023CA0 0x20>; 99 #power-domain-cells = <0>; 100 label = "LCD1"; 101 }; 102 103 l2c: l2-cache-controller@10502000 { 104 compatible = "arm,pl310-cache"; 105 reg = <0x10502000 0x1000>; 106 cache-unified; 107 cache-level = <2>; 108 arm,tag-latency = <2 2 1>; 109 arm,data-latency = <2 2 1>; 110 }; 111 112 mct: mct@10050000 { 113 compatible = "samsung,exynos4210-mct"; 114 reg = <0x10050000 0x800>; 115 interrupt-parent = <&mct_map>; 116 interrupts = <0>, <1>, <2>, <3>, <4>, <5>; 117 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 118 clock-names = "fin_pll", "mct"; 119 120 mct_map: mct-map { 121 #interrupt-cells = <1>; 122 #address-cells = <0>; 123 #size-cells = <0>; 124 interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, 125 <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>, 126 <2 &combiner 12 6>, 127 <3 &combiner 12 7>, 128 <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>, 129 <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>; 130 }; 131 }; 132 133 watchdog: watchdog@10060000 { 134 compatible = "samsung,s3c6410-wdt"; 135 reg = <0x10060000 0x100>; 136 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&clock CLK_WDT>; 138 clock-names = "watchdog"; 139 }; 140 141 clock: clock-controller@10030000 { 142 compatible = "samsung,exynos4210-clock"; 143 reg = <0x10030000 0x20000>; 144 #clock-cells = <1>; 145 }; 146 147 pinctrl_0: pinctrl@11400000 { 148 compatible = "samsung,exynos4210-pinctrl"; 149 reg = <0x11400000 0x1000>; 150 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 151 }; 152 153 pinctrl_1: pinctrl@11000000 { 154 compatible = "samsung,exynos4210-pinctrl"; 155 reg = <0x11000000 0x1000>; 156 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 157 158 wakup_eint: wakeup-interrupt-controller { 159 compatible = "samsung,exynos4210-wakeup-eint"; 160 interrupt-parent = <&gic>; 161 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 162 }; 163 }; 164 165 pinctrl_2: pinctrl@03860000 { 166 compatible = "samsung,exynos4210-pinctrl"; 167 reg = <0x03860000 0x1000>; 168 }; 169 170 tmu: tmu@100C0000 { 171 compatible = "samsung,exynos4210-tmu"; 172 interrupt-parent = <&combiner>; 173 reg = <0x100C0000 0x100>; 174 interrupts = <2 4>; 175 clocks = <&clock CLK_TMU_APBIF>; 176 clock-names = "tmu_apbif"; 177 samsung,tmu_gain = <15>; 178 samsung,tmu_reference_voltage = <7>; 179 status = "disabled"; 180 }; 181 182 thermal-zones { 183 cpu_thermal: cpu-thermal { 184 polling-delay-passive = <0>; 185 polling-delay = <0>; 186 thermal-sensors = <&tmu 0>; 187 188 trips { 189 cpu_alert0: cpu-alert-0 { 190 temperature = <85000>; /* millicelsius */ 191 }; 192 cpu_alert1: cpu-alert-1 { 193 temperature = <100000>; /* millicelsius */ 194 }; 195 cpu_alert2: cpu-alert-2 { 196 temperature = <110000>; /* millicelsius */ 197 }; 198 }; 199 }; 200 }; 201 202 g2d: g2d@12800000 { 203 compatible = "samsung,s5pv210-g2d"; 204 reg = <0x12800000 0x1000>; 205 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; 207 clock-names = "sclk_fimg2d", "fimg2d"; 208 power-domains = <&pd_lcd0>; 209 iommus = <&sysmmu_g2d>; 210 }; 211 212 camera { 213 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, 214 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; 215 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 216 217 fimc_0: fimc@11800000 { 218 samsung,pix-limits = <4224 8192 1920 4224>; 219 samsung,mainscaler-ext; 220 samsung,cam-if; 221 }; 222 223 fimc_1: fimc@11810000 { 224 samsung,pix-limits = <4224 8192 1920 4224>; 225 samsung,mainscaler-ext; 226 samsung,cam-if; 227 }; 228 229 fimc_2: fimc@11820000 { 230 samsung,pix-limits = <4224 8192 1920 4224>; 231 samsung,mainscaler-ext; 232 samsung,lcd-wb; 233 }; 234 235 fimc_3: fimc@11830000 { 236 samsung,pix-limits = <1920 8192 1366 1920>; 237 samsung,rotators = <0>; 238 samsung,mainscaler-ext; 239 samsung,lcd-wb; 240 }; 241 }; 242 243 mixer: mixer@12C10000 { 244 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer", 245 "sclk_mixer"; 246 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 247 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>, 248 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>; 249 }; 250 251 ppmu_lcd1: ppmu_lcd1@12240000 { 252 compatible = "samsung,exynos-ppmu"; 253 reg = <0x12240000 0x2000>; 254 clocks = <&clock CLK_PPMULCD1>; 255 clock-names = "ppmu"; 256 status = "disabled"; 257 }; 258 259 sysmmu_g2d: sysmmu@12A20000 { 260 compatible = "samsung,exynos-sysmmu"; 261 reg = <0x12A20000 0x1000>; 262 interrupt-parent = <&combiner>; 263 interrupts = <4 7>; 264 clock-names = "sysmmu", "master"; 265 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 266 power-domains = <&pd_lcd0>; 267 #iommu-cells = <0>; 268 }; 269 270 sysmmu_fimd1: sysmmu@12220000 { 271 compatible = "samsung,exynos-sysmmu"; 272 interrupt-parent = <&combiner>; 273 reg = <0x12220000 0x1000>; 274 interrupts = <5 3>; 275 clock-names = "sysmmu", "master"; 276 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; 277 power-domains = <&pd_lcd1>; 278 #iommu-cells = <0>; 279 }; 280 281 bus_dmc: bus_dmc { 282 compatible = "samsung,exynos-bus"; 283 clocks = <&clock CLK_DIV_DMC>; 284 clock-names = "bus"; 285 operating-points-v2 = <&bus_dmc_opp_table>; 286 status = "disabled"; 287 }; 288 289 bus_acp: bus_acp { 290 compatible = "samsung,exynos-bus"; 291 clocks = <&clock CLK_DIV_ACP>; 292 clock-names = "bus"; 293 operating-points-v2 = <&bus_acp_opp_table>; 294 status = "disabled"; 295 }; 296 297 bus_peri: bus_peri { 298 compatible = "samsung,exynos-bus"; 299 clocks = <&clock CLK_ACLK100>; 300 clock-names = "bus"; 301 operating-points-v2 = <&bus_peri_opp_table>; 302 status = "disabled"; 303 }; 304 305 bus_fsys: bus_fsys { 306 compatible = "samsung,exynos-bus"; 307 clocks = <&clock CLK_ACLK133>; 308 clock-names = "bus"; 309 operating-points-v2 = <&bus_fsys_opp_table>; 310 status = "disabled"; 311 }; 312 313 bus_display: bus_display { 314 compatible = "samsung,exynos-bus"; 315 clocks = <&clock CLK_ACLK160>; 316 clock-names = "bus"; 317 operating-points-v2 = <&bus_display_opp_table>; 318 status = "disabled"; 319 }; 320 321 bus_lcd0: bus_lcd0 { 322 compatible = "samsung,exynos-bus"; 323 clocks = <&clock CLK_ACLK200>; 324 clock-names = "bus"; 325 operating-points-v2 = <&bus_leftbus_opp_table>; 326 status = "disabled"; 327 }; 328 329 bus_leftbus: bus_leftbus { 330 compatible = "samsung,exynos-bus"; 331 clocks = <&clock CLK_DIV_GDL>; 332 clock-names = "bus"; 333 operating-points-v2 = <&bus_leftbus_opp_table>; 334 status = "disabled"; 335 }; 336 337 bus_rightbus: bus_rightbus { 338 compatible = "samsung,exynos-bus"; 339 clocks = <&clock CLK_DIV_GDR>; 340 clock-names = "bus"; 341 operating-points-v2 = <&bus_leftbus_opp_table>; 342 status = "disabled"; 343 }; 344 345 bus_mfc: bus_mfc { 346 compatible = "samsung,exynos-bus"; 347 clocks = <&clock CLK_SCLK_MFC>; 348 clock-names = "bus"; 349 operating-points-v2 = <&bus_leftbus_opp_table>; 350 status = "disabled"; 351 }; 352 353 bus_dmc_opp_table: opp_table1 { 354 compatible = "operating-points-v2"; 355 opp-shared; 356 357 opp-134000000 { 358 opp-hz = /bits/ 64 <134000000>; 359 opp-microvolt = <1025000>; 360 }; 361 opp-267000000 { 362 opp-hz = /bits/ 64 <267000000>; 363 opp-microvolt = <1050000>; 364 }; 365 opp-400000000 { 366 opp-hz = /bits/ 64 <400000000>; 367 opp-microvolt = <1150000>; 368 }; 369 }; 370 371 bus_acp_opp_table: opp_table2 { 372 compatible = "operating-points-v2"; 373 opp-shared; 374 375 opp-134000000 { 376 opp-hz = /bits/ 64 <134000000>; 377 }; 378 opp-160000000 { 379 opp-hz = /bits/ 64 <160000000>; 380 }; 381 opp-200000000 { 382 opp-hz = /bits/ 64 <200000000>; 383 }; 384 }; 385 386 bus_peri_opp_table: opp_table3 { 387 compatible = "operating-points-v2"; 388 opp-shared; 389 390 opp-5000000 { 391 opp-hz = /bits/ 64 <5000000>; 392 }; 393 opp-100000000 { 394 opp-hz = /bits/ 64 <100000000>; 395 }; 396 }; 397 398 bus_fsys_opp_table: opp_table4 { 399 compatible = "operating-points-v2"; 400 opp-shared; 401 402 opp-10000000 { 403 opp-hz = /bits/ 64 <10000000>; 404 }; 405 opp-134000000 { 406 opp-hz = /bits/ 64 <134000000>; 407 }; 408 }; 409 410 bus_display_opp_table: opp_table5 { 411 compatible = "operating-points-v2"; 412 opp-shared; 413 414 opp-100000000 { 415 opp-hz = /bits/ 64 <100000000>; 416 }; 417 opp-134000000 { 418 opp-hz = /bits/ 64 <134000000>; 419 }; 420 opp-160000000 { 421 opp-hz = /bits/ 64 <160000000>; 422 }; 423 }; 424 425 bus_leftbus_opp_table: opp_table6 { 426 compatible = "operating-points-v2"; 427 opp-shared; 428 429 opp-100000000 { 430 opp-hz = /bits/ 64 <100000000>; 431 }; 432 opp-160000000 { 433 opp-hz = /bits/ 64 <160000000>; 434 }; 435 opp-200000000 { 436 opp-hz = /bits/ 64 <200000000>; 437 }; 438 }; 439}; 440 441&gic { 442 cpu-offset = <0x8000>; 443}; 444 445&combiner { 446 samsung,combiner-nr = <16>; 447 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 463}; 464 465&mdma1 { 466 power-domains = <&pd_lcd0>; 467}; 468 469&pmu_system_controller { 470 clock-names = "clkout0", "clkout1", "clkout2", "clkout3", 471 "clkout4", "clkout8", "clkout9"; 472 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, 473 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, 474 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; 475 #clock-cells = <1>; 476}; 477 478&rotator { 479 power-domains = <&pd_lcd0>; 480}; 481 482&sysmmu_rotator { 483 power-domains = <&pd_lcd0>; 484}; 485