1/* 2 * Samsung's Exynos5 SoC series common device tree source 3 * 4 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular 8 * SoCs from Exynos5 series can include this file and provide values for SoCs 9 * specfic bindings. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/interrupt-controller/irq.h> 18#include "exynos-syscon-restart.dtsi" 19 20/ { 21 interrupt-parent = <&gic>; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 25 aliases { 26 i2c0 = &i2c_0; 27 i2c1 = &i2c_1; 28 i2c2 = &i2c_2; 29 i2c3 = &i2c_3; 30 serial0 = &serial_0; 31 serial1 = &serial_1; 32 serial2 = &serial_2; 33 serial3 = &serial_3; 34 }; 35 36 soc: soc { 37 compatible = "simple-bus"; 38 #address-cells = <1>; 39 #size-cells = <1>; 40 ranges; 41 42 chipid@10000000 { 43 compatible = "samsung,exynos4210-chipid"; 44 reg = <0x10000000 0x100>; 45 }; 46 47 sromc: memory-controller@12250000 { 48 compatible = "samsung,exynos4210-srom"; 49 reg = <0x12250000 0x14>; 50 }; 51 52 combiner: interrupt-controller@10440000 { 53 compatible = "samsung,exynos4210-combiner"; 54 #interrupt-cells = <2>; 55 interrupt-controller; 56 samsung,combiner-nr = <32>; 57 reg = <0x10440000 0x1000>; 58 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 90 }; 91 92 gic: interrupt-controller@10481000 { 93 compatible = "arm,gic-400", "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 94 #interrupt-cells = <3>; 95 interrupt-controller; 96 reg = <0x10481000 0x1000>, 97 <0x10482000 0x2000>, 98 <0x10484000 0x2000>, 99 <0x10486000 0x2000>; 100 interrupts = <GIC_PPI 9 101 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 102 }; 103 104 sysreg_system_controller: syscon@10050000 { 105 compatible = "samsung,exynos5-sysreg", "syscon"; 106 reg = <0x10050000 0x5000>; 107 }; 108 109 serial_0: serial@12C00000 { 110 compatible = "samsung,exynos4210-uart"; 111 reg = <0x12C00000 0x100>; 112 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 113 }; 114 115 serial_1: serial@12C10000 { 116 compatible = "samsung,exynos4210-uart"; 117 reg = <0x12C10000 0x100>; 118 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 119 }; 120 121 serial_2: serial@12C20000 { 122 compatible = "samsung,exynos4210-uart"; 123 reg = <0x12C20000 0x100>; 124 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 125 }; 126 127 serial_3: serial@12C30000 { 128 compatible = "samsung,exynos4210-uart"; 129 reg = <0x12C30000 0x100>; 130 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 131 }; 132 133 i2c_0: i2c@12C60000 { 134 compatible = "samsung,s3c2440-i2c"; 135 reg = <0x12C60000 0x100>; 136 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 samsung,sysreg-phandle = <&sysreg_system_controller>; 140 status = "disabled"; 141 }; 142 143 i2c_1: i2c@12C70000 { 144 compatible = "samsung,s3c2440-i2c"; 145 reg = <0x12C70000 0x100>; 146 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 samsung,sysreg-phandle = <&sysreg_system_controller>; 150 status = "disabled"; 151 }; 152 153 i2c_2: i2c@12C80000 { 154 compatible = "samsung,s3c2440-i2c"; 155 reg = <0x12C80000 0x100>; 156 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 samsung,sysreg-phandle = <&sysreg_system_controller>; 160 status = "disabled"; 161 }; 162 163 i2c_3: i2c@12C90000 { 164 compatible = "samsung,s3c2440-i2c"; 165 reg = <0x12C90000 0x100>; 166 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 samsung,sysreg-phandle = <&sysreg_system_controller>; 170 status = "disabled"; 171 }; 172 173 pwm: pwm@12DD0000 { 174 compatible = "samsung,exynos4210-pwm"; 175 reg = <0x12DD0000 0x100>; 176 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 177 #pwm-cells = <3>; 178 }; 179 180 rtc: rtc@101E0000 { 181 compatible = "samsung,s3c6410-rtc"; 182 reg = <0x101E0000 0x100>; 183 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 185 status = "disabled"; 186 }; 187 188 fimd: fimd@14400000 { 189 compatible = "samsung,exynos5250-fimd"; 190 interrupt-parent = <&combiner>; 191 reg = <0x14400000 0x40000>; 192 interrupt-names = "fifo", "vsync", "lcd_sys"; 193 interrupts = <18 4>, <18 5>, <18 6>; 194 samsung,sysreg = <&sysreg_system_controller>; 195 status = "disabled"; 196 }; 197 198 dp: dp-controller@145B0000 { 199 compatible = "samsung,exynos5-dp"; 200 reg = <0x145B0000 0x1000>; 201 interrupts = <10 3>; 202 interrupt-parent = <&combiner>; 203 #address-cells = <1>; 204 #size-cells = <0>; 205 status = "disabled"; 206 }; 207 }; 208}; 209