1/* 2 * SAMSUNG EXYNOS5410 SoC device tree source 3 * 4 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file. 8 * EXYNOS5410 based board files can include this file and provide 9 * values for board specfic bindings. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16#include "exynos54xx.dtsi" 17#include "exynos-syscon-restart.dtsi" 18#include <dt-bindings/clock/exynos5410.h> 19#include <dt-bindings/clock/exynos-audss-clk.h> 20#include <dt-bindings/interrupt-controller/arm-gic.h> 21 22/ { 23 compatible = "samsung,exynos5410", "samsung,exynos5"; 24 interrupt-parent = <&gic>; 25 26 aliases { 27 pinctrl0 = &pinctrl_0; 28 pinctrl1 = &pinctrl_1; 29 pinctrl2 = &pinctrl_2; 30 pinctrl3 = &pinctrl_3; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a15"; 40 reg = <0x0>; 41 clock-frequency = <1600000000>; 42 }; 43 44 cpu1: cpu@1 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a15"; 47 reg = <0x1>; 48 clock-frequency = <1600000000>; 49 }; 50 51 cpu2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a15"; 54 reg = <0x2>; 55 clock-frequency = <1600000000>; 56 }; 57 58 cpu3: cpu@3 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a15"; 61 reg = <0x3>; 62 clock-frequency = <1600000000>; 63 }; 64 }; 65 66 soc: soc { 67 compatible = "simple-bus"; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 ranges; 71 72 pmu_system_controller: system-controller@10040000 { 73 compatible = "samsung,exynos5410-pmu", "syscon"; 74 reg = <0x10040000 0x5000>; 75 clock-names = "clkout16"; 76 clocks = <&fin_pll>; 77 #clock-cells = <1>; 78 }; 79 80 clock: clock-controller@10010000 { 81 compatible = "samsung,exynos5410-clock"; 82 reg = <0x10010000 0x30000>; 83 #clock-cells = <1>; 84 }; 85 86 clock_audss: audss-clock-controller@3810000 { 87 compatible = "samsung,exynos5410-audss-clock"; 88 reg = <0x03810000 0x0C>; 89 #clock-cells = <1>; 90 clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>; 91 clock-names = "pll_ref", "pll_in"; 92 }; 93 94 tmu_cpu0: tmu@10060000 { 95 compatible = "samsung,exynos5420-tmu"; 96 reg = <0x10060000 0x100>; 97 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&clock CLK_TMU>; 99 clock-names = "tmu_apbif"; 100 #include "exynos4412-tmu-sensor-conf.dtsi" 101 }; 102 103 tmu_cpu1: tmu@10064000 { 104 compatible = "samsung,exynos5420-tmu"; 105 reg = <0x10064000 0x100>; 106 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&clock CLK_TMU>; 108 clock-names = "tmu_apbif"; 109 #include "exynos4412-tmu-sensor-conf.dtsi" 110 }; 111 112 tmu_cpu2: tmu@10068000 { 113 compatible = "samsung,exynos5420-tmu"; 114 reg = <0x10068000 0x100>; 115 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 116 clocks = <&clock CLK_TMU>; 117 clock-names = "tmu_apbif"; 118 #include "exynos4412-tmu-sensor-conf.dtsi" 119 }; 120 121 tmu_cpu3: tmu@1006c000 { 122 compatible = "samsung,exynos5420-tmu"; 123 reg = <0x1006c000 0x100>; 124 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&clock CLK_TMU>; 126 clock-names = "tmu_apbif"; 127 #include "exynos4412-tmu-sensor-conf.dtsi" 128 }; 129 130 mmc_0: mmc@12200000 { 131 compatible = "samsung,exynos5250-dw-mshc"; 132 reg = <0x12200000 0x1000>; 133 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 134 #address-cells = <1>; 135 #size-cells = <0>; 136 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; 137 clock-names = "biu", "ciu"; 138 fifo-depth = <0x80>; 139 status = "disabled"; 140 }; 141 142 mmc_1: mmc@12210000 { 143 compatible = "samsung,exynos5250-dw-mshc"; 144 reg = <0x12210000 0x1000>; 145 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; 149 clock-names = "biu", "ciu"; 150 fifo-depth = <0x80>; 151 status = "disabled"; 152 }; 153 154 mmc_2: mmc@12220000 { 155 compatible = "samsung,exynos5250-dw-mshc"; 156 reg = <0x12220000 0x1000>; 157 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 158 #address-cells = <1>; 159 #size-cells = <0>; 160 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; 161 clock-names = "biu", "ciu"; 162 fifo-depth = <0x80>; 163 status = "disabled"; 164 }; 165 166 pinctrl_0: pinctrl@13400000 { 167 compatible = "samsung,exynos5410-pinctrl"; 168 reg = <0x13400000 0x1000>; 169 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 170 171 wakeup-interrupt-controller { 172 compatible = "samsung,exynos4210-wakeup-eint"; 173 interrupt-parent = <&gic>; 174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 175 }; 176 }; 177 178 pinctrl_1: pinctrl@14000000 { 179 compatible = "samsung,exynos5410-pinctrl"; 180 reg = <0x14000000 0x1000>; 181 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 182 }; 183 184 pinctrl_2: pinctrl@10d10000 { 185 compatible = "samsung,exynos5410-pinctrl"; 186 reg = <0x10d10000 0x1000>; 187 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 188 }; 189 190 pinctrl_3: pinctrl@03860000 { 191 compatible = "samsung,exynos5410-pinctrl"; 192 reg = <0x03860000 0x1000>; 193 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 194 }; 195 196 amba { 197 #address-cells = <1>; 198 #size-cells = <1>; 199 compatible = "simple-bus"; 200 interrupt-parent = <&gic>; 201 ranges; 202 203 pdma0: pdma@12680000 { 204 compatible = "arm,pl330", "arm,primecell"; 205 reg = <0x121A0000 0x1000>; 206 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&clock CLK_PDMA0>; 208 clock-names = "apb_pclk"; 209 #dma-cells = <1>; 210 #dma-channels = <8>; 211 #dma-requests = <32>; 212 }; 213 214 pdma1: pdma@12690000 { 215 compatible = "arm,pl330", "arm,primecell"; 216 reg = <0x121B0000 0x1000>; 217 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&clock CLK_PDMA1>; 219 clock-names = "apb_pclk"; 220 #dma-cells = <1>; 221 #dma-channels = <8>; 222 #dma-requests = <32>; 223 }; 224 }; 225 226 audi2s0: i2s@03830000 { 227 compatible = "samsung,exynos5420-i2s"; 228 reg = <0x03830000 0x100>; 229 dmas = <&pdma0 10 230 &pdma0 9 231 &pdma0 8>; 232 dma-names = "tx", "rx", "tx-sec"; 233 clocks = <&clock_audss EXYNOS_I2S_BUS>, 234 <&clock_audss EXYNOS_I2S_BUS>, 235 <&clock_audss EXYNOS_SCLK_I2S>; 236 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 237 #clock-cells = <1>; 238 clock-output-names = "i2s_cdclk0"; 239 #sound-dai-cells = <1>; 240 samsung,idma-addr = <0x03000000>; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&audi2s0_bus>; 243 status = "disabled"; 244 }; 245 }; 246 247 thermal-zones { 248 cpu0_thermal: cpu0-thermal { 249 thermal-sensors = <&tmu_cpu0>; 250 #include "exynos5420-trip-points.dtsi" 251 }; 252 cpu1_thermal: cpu1-thermal { 253 thermal-sensors = <&tmu_cpu1>; 254 #include "exynos5420-trip-points.dtsi" 255 }; 256 cpu2_thermal: cpu2-thermal { 257 thermal-sensors = <&tmu_cpu2>; 258 #include "exynos5420-trip-points.dtsi" 259 }; 260 cpu3_thermal: cpu3-thermal { 261 thermal-sensors = <&tmu_cpu3>; 262 #include "exynos5420-trip-points.dtsi" 263 }; 264 }; 265}; 266 267&i2c_0 { 268 clocks = <&clock CLK_I2C0>; 269 clock-names = "i2c"; 270 pinctrl-names = "default"; 271 pinctrl-0 = <&i2c0_bus>; 272}; 273 274&i2c_1 { 275 clocks = <&clock CLK_I2C1>; 276 clock-names = "i2c"; 277 pinctrl-names = "default"; 278 pinctrl-0 = <&i2c1_bus>; 279}; 280 281&i2c_2 { 282 clocks = <&clock CLK_I2C2>; 283 clock-names = "i2c"; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&i2c2_bus>; 286}; 287 288&i2c_3 { 289 clocks = <&clock CLK_I2C3>; 290 clock-names = "i2c"; 291 pinctrl-names = "default"; 292 pinctrl-0 = <&i2c3_bus>; 293}; 294 295&hsi2c_4 { 296 clocks = <&clock CLK_USI0>; 297 clock-names = "hsi2c"; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&i2c4_hs_bus>; 300}; 301 302&hsi2c_5 { 303 clocks = <&clock CLK_USI1>; 304 clock-names = "hsi2c"; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&i2c5_hs_bus>; 307}; 308 309&hsi2c_6 { 310 clocks = <&clock CLK_USI2>; 311 clock-names = "hsi2c"; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&i2c6_hs_bus>; 314}; 315 316&hsi2c_7 { 317 clocks = <&clock CLK_USI3>; 318 clock-names = "hsi2c"; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&i2c7_hs_bus>; 321}; 322 323&mct { 324 clocks = <&fin_pll>, <&clock CLK_MCT>; 325 clock-names = "fin_pll", "mct"; 326}; 327 328&pwm { 329 clocks = <&clock CLK_PWM>; 330 clock-names = "timers"; 331}; 332 333&rtc { 334 clocks = <&clock CLK_RTC>; 335 clock-names = "rtc"; 336 status = "disabled"; 337}; 338 339&serial_0 { 340 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 341 clock-names = "uart", "clk_uart_baud0"; 342 dmas = <&pdma0 13>, <&pdma0 14>; 343 dma-names = "rx", "tx"; 344}; 345 346&serial_1 { 347 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 348 clock-names = "uart", "clk_uart_baud0"; 349 dmas = <&pdma1 15>, <&pdma1 16>; 350 dma-names = "rx", "tx"; 351}; 352 353&serial_2 { 354 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 355 clock-names = "uart", "clk_uart_baud0"; 356 dmas = <&pdma0 15>, <&pdma0 16>; 357 dma-names = "rx", "tx"; 358}; 359 360&serial_3 { 361 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 362 clock-names = "uart", "clk_uart_baud0"; 363 dmas = <&pdma1 17>, <&pdma1 18>; 364 dma-names = "rx", "tx"; 365}; 366 367&sss { 368 clocks = <&clock CLK_SSS>; 369 clock-names = "secss"; 370}; 371 372&sromc { 373 #address-cells = <2>; 374 #size-cells = <1>; 375 ranges = <0 0 0x04000000 0x20000 376 1 0 0x05000000 0x20000 377 2 0 0x06000000 0x20000 378 3 0 0x07000000 0x20000>; 379}; 380 381&usbdrd3_0 { 382 clocks = <&clock CLK_USBD300>; 383 clock-names = "usbdrd30"; 384}; 385 386&usbdrd_phy0 { 387 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; 388 clock-names = "phy", "ref"; 389 samsung,pmu-syscon = <&pmu_system_controller>; 390}; 391 392&usbdrd3_1 { 393 clocks = <&clock CLK_USBD301>; 394 clock-names = "usbdrd30"; 395}; 396 397&usbdrd_dwc3_1 { 398 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 399}; 400 401&usbdrd_phy1 { 402 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; 403 clock-names = "phy", "ref"; 404 samsung,pmu-syscon = <&pmu_system_controller>; 405}; 406 407&usbhost1 { 408 clocks = <&clock CLK_USBH20>; 409 clock-names = "usbhost"; 410}; 411 412&usbhost2 { 413 clocks = <&clock CLK_USBH20>; 414 clock-names = "usbhost"; 415}; 416 417&usb2_phy { 418 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; 419 clock-names = "phy", "ref"; 420 samsung,sysreg-phandle = <&sysreg_system_controller>; 421 samsung,pmureg-phandle = <&pmu_system_controller>; 422}; 423 424&watchdog { 425 clocks = <&clock CLK_WDT>; 426 clock-names = "watchdog"; 427 samsung,syscon-phandle = <&pmu_system_controller>; 428}; 429 430#include "exynos5410-pinctrl.dtsi" 431