1/* 2 * Copyright 2012 Sascha Hauer, Pengutronix 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License. You may obtain a copy of the GNU General Public License 6 * Version 2 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.gnu.org/copyleft/gpl.html 10 */ 11 12/dts-v1/; 13#include "imx27.dtsi" 14 15/ { 16 model = "Phytec pcm038"; 17 compatible = "phytec,imx27-pcm038", "fsl,imx27"; 18 19 memory { 20 reg = <0xa0000000 0x08000000>; 21 }; 22 23 regulators { 24 compatible = "simple-bus"; 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 reg_3v3: regulator@0 { 29 compatible = "regulator-fixed"; 30 reg = <0>; 31 regulator-name = "3V3"; 32 regulator-min-microvolt = <3300000>; 33 regulator-max-microvolt = <3300000>; 34 }; 35 36 reg_5v0: regulator@1 { 37 compatible = "regulator-fixed"; 38 reg = <1>; 39 regulator-name = "5V0"; 40 regulator-min-microvolt = <5000000>; 41 regulator-max-microvolt = <5000000>; 42 }; 43 }; 44 45 usbphy { 46 compatible = "simple-bus"; 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 usbphy0: usbphy@0 { 51 compatible = "usb-nop-xceiv"; 52 reg = <0>; 53 vcc-supply = <&sw3_reg>; 54 clocks = <&clks IMX27_CLK_DUMMY>; 55 clock-names = "main_clk"; 56 }; 57 }; 58}; 59 60&audmux { 61 status = "okay"; 62 63 /* SSI0 <=> PINS_4 (MC13783 Audio) */ 64 ssi0 { 65 fsl,audmux-port = <0>; 66 fsl,port-config = <0xcb205000>; 67 }; 68 69 pins4 { 70 fsl,audmux-port = <2>; 71 fsl,port-config = <0x00001000>; 72 }; 73}; 74 75&cspi1 { 76 pinctrl-names = "default"; 77 pinctrl-0 = <&pinctrl_cspi1>; 78 cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 79 status = "okay"; 80 81 pmic: mc13783@0 { 82 compatible = "fsl,mc13783"; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&pinctrl_pmic>; 85 reg = <0>; 86 spi-cs-high; 87 spi-max-frequency = <20000000>; 88 interrupt-parent = <&gpio2>; 89 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 90 fsl,mc13xxx-uses-adc; 91 fsl,mc13xxx-uses-rtc; 92 93 pmicleds: leds { 94 #address-cells = <1>; 95 #size-cells = <0>; 96 led-control = <0x001 0x000 0x000 0x000 0x000 0x000>; 97 }; 98 99 regulators { 100 /* SW1A and SW1B joined operation */ 101 sw1_reg: sw1a { 102 regulator-min-microvolt = <1200000>; 103 regulator-max-microvolt = <1520000>; 104 regulator-always-on; 105 regulator-boot-on; 106 }; 107 108 /* SW2A and SW2B joined operation */ 109 sw2_reg: sw2a { 110 regulator-min-microvolt = <1800000>; 111 regulator-max-microvolt = <1800000>; 112 regulator-always-on; 113 regulator-boot-on; 114 }; 115 116 sw3_reg: sw3 { 117 regulator-min-microvolt = <5000000>; 118 regulator-max-microvolt = <5000000>; 119 regulator-always-on; 120 regulator-boot-on; 121 }; 122 123 vaudio_reg: vaudio { 124 regulator-always-on; 125 regulator-boot-on; 126 }; 127 128 violo_reg: violo { 129 regulator-min-microvolt = <1800000>; 130 regulator-max-microvolt = <1800000>; 131 regulator-always-on; 132 regulator-boot-on; 133 }; 134 135 viohi_reg: viohi { 136 regulator-always-on; 137 regulator-boot-on; 138 }; 139 140 vgen_reg: vgen { 141 regulator-min-microvolt = <1500000>; 142 regulator-max-microvolt = <1500000>; 143 regulator-always-on; 144 regulator-boot-on; 145 }; 146 147 vcam_reg: vcam { 148 regulator-min-microvolt = <2800000>; 149 regulator-max-microvolt = <2800000>; 150 }; 151 152 vrf1_reg: vrf1 { 153 regulator-min-microvolt = <2775000>; 154 regulator-max-microvolt = <2775000>; 155 regulator-always-on; 156 regulator-boot-on; 157 }; 158 159 vrf2_reg: vrf2 { 160 regulator-min-microvolt = <2775000>; 161 regulator-max-microvolt = <2775000>; 162 regulator-always-on; 163 regulator-boot-on; 164 }; 165 166 vmmc1_reg: vmmc1 { 167 regulator-min-microvolt = <1600000>; 168 regulator-max-microvolt = <3000000>; 169 }; 170 171 gpo1_reg: gpo1 { }; 172 173 pwgt1spi_reg: pwgt1spi { 174 regulator-always-on; 175 }; 176 }; 177 }; 178}; 179 180&fec { 181 phy-mode = "mii"; 182 phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; 183 phy-supply = <®_3v3>; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_fec1>; 186 status = "okay"; 187}; 188 189&i2c2 { 190 clock-frequency = <400000>; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_i2c2>; 193 status = "okay"; 194 195 at24@52 { 196 compatible = "atmel,24c32"; 197 pagesize = <32>; 198 reg = <0x52>; 199 }; 200 201 pcf8563@51 { 202 compatible = "nxp,pcf8563"; 203 reg = <0x51>; 204 }; 205 206 lm75@4a { 207 compatible = "national,lm75"; 208 reg = <0x4a>; 209 }; 210}; 211 212&iomuxc { 213 imx27_phycore_som { 214 pinctrl_cspi1: cspi1grp { 215 fsl,pins = < 216 MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 217 MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 218 MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 219 MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ 220 >; 221 }; 222 223 pinctrl_fec1: fec1grp { 224 fsl,pins = < 225 MX27_PAD_SD3_CMD__FEC_TXD0 0x0 226 MX27_PAD_SD3_CLK__FEC_TXD1 0x0 227 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 228 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 229 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 230 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 231 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 232 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 233 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 234 MX27_PAD_ATA_DATA7__FEC_MDC 0x0 235 MX27_PAD_ATA_DATA8__FEC_CRS 0x0 236 MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 237 MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 238 MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 239 MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 240 MX27_PAD_ATA_DATA13__FEC_COL 0x0 241 MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 242 MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 243 MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */ 244 >; 245 }; 246 247 pinctrl_i2c2: i2c2grp { 248 fsl,pins = < 249 MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 250 MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 251 >; 252 }; 253 254 pinctrl_nfc: nfcgrp { 255 fsl,pins = < 256 MX27_PAD_NFRB__NFRB 0x0 257 MX27_PAD_NFCLE__NFCLE 0x0 258 MX27_PAD_NFWP_B__NFWP_B 0x0 259 MX27_PAD_NFCE_B__NFCE_B 0x0 260 MX27_PAD_NFALE__NFALE 0x0 261 MX27_PAD_NFRE_B__NFRE_B 0x0 262 MX27_PAD_NFWE_B__NFWE_B 0x0 263 >; 264 }; 265 266 pinctrl_pmic: pmicgrp { 267 fsl,pins = < 268 MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ 269 >; 270 }; 271 272 pinctrl_ssi1: ssi1grp { 273 fsl,pins = < 274 MX27_PAD_SSI1_FS__SSI1_FS 0x0 275 MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0 276 MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0 277 MX27_PAD_SSI1_CLK__SSI1_CLK 0x0 278 >; 279 }; 280 281 pinctrl_usbotg: usbotggrp { 282 fsl,pins = < 283 MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 284 MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 285 MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 286 MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 287 MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 288 MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 289 MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 290 MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 291 MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 292 MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 293 MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 294 MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 295 >; 296 }; 297 }; 298}; 299 300&nfc { 301 pinctrl-names = "default"; 302 pinctrl-0 = <&pinctrl_nfc>; 303 nand-bus-width = <8>; 304 nand-ecc-mode = "hw"; 305 nand-on-flash-bbt; 306 status = "okay"; 307}; 308 309&ssi1 { 310 pinctrl-names = "default"; 311 pinctrl-0 = <&pinctrl_ssi1>; 312 status = "okay"; 313}; 314 315&usbotg { 316 pinctrl-names = "default"; 317 pinctrl-0 = <&pinctrl_usbotg>; 318 dr_mode = "otg"; 319 phy_type = "ulpi"; 320 fsl,usbphy = <&usbphy0>; 321 vbus-supply = <&sw3_reg>; 322 disable-over-current; 323 status = "okay"; 324}; 325 326&weim { 327 status = "okay"; 328 329 nor: nor@0,0 { 330 compatible = "cfi-flash"; 331 reg = <0 0x00000000 0x02000000>; 332 bank-width = <2>; 333 linux,mtd-name = "physmap-flash.0"; 334 fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>; 335 #address-cells = <1>; 336 #size-cells = <1>; 337 }; 338 339 sram: sram@1,0 { 340 compatible = "mtd-ram"; 341 reg = <1 0x00000000 0x00800000>; 342 bank-width = <2>; 343 linux,mtd-name = "mtd-ram.0"; 344 fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>; 345 #address-cells = <1>; 346 #size-cells = <1>; 347 }; 348}; 349