1/* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13#include "imx53-pinfunc.h" 14#include <dt-bindings/clock/imx5-clock.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/input/input.h> 17#include <dt-bindings/interrupt-controller/irq.h> 18 19/ { 20 #address-cells = <1>; 21 #size-cells = <1>; 22 /* 23 * The decompressor and also some bootloaders rely on a 24 * pre-existing /chosen node to be available to insert the 25 * command line and merge other ATAGS info. 26 * Also for U-Boot there must be a pre-existing /memory node. 27 */ 28 chosen {}; 29 memory { device_type = "memory"; reg = <0 0>; }; 30 31 aliases { 32 ethernet0 = &fec; 33 gpio0 = &gpio1; 34 gpio1 = &gpio2; 35 gpio2 = &gpio3; 36 gpio3 = &gpio4; 37 gpio4 = &gpio5; 38 gpio5 = &gpio6; 39 gpio6 = &gpio7; 40 i2c0 = &i2c1; 41 i2c1 = &i2c2; 42 i2c2 = &i2c3; 43 mmc0 = &esdhc1; 44 mmc1 = &esdhc2; 45 mmc2 = &esdhc3; 46 mmc3 = &esdhc4; 47 serial0 = &uart1; 48 serial1 = &uart2; 49 serial2 = &uart3; 50 serial3 = &uart4; 51 serial4 = &uart5; 52 spi0 = &ecspi1; 53 spi1 = &ecspi2; 54 spi2 = &cspi; 55 }; 56 57 cpus { 58 #address-cells = <1>; 59 #size-cells = <0>; 60 cpu0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a8"; 63 reg = <0x0>; 64 clocks = <&clks IMX5_CLK_ARM>; 65 clock-latency = <61036>; 66 voltage-tolerance = <5>; 67 operating-points = < 68 /* kHz */ 69 166666 850000 70 400000 900000 71 800000 1050000 72 1000000 1200000 73 1200000 1300000 74 >; 75 }; 76 }; 77 78 display-subsystem { 79 compatible = "fsl,imx-display-subsystem"; 80 ports = <&ipu_di0>, <&ipu_di1>; 81 }; 82 83 tzic: tz-interrupt-controller@0fffc000 { 84 compatible = "fsl,imx53-tzic", "fsl,tzic"; 85 interrupt-controller; 86 #interrupt-cells = <1>; 87 reg = <0x0fffc000 0x4000>; 88 }; 89 90 clocks { 91 #address-cells = <1>; 92 #size-cells = <0>; 93 94 ckil { 95 compatible = "fsl,imx-ckil", "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <32768>; 98 }; 99 100 ckih1 { 101 compatible = "fsl,imx-ckih1", "fixed-clock"; 102 #clock-cells = <0>; 103 clock-frequency = <22579200>; 104 }; 105 106 ckih2 { 107 compatible = "fsl,imx-ckih2", "fixed-clock"; 108 #clock-cells = <0>; 109 clock-frequency = <0>; 110 }; 111 112 osc { 113 compatible = "fsl,imx-osc", "fixed-clock"; 114 #clock-cells = <0>; 115 clock-frequency = <24000000>; 116 }; 117 }; 118 119 soc { 120 #address-cells = <1>; 121 #size-cells = <1>; 122 compatible = "simple-bus"; 123 interrupt-parent = <&tzic>; 124 ranges; 125 126 sata: sata@10000000 { 127 compatible = "fsl,imx53-ahci"; 128 reg = <0x10000000 0x1000>; 129 interrupts = <28>; 130 clocks = <&clks IMX5_CLK_SATA_GATE>, 131 <&clks IMX5_CLK_SATA_REF>, 132 <&clks IMX5_CLK_AHB>; 133 clock-names = "sata", "sata_ref", "ahb"; 134 status = "disabled"; 135 }; 136 137 ipu: ipu@18000000 { 138 #address-cells = <1>; 139 #size-cells = <0>; 140 compatible = "fsl,imx53-ipu"; 141 reg = <0x18000000 0x08000000>; 142 interrupts = <11 10>; 143 clocks = <&clks IMX5_CLK_IPU_GATE>, 144 <&clks IMX5_CLK_IPU_DI0_GATE>, 145 <&clks IMX5_CLK_IPU_DI1_GATE>; 146 clock-names = "bus", "di0", "di1"; 147 resets = <&src 2>; 148 149 ipu_csi0: port@0 { 150 reg = <0>; 151 }; 152 153 ipu_csi1: port@1 { 154 reg = <1>; 155 }; 156 157 ipu_di0: port@2 { 158 #address-cells = <1>; 159 #size-cells = <0>; 160 reg = <2>; 161 162 ipu_di0_disp0: endpoint@0 { 163 reg = <0>; 164 }; 165 166 ipu_di0_lvds0: endpoint@1 { 167 reg = <1>; 168 remote-endpoint = <&lvds0_in>; 169 }; 170 }; 171 172 ipu_di1: port@3 { 173 #address-cells = <1>; 174 #size-cells = <0>; 175 reg = <3>; 176 177 ipu_di1_disp1: endpoint@0 { 178 reg = <0>; 179 }; 180 181 ipu_di1_lvds1: endpoint@1 { 182 reg = <1>; 183 remote-endpoint = <&lvds1_in>; 184 }; 185 186 ipu_di1_tve: endpoint@2 { 187 reg = <2>; 188 remote-endpoint = <&tve_in>; 189 }; 190 }; 191 }; 192 193 aips@50000000 { /* AIPS1 */ 194 compatible = "fsl,aips-bus", "simple-bus"; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 reg = <0x50000000 0x10000000>; 198 ranges; 199 200 spba@50000000 { 201 compatible = "fsl,spba-bus", "simple-bus"; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 reg = <0x50000000 0x40000>; 205 ranges; 206 207 esdhc1: esdhc@50004000 { 208 compatible = "fsl,imx53-esdhc"; 209 reg = <0x50004000 0x4000>; 210 interrupts = <1>; 211 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, 212 <&clks IMX5_CLK_DUMMY>, 213 <&clks IMX5_CLK_ESDHC1_PER_GATE>; 214 clock-names = "ipg", "ahb", "per"; 215 bus-width = <4>; 216 status = "disabled"; 217 }; 218 219 esdhc2: esdhc@50008000 { 220 compatible = "fsl,imx53-esdhc"; 221 reg = <0x50008000 0x4000>; 222 interrupts = <2>; 223 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, 224 <&clks IMX5_CLK_DUMMY>, 225 <&clks IMX5_CLK_ESDHC2_PER_GATE>; 226 clock-names = "ipg", "ahb", "per"; 227 bus-width = <4>; 228 status = "disabled"; 229 }; 230 231 uart3: serial@5000c000 { 232 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 233 reg = <0x5000c000 0x4000>; 234 interrupts = <33>; 235 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, 236 <&clks IMX5_CLK_UART3_PER_GATE>; 237 clock-names = "ipg", "per"; 238 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; 239 dma-names = "rx", "tx"; 240 status = "disabled"; 241 }; 242 243 ecspi1: ecspi@50010000 { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 247 reg = <0x50010000 0x4000>; 248 interrupts = <36>; 249 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, 250 <&clks IMX5_CLK_ECSPI1_PER_GATE>; 251 clock-names = "ipg", "per"; 252 status = "disabled"; 253 }; 254 255 ssi2: ssi@50014000 { 256 #sound-dai-cells = <0>; 257 compatible = "fsl,imx53-ssi", 258 "fsl,imx51-ssi", 259 "fsl,imx21-ssi"; 260 reg = <0x50014000 0x4000>; 261 interrupts = <30>; 262 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, 263 <&clks IMX5_CLK_SSI2_ROOT_GATE>; 264 clock-names = "ipg", "baud"; 265 dmas = <&sdma 24 1 0>, 266 <&sdma 25 1 0>; 267 dma-names = "rx", "tx"; 268 fsl,fifo-depth = <15>; 269 status = "disabled"; 270 }; 271 272 esdhc3: esdhc@50020000 { 273 compatible = "fsl,imx53-esdhc"; 274 reg = <0x50020000 0x4000>; 275 interrupts = <3>; 276 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, 277 <&clks IMX5_CLK_DUMMY>, 278 <&clks IMX5_CLK_ESDHC3_PER_GATE>; 279 clock-names = "ipg", "ahb", "per"; 280 bus-width = <4>; 281 status = "disabled"; 282 }; 283 284 esdhc4: esdhc@50024000 { 285 compatible = "fsl,imx53-esdhc"; 286 reg = <0x50024000 0x4000>; 287 interrupts = <4>; 288 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, 289 <&clks IMX5_CLK_DUMMY>, 290 <&clks IMX5_CLK_ESDHC4_PER_GATE>; 291 clock-names = "ipg", "ahb", "per"; 292 bus-width = <4>; 293 status = "disabled"; 294 }; 295 }; 296 297 aipstz1: bridge@53f00000 { 298 compatible = "fsl,imx53-aipstz"; 299 reg = <0x53f00000 0x60>; 300 }; 301 302 usbphy0: usbphy@0 { 303 compatible = "usb-nop-xceiv"; 304 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; 305 clock-names = "main_clk"; 306 status = "okay"; 307 }; 308 309 usbphy1: usbphy@1 { 310 compatible = "usb-nop-xceiv"; 311 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; 312 clock-names = "main_clk"; 313 status = "okay"; 314 }; 315 316 usbotg: usb@53f80000 { 317 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 318 reg = <0x53f80000 0x0200>; 319 interrupts = <18>; 320 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 321 fsl,usbmisc = <&usbmisc 0>; 322 fsl,usbphy = <&usbphy0>; 323 status = "disabled"; 324 }; 325 326 usbh1: usb@53f80200 { 327 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 328 reg = <0x53f80200 0x0200>; 329 interrupts = <14>; 330 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 331 fsl,usbmisc = <&usbmisc 1>; 332 fsl,usbphy = <&usbphy1>; 333 dr_mode = "host"; 334 status = "disabled"; 335 }; 336 337 usbh2: usb@53f80400 { 338 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 339 reg = <0x53f80400 0x0200>; 340 interrupts = <16>; 341 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 342 fsl,usbmisc = <&usbmisc 2>; 343 dr_mode = "host"; 344 status = "disabled"; 345 }; 346 347 usbh3: usb@53f80600 { 348 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 349 reg = <0x53f80600 0x0200>; 350 interrupts = <17>; 351 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 352 fsl,usbmisc = <&usbmisc 3>; 353 dr_mode = "host"; 354 status = "disabled"; 355 }; 356 357 usbmisc: usbmisc@53f80800 { 358 #index-cells = <1>; 359 compatible = "fsl,imx53-usbmisc"; 360 reg = <0x53f80800 0x200>; 361 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 362 }; 363 364 gpio1: gpio@53f84000 { 365 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 366 reg = <0x53f84000 0x4000>; 367 interrupts = <50 51>; 368 gpio-controller; 369 #gpio-cells = <2>; 370 interrupt-controller; 371 #interrupt-cells = <2>; 372 }; 373 374 gpio2: gpio@53f88000 { 375 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 376 reg = <0x53f88000 0x4000>; 377 interrupts = <52 53>; 378 gpio-controller; 379 #gpio-cells = <2>; 380 interrupt-controller; 381 #interrupt-cells = <2>; 382 }; 383 384 gpio3: gpio@53f8c000 { 385 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 386 reg = <0x53f8c000 0x4000>; 387 interrupts = <54 55>; 388 gpio-controller; 389 #gpio-cells = <2>; 390 interrupt-controller; 391 #interrupt-cells = <2>; 392 }; 393 394 gpio4: gpio@53f90000 { 395 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 396 reg = <0x53f90000 0x4000>; 397 interrupts = <56 57>; 398 gpio-controller; 399 #gpio-cells = <2>; 400 interrupt-controller; 401 #interrupt-cells = <2>; 402 }; 403 404 kpp: kpp@53f94000 { 405 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; 406 reg = <0x53f94000 0x4000>; 407 interrupts = <60>; 408 clocks = <&clks IMX5_CLK_DUMMY>; 409 status = "disabled"; 410 }; 411 412 wdog1: wdog@53f98000 { 413 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 414 reg = <0x53f98000 0x4000>; 415 interrupts = <58>; 416 clocks = <&clks IMX5_CLK_DUMMY>; 417 }; 418 419 wdog2: wdog@53f9c000 { 420 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 421 reg = <0x53f9c000 0x4000>; 422 interrupts = <59>; 423 clocks = <&clks IMX5_CLK_DUMMY>; 424 status = "disabled"; 425 }; 426 427 gpt: timer@53fa0000 { 428 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; 429 reg = <0x53fa0000 0x4000>; 430 interrupts = <39>; 431 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, 432 <&clks IMX5_CLK_GPT_HF_GATE>; 433 clock-names = "ipg", "per"; 434 }; 435 436 iomuxc: iomuxc@53fa8000 { 437 compatible = "fsl,imx53-iomuxc"; 438 reg = <0x53fa8000 0x4000>; 439 }; 440 441 gpr: iomuxc-gpr@53fa8000 { 442 compatible = "fsl,imx53-iomuxc-gpr", "syscon"; 443 reg = <0x53fa8000 0xc>; 444 }; 445 446 ldb: ldb@53fa8008 { 447 #address-cells = <1>; 448 #size-cells = <0>; 449 compatible = "fsl,imx53-ldb"; 450 reg = <0x53fa8008 0x4>; 451 gpr = <&gpr>; 452 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, 453 <&clks IMX5_CLK_LDB_DI1_SEL>, 454 <&clks IMX5_CLK_IPU_DI0_SEL>, 455 <&clks IMX5_CLK_IPU_DI1_SEL>, 456 <&clks IMX5_CLK_LDB_DI0_GATE>, 457 <&clks IMX5_CLK_LDB_DI1_GATE>; 458 clock-names = "di0_pll", "di1_pll", 459 "di0_sel", "di1_sel", 460 "di0", "di1"; 461 status = "disabled"; 462 463 lvds-channel@0 { 464 #address-cells = <1>; 465 #size-cells = <0>; 466 reg = <0>; 467 status = "disabled"; 468 469 port@0 { 470 reg = <0>; 471 472 lvds0_in: endpoint { 473 remote-endpoint = <&ipu_di0_lvds0>; 474 }; 475 }; 476 }; 477 478 lvds-channel@1 { 479 #address-cells = <1>; 480 #size-cells = <0>; 481 reg = <1>; 482 status = "disabled"; 483 484 port@1 { 485 reg = <1>; 486 487 lvds1_in: endpoint { 488 remote-endpoint = <&ipu_di1_lvds1>; 489 }; 490 }; 491 }; 492 }; 493 494 pwm1: pwm@53fb4000 { 495 #pwm-cells = <2>; 496 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; 497 reg = <0x53fb4000 0x4000>; 498 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, 499 <&clks IMX5_CLK_PWM1_HF_GATE>; 500 clock-names = "ipg", "per"; 501 interrupts = <61>; 502 }; 503 504 pwm2: pwm@53fb8000 { 505 #pwm-cells = <2>; 506 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; 507 reg = <0x53fb8000 0x4000>; 508 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, 509 <&clks IMX5_CLK_PWM2_HF_GATE>; 510 clock-names = "ipg", "per"; 511 interrupts = <94>; 512 }; 513 514 uart1: serial@53fbc000 { 515 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 516 reg = <0x53fbc000 0x4000>; 517 interrupts = <31>; 518 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, 519 <&clks IMX5_CLK_UART1_PER_GATE>; 520 clock-names = "ipg", "per"; 521 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; 522 dma-names = "rx", "tx"; 523 status = "disabled"; 524 }; 525 526 uart2: serial@53fc0000 { 527 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 528 reg = <0x53fc0000 0x4000>; 529 interrupts = <32>; 530 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, 531 <&clks IMX5_CLK_UART2_PER_GATE>; 532 clock-names = "ipg", "per"; 533 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; 534 dma-names = "rx", "tx"; 535 status = "disabled"; 536 }; 537 538 can1: can@53fc8000 { 539 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 540 reg = <0x53fc8000 0x4000>; 541 interrupts = <82>; 542 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, 543 <&clks IMX5_CLK_CAN1_SERIAL_GATE>; 544 clock-names = "ipg", "per"; 545 status = "disabled"; 546 }; 547 548 can2: can@53fcc000 { 549 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 550 reg = <0x53fcc000 0x4000>; 551 interrupts = <83>; 552 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, 553 <&clks IMX5_CLK_CAN2_SERIAL_GATE>; 554 clock-names = "ipg", "per"; 555 status = "disabled"; 556 }; 557 558 src: src@53fd0000 { 559 compatible = "fsl,imx53-src", "fsl,imx51-src"; 560 reg = <0x53fd0000 0x4000>; 561 #reset-cells = <1>; 562 }; 563 564 clks: ccm@53fd4000{ 565 compatible = "fsl,imx53-ccm"; 566 reg = <0x53fd4000 0x4000>; 567 interrupts = <0 71 0x04 0 72 0x04>; 568 #clock-cells = <1>; 569 }; 570 571 gpio5: gpio@53fdc000 { 572 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 573 reg = <0x53fdc000 0x4000>; 574 interrupts = <103 104>; 575 gpio-controller; 576 #gpio-cells = <2>; 577 interrupt-controller; 578 #interrupt-cells = <2>; 579 }; 580 581 gpio6: gpio@53fe0000 { 582 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 583 reg = <0x53fe0000 0x4000>; 584 interrupts = <105 106>; 585 gpio-controller; 586 #gpio-cells = <2>; 587 interrupt-controller; 588 #interrupt-cells = <2>; 589 }; 590 591 gpio7: gpio@53fe4000 { 592 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 593 reg = <0x53fe4000 0x4000>; 594 interrupts = <107 108>; 595 gpio-controller; 596 #gpio-cells = <2>; 597 interrupt-controller; 598 #interrupt-cells = <2>; 599 }; 600 601 i2c3: i2c@53fec000 { 602 #address-cells = <1>; 603 #size-cells = <0>; 604 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 605 reg = <0x53fec000 0x4000>; 606 interrupts = <64>; 607 clocks = <&clks IMX5_CLK_I2C3_GATE>; 608 status = "disabled"; 609 }; 610 611 uart4: serial@53ff0000 { 612 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 613 reg = <0x53ff0000 0x4000>; 614 interrupts = <13>; 615 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, 616 <&clks IMX5_CLK_UART4_PER_GATE>; 617 clock-names = "ipg", "per"; 618 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; 619 dma-names = "rx", "tx"; 620 status = "disabled"; 621 }; 622 }; 623 624 aips@60000000 { /* AIPS2 */ 625 compatible = "fsl,aips-bus", "simple-bus"; 626 #address-cells = <1>; 627 #size-cells = <1>; 628 reg = <0x60000000 0x10000000>; 629 ranges; 630 631 aipstz2: bridge@63f00000 { 632 compatible = "fsl,imx53-aipstz"; 633 reg = <0x63f00000 0x60>; 634 }; 635 636 iim: iim@63f98000 { 637 compatible = "fsl,imx53-iim", "fsl,imx27-iim"; 638 reg = <0x63f98000 0x4000>; 639 interrupts = <69>; 640 clocks = <&clks IMX5_CLK_IIM_GATE>; 641 }; 642 643 uart5: serial@63f90000 { 644 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 645 reg = <0x63f90000 0x4000>; 646 interrupts = <86>; 647 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, 648 <&clks IMX5_CLK_UART5_PER_GATE>; 649 clock-names = "ipg", "per"; 650 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; 651 dma-names = "rx", "tx"; 652 status = "disabled"; 653 }; 654 655 owire: owire@63fa4000 { 656 compatible = "fsl,imx53-owire", "fsl,imx21-owire"; 657 reg = <0x63fa4000 0x4000>; 658 clocks = <&clks IMX5_CLK_OWIRE_GATE>; 659 status = "disabled"; 660 }; 661 662 ecspi2: ecspi@63fac000 { 663 #address-cells = <1>; 664 #size-cells = <0>; 665 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 666 reg = <0x63fac000 0x4000>; 667 interrupts = <37>; 668 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, 669 <&clks IMX5_CLK_ECSPI2_PER_GATE>; 670 clock-names = "ipg", "per"; 671 status = "disabled"; 672 }; 673 674 sdma: sdma@63fb0000 { 675 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; 676 reg = <0x63fb0000 0x4000>; 677 interrupts = <6>; 678 clocks = <&clks IMX5_CLK_SDMA_GATE>, 679 <&clks IMX5_CLK_AHB>; 680 clock-names = "ipg", "ahb"; 681 #dma-cells = <3>; 682 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; 683 }; 684 685 cspi: cspi@63fc0000 { 686 #address-cells = <1>; 687 #size-cells = <0>; 688 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; 689 reg = <0x63fc0000 0x4000>; 690 interrupts = <38>; 691 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, 692 <&clks IMX5_CLK_CSPI_IPG_GATE>; 693 clock-names = "ipg", "per"; 694 status = "disabled"; 695 }; 696 697 i2c2: i2c@63fc4000 { 698 #address-cells = <1>; 699 #size-cells = <0>; 700 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 701 reg = <0x63fc4000 0x4000>; 702 interrupts = <63>; 703 clocks = <&clks IMX5_CLK_I2C2_GATE>; 704 status = "disabled"; 705 }; 706 707 i2c1: i2c@63fc8000 { 708 #address-cells = <1>; 709 #size-cells = <0>; 710 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 711 reg = <0x63fc8000 0x4000>; 712 interrupts = <62>; 713 clocks = <&clks IMX5_CLK_I2C1_GATE>; 714 status = "disabled"; 715 }; 716 717 ssi1: ssi@63fcc000 { 718 #sound-dai-cells = <0>; 719 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", 720 "fsl,imx21-ssi"; 721 reg = <0x63fcc000 0x4000>; 722 interrupts = <29>; 723 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, 724 <&clks IMX5_CLK_SSI1_ROOT_GATE>; 725 clock-names = "ipg", "baud"; 726 dmas = <&sdma 28 0 0>, 727 <&sdma 29 0 0>; 728 dma-names = "rx", "tx"; 729 fsl,fifo-depth = <15>; 730 status = "disabled"; 731 }; 732 733 audmux: audmux@63fd0000 { 734 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; 735 reg = <0x63fd0000 0x4000>; 736 status = "disabled"; 737 }; 738 739 nfc: nand@63fdb000 { 740 compatible = "fsl,imx53-nand"; 741 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; 742 interrupts = <8>; 743 clocks = <&clks IMX5_CLK_NFC_GATE>; 744 status = "disabled"; 745 }; 746 747 ssi3: ssi@63fe8000 { 748 #sound-dai-cells = <0>; 749 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", 750 "fsl,imx21-ssi"; 751 reg = <0x63fe8000 0x4000>; 752 interrupts = <96>; 753 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, 754 <&clks IMX5_CLK_SSI3_ROOT_GATE>; 755 clock-names = "ipg", "baud"; 756 dmas = <&sdma 46 0 0>, 757 <&sdma 47 0 0>; 758 dma-names = "rx", "tx"; 759 fsl,fifo-depth = <15>; 760 status = "disabled"; 761 }; 762 763 fec: ethernet@63fec000 { 764 compatible = "fsl,imx53-fec", "fsl,imx25-fec"; 765 reg = <0x63fec000 0x4000>; 766 interrupts = <87>; 767 clocks = <&clks IMX5_CLK_FEC_GATE>, 768 <&clks IMX5_CLK_FEC_GATE>, 769 <&clks IMX5_CLK_FEC_GATE>; 770 clock-names = "ipg", "ahb", "ptp"; 771 status = "disabled"; 772 }; 773 774 tve: tve@63ff0000 { 775 compatible = "fsl,imx53-tve"; 776 reg = <0x63ff0000 0x1000>; 777 interrupts = <92>; 778 clocks = <&clks IMX5_CLK_TVE_GATE>, 779 <&clks IMX5_CLK_IPU_DI1_SEL>; 780 clock-names = "tve", "di_sel"; 781 status = "disabled"; 782 783 port { 784 tve_in: endpoint { 785 remote-endpoint = <&ipu_di1_tve>; 786 }; 787 }; 788 }; 789 790 vpu: vpu@63ff4000 { 791 compatible = "fsl,imx53-vpu", "cnm,coda7541"; 792 reg = <0x63ff4000 0x1000>; 793 interrupts = <9>; 794 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, 795 <&clks IMX5_CLK_VPU_GATE>; 796 clock-names = "per", "ahb"; 797 resets = <&src 1>; 798 iram = <&ocram>; 799 }; 800 801 sahara: crypto@63ff8000 { 802 compatible = "fsl,imx53-sahara"; 803 reg = <0x63ff8000 0x4000>; 804 interrupts = <19 20>; 805 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, 806 <&clks IMX5_CLK_SAHARA_IPG_GATE>; 807 clock-names = "ipg", "ahb"; 808 }; 809 }; 810 811 ocram: sram@f8000000 { 812 compatible = "mmio-sram"; 813 reg = <0xf8000000 0x20000>; 814 clocks = <&clks IMX5_CLK_OCRAM>; 815 }; 816 817 pmu { 818 compatible = "arm,cortex-a8-pmu"; 819 interrupts = <77>; 820 }; 821 }; 822}; 823