1/* 2 * Copyright 2014-2016 Toradex AG 3 * Copyright 2012 Freescale Semiconductor, Inc. 4 * Copyright 2011 Linaro Ltd. 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * version 2 as published by the Free Software Foundation. 14 * 15 * This file is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include <dt-bindings/gpio/gpio.h> 45 46/ { 47 model = "Toradex Colibri iMX6DL/S Module"; 48 compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; 49 50 backlight: backlight { 51 compatible = "pwm-backlight"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pinctrl_gpio_bl_on>; 54 pwms = <&pwm3 0 5000000>; 55 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ 56 status = "disabled"; 57 }; 58 59 reg_1p8v: regulator-1p8v { 60 compatible = "regulator-fixed"; 61 regulator-name = "1P8V"; 62 regulator-min-microvolt = <1800000>; 63 regulator-max-microvolt = <1800000>; 64 regulator-always-on; 65 }; 66 67 reg_2p5v: regulator-2p5v { 68 compatible = "regulator-fixed"; 69 regulator-name = "2P5V"; 70 regulator-min-microvolt = <2500000>; 71 regulator-max-microvolt = <2500000>; 72 regulator-always-on; 73 }; 74 75 reg_3p3v: regulator-3p3v { 76 compatible = "regulator-fixed"; 77 regulator-name = "3P3V"; 78 regulator-min-microvolt = <3300000>; 79 regulator-max-microvolt = <3300000>; 80 regulator-always-on; 81 }; 82 83 reg_usb_host_vbus: regulator-usb-host-vbus { 84 compatible = "regulator-fixed"; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; 87 regulator-name = "usb_host_vbus"; 88 regulator-min-microvolt = <5000000>; 89 regulator-max-microvolt = <5000000>; 90 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ 91 status = "disabled"; 92 }; 93 94 sound { 95 compatible = "fsl,imx-audio-sgtl5000"; 96 model = "imx6dl-colibri-sgtl5000"; 97 ssi-controller = <&ssi1>; 98 audio-codec = <&codec>; 99 audio-routing = 100 "Headphone Jack", "HP_OUT", 101 "LINE_IN", "Line In Jack", 102 "MIC_IN", "Mic Jack", 103 "Mic Jack", "Mic Bias"; 104 mux-int-port = <1>; 105 mux-ext-port = <5>; 106 }; 107 108 /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ 109 sound_spdif: sound-spdif { 110 compatible = "fsl,imx-audio-spdif"; 111 model = "imx-spdif"; 112 spdif-controller = <&spdif>; 113 spdif-in; 114 spdif-out; 115 status = "disabled"; 116 }; 117}; 118 119&audmux { 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>; 122 status = "okay"; 123}; 124 125/* Optional on SODIMM 55/63 */ 126&can1 { 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_flexcan1>; 129 status = "disabled"; 130}; 131 132/* Optional on SODIMM 178/188 */ 133&can2 { 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_flexcan2>; 136 status = "disabled"; 137}; 138 139/* Colibri SSP */ 140&ecspi4 { 141 cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_ecspi4>; 144 status = "disabled"; 145}; 146 147&fec { 148 pinctrl-names = "default"; 149 pinctrl-0 = <&pinctrl_enet>; 150 phy-mode = "rmii"; 151 status = "okay"; 152}; 153 154&hdmi { 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_hdmi_ddc>; 157 status = "disabled"; 158}; 159 160/* 161 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 162 * touch screen controller 163 */ 164&i2c2 { 165 clock-frequency = <100000>; 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_i2c2>; 168 status = "okay"; 169 170 pmic: pfuze100@08 { 171 compatible = "fsl,pfuze100"; 172 reg = <0x08>; 173 174 regulators { 175 sw1a_reg: sw1ab { 176 regulator-min-microvolt = <300000>; 177 regulator-max-microvolt = <1875000>; 178 regulator-boot-on; 179 regulator-always-on; 180 regulator-ramp-delay = <6250>; 181 }; 182 183 sw1c_reg: sw1c { 184 regulator-min-microvolt = <300000>; 185 regulator-max-microvolt = <1875000>; 186 regulator-boot-on; 187 regulator-always-on; 188 regulator-ramp-delay = <6250>; 189 }; 190 191 sw3a_reg: sw3a { 192 regulator-min-microvolt = <400000>; 193 regulator-max-microvolt = <1975000>; 194 regulator-boot-on; 195 regulator-always-on; 196 }; 197 198 swbst_reg: swbst { 199 regulator-min-microvolt = <5000000>; 200 regulator-max-microvolt = <5150000>; 201 regulator-boot-on; 202 regulator-always-on; 203 }; 204 205 snvs_reg: vsnvs { 206 regulator-min-microvolt = <1000000>; 207 regulator-max-microvolt = <3000000>; 208 regulator-boot-on; 209 regulator-always-on; 210 }; 211 212 vref_reg: vrefddr { 213 regulator-boot-on; 214 regulator-always-on; 215 }; 216 217 /* vgen1: unused */ 218 219 vgen2_reg: vgen2 { 220 regulator-min-microvolt = <800000>; 221 regulator-max-microvolt = <1550000>; 222 regulator-boot-on; 223 regulator-always-on; 224 }; 225 226 /* vgen3: unused */ 227 228 vgen4_reg: vgen4 { 229 regulator-min-microvolt = <1800000>; 230 regulator-max-microvolt = <3300000>; 231 regulator-boot-on; 232 regulator-always-on; 233 }; 234 235 vgen5_reg: vgen5 { 236 regulator-min-microvolt = <1800000>; 237 regulator-max-microvolt = <3300000>; 238 regulator-boot-on; 239 regulator-always-on; 240 }; 241 242 vgen6_reg: vgen6 { 243 regulator-min-microvolt = <1800000>; 244 regulator-max-microvolt = <3300000>; 245 regulator-boot-on; 246 regulator-always-on; 247 }; 248 }; 249 }; 250 251 codec: sgtl5000@0a { 252 compatible = "fsl,sgtl5000"; 253 reg = <0x0a>; 254 clocks = <&clks IMX6QDL_CLK_CKO>; 255 VDDA-supply = <®_2p5v>; 256 VDDIO-supply = <®_3p3v>; 257 lrclk-strength = <3>; 258 }; 259 260 /* STMPE811 touch screen controller */ 261 stmpe811@41 { 262 compatible = "st,stmpe811"; 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_touch_int>; 265 #address-cells = <1>; 266 #size-cells = <0>; 267 reg = <0x41>; 268 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 269 interrupt-parent = <&gpio6>; 270 interrupt-controller; 271 id = <0>; 272 blocks = <0x5>; 273 irq-trigger = <0x1>; 274 275 stmpe_touchscreen { 276 compatible = "st,stmpe-ts"; 277 reg = <0>; 278 /* 3.25 MHz ADC clock speed */ 279 st,adc-freq = <1>; 280 /* 8 sample average control */ 281 st,ave-ctrl = <3>; 282 /* 7 length fractional part in z */ 283 st,fraction-z = <7>; 284 /* 285 * 50 mA typical 80 mA max touchscreen drivers 286 * current limit value 287 */ 288 st,i-drive = <1>; 289 /* 12-bit ADC */ 290 st,mod-12b = <1>; 291 /* internal ADC reference */ 292 st,ref-sel = <0>; 293 /* ADC converstion time: 80 clocks */ 294 st,sample-time = <4>; 295 /* 1 ms panel driver settling time */ 296 st,settling = <3>; 297 /* 5 ms touch detect interrupt delay */ 298 st,touch-det-delay = <5>; 299 }; 300 }; 301}; 302 303/* 304 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) 305 */ 306&i2c3 { 307 clock-frequency = <100000>; 308 pinctrl-names = "default", "recovery"; 309 pinctrl-0 = <&pinctrl_i2c3>; 310 pinctrl-1 = <&pinctrl_i2c3_recovery>; 311 scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 312 sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 313 status = "disabled"; 314}; 315 316/* Colibri PWM<B> */ 317&pwm1 { 318 pinctrl-names = "default"; 319 pinctrl-0 = <&pinctrl_pwm1>; 320 status = "disabled"; 321}; 322 323/* Colibri PWM<D> */ 324&pwm2 { 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pinctrl_pwm2>; 327 status = "disabled"; 328}; 329 330/* Colibri PWM<A> */ 331&pwm3 { 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pinctrl_pwm3>; 334 status = "disabled"; 335}; 336 337/* Colibri PWM<C> */ 338&pwm4 { 339 pinctrl-names = "default"; 340 pinctrl-0 = <&pinctrl_pwm4>; 341 status = "disabled"; 342}; 343 344/* Optional S/PDIF out on SODIMM 137 */ 345&spdif { 346 pinctrl-names = "default"; 347 pinctrl-0 = <&pinctrl_spdif>; 348 status = "disabled"; 349}; 350 351&ssi1 { 352 status = "okay"; 353}; 354 355/* Colibri UART_A */ 356&uart1 { 357 pinctrl-names = "default"; 358 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; 359 fsl,dte-mode; 360 uart-has-rtscts; 361 status = "disabled"; 362}; 363 364/* Colibri UART_B */ 365&uart2 { 366 pinctrl-names = "default"; 367 pinctrl-0 = <&pinctrl_uart2_dte>; 368 fsl,dte-mode; 369 uart-has-rtscts; 370 status = "disabled"; 371}; 372 373/* Colibri UART_C */ 374&uart3 { 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pinctrl_uart3_dte>; 377 fsl,dte-mode; 378 status = "disabled"; 379}; 380 381&usbotg { 382 pinctrl-names = "default"; 383 disable-over-current; 384 dr_mode = "peripheral"; 385 status = "disabled"; 386}; 387 388/* Colibri MMC */ 389&usdhc1 { 390 pinctrl-names = "default"; 391 pinctrl-0 = <&pinctrl_usdhc1>; 392 vqmmc-supply = <®_3p3v>; 393 bus-width = <4>; 394 voltage-ranges = <3300 3300>; 395 status = "disabled"; 396}; 397 398/* eMMC */ 399&usdhc3 { 400 pinctrl-names = "default"; 401 pinctrl-0 = <&pinctrl_usdhc3>; 402 vqmmc-supply = <®_3p3v>; 403 bus-width = <8>; 404 voltage-ranges = <3300 3300>; 405 non-removable; 406 status = "okay"; 407}; 408 409&weim { 410 pinctrl-names = "default"; 411 pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0 412 &pinctrl_weim_cs1 &pinctrl_weim_cs2 413 &pinctrl_weim_rdnwr &pinctrl_weim_npwe>; 414 #address-cells = <2>; 415 #size-cells = <1>; 416 status = "disabled"; 417}; 418 419&iomuxc { 420 pinctrl_audmux: audmuxgrp { 421 fsl,pins = < 422 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 423 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 424 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 425 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 426 /* SGTL5000 sys_mclk */ 427 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 428 >; 429 }; 430 431 pinctrl_cam_mclk: cammclkgrp { 432 fsl,pins = < 433 /* Parallel Camera CAM sys_mclk */ 434 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 435 >; 436 }; 437 438 pinctrl_ecspi4: ecspi4grp { 439 fsl,pins = < 440 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 441 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 442 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 443 /* SPI CS */ 444 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 445 >; 446 }; 447 448 pinctrl_enet: enetgrp { 449 fsl,pins = < 450 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 451 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 452 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 453 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 454 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 455 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 456 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 457 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 458 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 459 MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) 460 >; 461 }; 462 463 pinctrl_flexcan1: flexcan1grp { 464 fsl,pins = < 465 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 466 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 467 >; 468 }; 469 470 pinctrl_flexcan2: flexcan2grp { 471 fsl,pins = < 472 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 473 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 474 >; 475 }; 476 477 pinctrl_gpio_bl_on: gpioblon { 478 fsl,pins = < 479 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 480 >; 481 }; 482 483 pinctrl_gpio_keys: gpiokeys { 484 fsl,pins = < 485 /* Power button */ 486 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 487 >; 488 }; 489 490 pinctrl_hdmi_ddc: hdmiddcgrp { 491 fsl,pins = < 492 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 493 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 494 >; 495 }; 496 497 pinctrl_i2c2: i2c2grp { 498 fsl,pins = < 499 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 500 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 501 >; 502 }; 503 504 pinctrl_i2c3: i2c3grp { 505 fsl,pins = < 506 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 507 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 508 >; 509 }; 510 511 pinctrl_i2c3_recovery: i2c3recoverygrp { 512 fsl,pins = < 513 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 514 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 515 >; 516 }; 517 518 pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */ 519 fsl,pins = < 520 MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 521 MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 522 MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 523 MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 524 MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 525 MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 526 MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 527 MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1 528 MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1 529 MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 530 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 531 /* Disable PWM pins on camera interface */ 532 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 533 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 534 >; 535 }; 536 537 pinctrl_ipu1_lcdif: ipu1lcdifgrp { 538 fsl,pins = < 539 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1 540 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1 541 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1 542 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1 543 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1 544 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1 545 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1 546 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1 547 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1 548 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1 549 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1 550 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1 551 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1 552 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1 553 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1 554 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1 555 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1 556 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1 557 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1 558 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1 559 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1 560 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 561 >; 562 }; 563 564 pinctrl_mic_gnd: gpiomicgnd { 565 fsl,pins = < 566 /* Controls Mic GND, PU or '1' pull Mic GND to GND */ 567 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 568 >; 569 }; 570 571 pinctrl_mmc_cd: gpiommccd { 572 fsl,pins = < 573 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 574 >; 575 }; 576 577 pinctrl_pwm1: pwm1grp { 578 fsl,pins = < 579 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 580 >; 581 }; 582 583 pinctrl_pwm2: pwm2grp { 584 fsl,pins = < 585 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 586 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 587 >; 588 }; 589 590 pinctrl_pwm3: pwm3grp { 591 fsl,pins = < 592 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 593 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 594 >; 595 }; 596 597 pinctrl_pwm4: pwm4grp { 598 fsl,pins = < 599 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 600 >; 601 }; 602 603 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { 604 fsl,pins = < 605 /* USBH_EN */ 606 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 607 >; 608 }; 609 610 pinctrl_spdif: spdifgrp { 611 fsl,pins = < 612 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 613 >; 614 }; 615 616 pinctrl_touch_int: gpiotouchintgrp { 617 fsl,pins = < 618 /* STMPE811 interrupt */ 619 MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0 620 >; 621 }; 622 623 pinctrl_uart1_dce: uart1dcegrp { 624 fsl,pins = < 625 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 626 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 627 >; 628 }; 629 630 /* DTE mode */ 631 pinctrl_uart1_dte: uart1dtegrp { 632 fsl,pins = < 633 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 634 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 635 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 636 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 637 >; 638 }; 639 640 /* Additional DTR, DSR, DCD */ 641 pinctrl_uart1_ctrl: uart1ctrlgrp { 642 fsl,pins = < 643 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 644 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 645 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 646 >; 647 }; 648 649 pinctrl_uart2_dte: uart2dtegrp { 650 fsl,pins = < 651 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 652 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 653 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 654 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 655 >; 656 }; 657 658 pinctrl_uart3_dte: uart3dtegrp { 659 fsl,pins = < 660 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 661 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 662 >; 663 }; 664 665 pinctrl_usbc_det: usbcdetgrp { 666 fsl,pins = < 667 /* USBC_DET */ 668 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 669 /* USBC_DET_EN */ 670 MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 671 /* USBC_DET_OVERWRITE */ 672 MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 673 >; 674 }; 675 676 pinctrl_usdhc1: usdhc1grp { 677 fsl,pins = < 678 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 679 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 680 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 681 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 682 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 683 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 684 >; 685 }; 686 687 pinctrl_usdhc3: usdhc3grp { 688 fsl,pins = < 689 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 690 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 691 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 692 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 693 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 694 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 695 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 696 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 697 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 698 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 699 /* eMMC reset */ 700 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 701 >; 702 }; 703 704 pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { 705 fsl,pins = < 706 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 707 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 708 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 709 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 710 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 711 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 712 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 713 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 714 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 715 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 716 /* eMMC reset */ 717 MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9 718 >; 719 }; 720 721 pinctrl_usdhc3_200mhz: usdhc3200mhzgrp { 722 fsl,pins = < 723 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 724 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 725 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 726 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 727 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 728 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 729 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 730 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 731 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 732 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 733 /* eMMC reset */ 734 MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9 735 >; 736 }; 737 738 pinctrl_weim_cs0: weimcs0grp { 739 fsl,pins = < 740 /* nEXT_CS0 */ 741 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 742 >; 743 }; 744 745 pinctrl_weim_cs1: weimcs1grp { 746 fsl,pins = < 747 /* nEXT_CS1 */ 748 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 749 >; 750 }; 751 752 pinctrl_weim_cs2: weimcs2grp { 753 fsl,pins = < 754 /* nEXT_CS2 */ 755 MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 756 >; 757 }; 758 759 pinctrl_weim_sram: weimsramgrp { 760 fsl,pins = < 761 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 762 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 763 /* Data */ 764 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 765 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 766 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 767 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 768 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 769 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 770 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 771 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 772 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 773 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 774 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 775 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 776 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 777 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 778 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 779 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 780 /* Address */ 781 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 782 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 783 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 784 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 785 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 786 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 787 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 788 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 789 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 790 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 791 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 792 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 793 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 794 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 795 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 796 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 797 >; 798 }; 799 800 pinctrl_weim_rdnwr: weimrdnwr { 801 fsl,pins = < 802 MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 803 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 804 >; 805 }; 806 807 pinctrl_weim_npwe: weimnpwe { 808 fsl,pins = < 809 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 810 MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 811 >; 812 }; 813 814 /* ADDRESS[16:18] [25] used as GPIO */ 815 pinctrl_weim_gpio_1: weimgpio-1 { 816 fsl,pins = < 817 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 818 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 819 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 820 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 821 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 822 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 823 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 824 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 825 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 826 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 827 >; 828 }; 829 830 /* ADDRESS[19:24] used as GPIO */ 831 pinctrl_weim_gpio_2: weimgpio-2 { 832 fsl,pins = < 833 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 834 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 835 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 836 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 837 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 838 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 839 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 840 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 841 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 842 >; 843 }; 844 845 /* DATA[16:31] used as GPIO */ 846 pinctrl_weim_gpio_3: weimgpio-3 { 847 fsl,pins = < 848 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 849 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 850 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 851 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 852 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 853 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 854 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 855 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 856 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 857 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 858 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 859 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 860 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 861 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 862 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 863 >; 864 }; 865 866 /* DQM[0:3] used as GPIO */ 867 pinctrl_weim_gpio_4: weimgpio-4 { 868 fsl,pins = < 869 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 870 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 871 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 872 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 873 >; 874 }; 875 876 /* RDY used as GPIO */ 877 pinctrl_weim_gpio_5: weimgpio-5 { 878 fsl,pins = < 879 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 880 >; 881 }; 882 883 /* ADDRESS[16] DATA[30] used as GPIO */ 884 pinctrl_weim_gpio_6: weimgpio-6 { 885 fsl,pins = < 886 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 887 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 888 >; 889 }; 890}; 891