1/* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9#include <dt-bindings/clock/imx6sx-clock.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include "imx6sx-pinfunc.h" 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 /* 19 * The decompressor and also some bootloaders rely on a 20 * pre-existing /chosen node to be available to insert the 21 * command line and merge other ATAGS info. 22 * Also for U-Boot there must be a pre-existing /memory node. 23 */ 24 chosen {}; 25 memory { device_type = "memory"; reg = <0 0>; }; 26 27 aliases { 28 can0 = &flexcan1; 29 can1 = &flexcan2; 30 ethernet0 = &fec1; 31 ethernet1 = &fec2; 32 gpio0 = &gpio1; 33 gpio1 = &gpio2; 34 gpio2 = &gpio3; 35 gpio3 = &gpio4; 36 gpio4 = &gpio5; 37 gpio5 = &gpio6; 38 gpio6 = &gpio7; 39 i2c0 = &i2c1; 40 i2c1 = &i2c2; 41 i2c2 = &i2c3; 42 i2c3 = &i2c4; 43 mmc0 = &usdhc1; 44 mmc1 = &usdhc2; 45 mmc2 = &usdhc3; 46 mmc3 = &usdhc4; 47 serial0 = &uart1; 48 serial1 = &uart2; 49 serial2 = &uart3; 50 serial3 = &uart4; 51 serial4 = &uart5; 52 serial5 = &uart6; 53 spi0 = &ecspi1; 54 spi1 = &ecspi2; 55 spi2 = &ecspi3; 56 spi3 = &ecspi4; 57 spi4 = &ecspi5; 58 usbphy0 = &usbphy1; 59 usbphy1 = &usbphy2; 60 }; 61 62 cpus { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 66 cpu0: cpu@0 { 67 compatible = "arm,cortex-a9"; 68 device_type = "cpu"; 69 reg = <0>; 70 next-level-cache = <&L2>; 71 operating-points = < 72 /* kHz uV */ 73 996000 1250000 74 792000 1175000 75 396000 1075000 76 198000 975000 77 >; 78 fsl,soc-operating-points = < 79 /* ARM kHz SOC uV */ 80 996000 1175000 81 792000 1175000 82 396000 1175000 83 198000 1175000 84 >; 85 clock-latency = <61036>; /* two CLK32 periods */ 86 clocks = <&clks IMX6SX_CLK_ARM>, 87 <&clks IMX6SX_CLK_PLL2_PFD2>, 88 <&clks IMX6SX_CLK_STEP>, 89 <&clks IMX6SX_CLK_PLL1_SW>, 90 <&clks IMX6SX_CLK_PLL1_SYS>; 91 clock-names = "arm", "pll2_pfd2_396m", "step", 92 "pll1_sw", "pll1_sys"; 93 arm-supply = <®_arm>; 94 soc-supply = <®_soc>; 95 }; 96 }; 97 98 intc: interrupt-controller@00a01000 { 99 compatible = "arm,cortex-a9-gic"; 100 #interrupt-cells = <3>; 101 interrupt-controller; 102 reg = <0x00a01000 0x1000>, 103 <0x00a00100 0x100>; 104 interrupt-parent = <&intc>; 105 }; 106 107 clocks { 108 #address-cells = <1>; 109 #size-cells = <0>; 110 111 ckil: clock@0 { 112 compatible = "fixed-clock"; 113 reg = <0>; 114 #clock-cells = <0>; 115 clock-frequency = <32768>; 116 clock-output-names = "ckil"; 117 }; 118 119 osc: clock@1 { 120 compatible = "fixed-clock"; 121 reg = <1>; 122 #clock-cells = <0>; 123 clock-frequency = <24000000>; 124 clock-output-names = "osc"; 125 }; 126 127 ipp_di0: clock@2 { 128 compatible = "fixed-clock"; 129 reg = <2>; 130 #clock-cells = <0>; 131 clock-frequency = <0>; 132 clock-output-names = "ipp_di0"; 133 }; 134 135 ipp_di1: clock@3 { 136 compatible = "fixed-clock"; 137 reg = <3>; 138 #clock-cells = <0>; 139 clock-frequency = <0>; 140 clock-output-names = "ipp_di1"; 141 }; 142 }; 143 144 soc { 145 #address-cells = <1>; 146 #size-cells = <1>; 147 compatible = "simple-bus"; 148 interrupt-parent = <&gpc>; 149 ranges; 150 151 pmu { 152 compatible = "arm,cortex-a9-pmu"; 153 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 154 }; 155 156 ocram: sram@00900000 { 157 compatible = "mmio-sram"; 158 reg = <0x00900000 0x20000>; 159 clocks = <&clks IMX6SX_CLK_OCRAM>; 160 }; 161 162 L2: l2-cache@00a02000 { 163 compatible = "arm,pl310-cache"; 164 reg = <0x00a02000 0x1000>; 165 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 166 cache-unified; 167 cache-level = <2>; 168 arm,tag-latency = <4 2 3>; 169 arm,data-latency = <4 2 3>; 170 }; 171 172 gpu: gpu@01800000 { 173 compatible = "vivante,gc"; 174 reg = <0x01800000 0x4000>; 175 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&clks IMX6SX_CLK_GPU>, 177 <&clks IMX6SX_CLK_GPU>, 178 <&clks IMX6SX_CLK_GPU>; 179 clock-names = "bus", "core", "shader"; 180 }; 181 182 dma_apbh: dma-apbh@01804000 { 183 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; 184 reg = <0x01804000 0x2000>; 185 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 189 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 190 #dma-cells = <1>; 191 dma-channels = <4>; 192 clocks = <&clks IMX6SX_CLK_APBH_DMA>; 193 }; 194 195 gpmi: gpmi-nand@01806000{ 196 compatible = "fsl,imx6sx-gpmi-nand"; 197 #address-cells = <1>; 198 #size-cells = <1>; 199 reg = <0x01806000 0x2000>, <0x01808000 0x4000>; 200 reg-names = "gpmi-nand", "bch"; 201 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 202 interrupt-names = "bch"; 203 clocks = <&clks IMX6SX_CLK_GPMI_IO>, 204 <&clks IMX6SX_CLK_GPMI_APB>, 205 <&clks IMX6SX_CLK_GPMI_BCH>, 206 <&clks IMX6SX_CLK_GPMI_BCH_APB>, 207 <&clks IMX6SX_CLK_PER1_BCH>; 208 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 209 "gpmi_bch_apb", "per1_bch"; 210 dmas = <&dma_apbh 0>; 211 dma-names = "rx-tx"; 212 status = "disabled"; 213 }; 214 215 aips1: aips-bus@02000000 { 216 compatible = "fsl,aips-bus", "simple-bus"; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 reg = <0x02000000 0x100000>; 220 ranges; 221 222 spba-bus@02000000 { 223 compatible = "fsl,spba-bus", "simple-bus"; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 reg = <0x02000000 0x40000>; 227 ranges; 228 229 spdif: spdif@02004000 { 230 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; 231 reg = <0x02004000 0x4000>; 232 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 233 dmas = <&sdma 14 18 0>, 234 <&sdma 15 18 0>; 235 dma-names = "rx", "tx"; 236 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>, 237 <&clks IMX6SX_CLK_OSC>, 238 <&clks IMX6SX_CLK_SPDIF>, 239 <&clks 0>, <&clks 0>, <&clks 0>, 240 <&clks IMX6SX_CLK_IPG>, 241 <&clks 0>, <&clks 0>, 242 <&clks IMX6SX_CLK_SPBA>; 243 clock-names = "core", "rxtx0", 244 "rxtx1", "rxtx2", 245 "rxtx3", "rxtx4", 246 "rxtx5", "rxtx6", 247 "rxtx7", "spba"; 248 status = "disabled"; 249 }; 250 251 ecspi1: ecspi@02008000 { 252 #address-cells = <1>; 253 #size-cells = <0>; 254 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 255 reg = <0x02008000 0x4000>; 256 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&clks IMX6SX_CLK_ECSPI1>, 258 <&clks IMX6SX_CLK_ECSPI1>; 259 clock-names = "ipg", "per"; 260 status = "disabled"; 261 }; 262 263 ecspi2: ecspi@0200c000 { 264 #address-cells = <1>; 265 #size-cells = <0>; 266 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 267 reg = <0x0200c000 0x4000>; 268 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&clks IMX6SX_CLK_ECSPI2>, 270 <&clks IMX6SX_CLK_ECSPI2>; 271 clock-names = "ipg", "per"; 272 status = "disabled"; 273 }; 274 275 ecspi3: ecspi@02010000 { 276 #address-cells = <1>; 277 #size-cells = <0>; 278 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 279 reg = <0x02010000 0x4000>; 280 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&clks IMX6SX_CLK_ECSPI3>, 282 <&clks IMX6SX_CLK_ECSPI3>; 283 clock-names = "ipg", "per"; 284 status = "disabled"; 285 }; 286 287 ecspi4: ecspi@02014000 { 288 #address-cells = <1>; 289 #size-cells = <0>; 290 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 291 reg = <0x02014000 0x4000>; 292 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&clks IMX6SX_CLK_ECSPI4>, 294 <&clks IMX6SX_CLK_ECSPI4>; 295 clock-names = "ipg", "per"; 296 status = "disabled"; 297 }; 298 299 uart1: serial@02020000 { 300 compatible = "fsl,imx6sx-uart", 301 "fsl,imx6q-uart", "fsl,imx21-uart"; 302 reg = <0x02020000 0x4000>; 303 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&clks IMX6SX_CLK_UART_IPG>, 305 <&clks IMX6SX_CLK_UART_SERIAL>; 306 clock-names = "ipg", "per"; 307 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 308 dma-names = "rx", "tx"; 309 status = "disabled"; 310 }; 311 312 esai: esai@02024000 { 313 reg = <0x02024000 0x4000>; 314 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&clks IMX6SX_CLK_ESAI_IPG>, 316 <&clks IMX6SX_CLK_ESAI_MEM>, 317 <&clks IMX6SX_CLK_ESAI_EXTAL>, 318 <&clks IMX6SX_CLK_ESAI_IPG>, 319 <&clks IMX6SX_CLK_SPBA>; 320 clock-names = "core", "mem", "extal", 321 "fsys", "spba"; 322 status = "disabled"; 323 }; 324 325 ssi1: ssi@02028000 { 326 #sound-dai-cells = <0>; 327 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 328 reg = <0x02028000 0x4000>; 329 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&clks IMX6SX_CLK_SSI1_IPG>, 331 <&clks IMX6SX_CLK_SSI1>; 332 clock-names = "ipg", "baud"; 333 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; 334 dma-names = "rx", "tx"; 335 fsl,fifo-depth = <15>; 336 status = "disabled"; 337 }; 338 339 ssi2: ssi@0202c000 { 340 #sound-dai-cells = <0>; 341 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 342 reg = <0x0202c000 0x4000>; 343 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&clks IMX6SX_CLK_SSI2_IPG>, 345 <&clks IMX6SX_CLK_SSI2>; 346 clock-names = "ipg", "baud"; 347 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; 348 dma-names = "rx", "tx"; 349 fsl,fifo-depth = <15>; 350 status = "disabled"; 351 }; 352 353 ssi3: ssi@02030000 { 354 #sound-dai-cells = <0>; 355 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 356 reg = <0x02030000 0x4000>; 357 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&clks IMX6SX_CLK_SSI3_IPG>, 359 <&clks IMX6SX_CLK_SSI3>; 360 clock-names = "ipg", "baud"; 361 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; 362 dma-names = "rx", "tx"; 363 fsl,fifo-depth = <15>; 364 status = "disabled"; 365 }; 366 367 asrc: asrc@02034000 { 368 reg = <0x02034000 0x4000>; 369 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&clks IMX6SX_CLK_ASRC_MEM>, 371 <&clks IMX6SX_CLK_ASRC_IPG>, 372 <&clks IMX6SX_CLK_SPDIF>, 373 <&clks IMX6SX_CLK_SPBA>; 374 clock-names = "mem", "ipg", "asrck", "spba"; 375 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, 376 <&sdma 19 20 1>, <&sdma 20 20 1>, 377 <&sdma 21 20 1>, <&sdma 22 20 1>; 378 dma-names = "rxa", "rxb", "rxc", 379 "txa", "txb", "txc"; 380 status = "okay"; 381 }; 382 }; 383 384 pwm1: pwm@02080000 { 385 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 386 reg = <0x02080000 0x4000>; 387 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&clks IMX6SX_CLK_PWM1>, 389 <&clks IMX6SX_CLK_PWM1>; 390 clock-names = "ipg", "per"; 391 #pwm-cells = <2>; 392 }; 393 394 pwm2: pwm@02084000 { 395 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 396 reg = <0x02084000 0x4000>; 397 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&clks IMX6SX_CLK_PWM2>, 399 <&clks IMX6SX_CLK_PWM2>; 400 clock-names = "ipg", "per"; 401 #pwm-cells = <2>; 402 }; 403 404 pwm3: pwm@02088000 { 405 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 406 reg = <0x02088000 0x4000>; 407 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&clks IMX6SX_CLK_PWM3>, 409 <&clks IMX6SX_CLK_PWM3>; 410 clock-names = "ipg", "per"; 411 #pwm-cells = <2>; 412 }; 413 414 pwm4: pwm@0208c000 { 415 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 416 reg = <0x0208c000 0x4000>; 417 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&clks IMX6SX_CLK_PWM4>, 419 <&clks IMX6SX_CLK_PWM4>; 420 clock-names = "ipg", "per"; 421 #pwm-cells = <2>; 422 }; 423 424 flexcan1: can@02090000 { 425 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; 426 reg = <0x02090000 0x4000>; 427 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&clks IMX6SX_CLK_CAN1_IPG>, 429 <&clks IMX6SX_CLK_CAN1_SERIAL>; 430 clock-names = "ipg", "per"; 431 status = "disabled"; 432 }; 433 434 flexcan2: can@02094000 { 435 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; 436 reg = <0x02094000 0x4000>; 437 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&clks IMX6SX_CLK_CAN2_IPG>, 439 <&clks IMX6SX_CLK_CAN2_SERIAL>; 440 clock-names = "ipg", "per"; 441 status = "disabled"; 442 }; 443 444 gpt: gpt@02098000 { 445 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt"; 446 reg = <0x02098000 0x4000>; 447 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&clks IMX6SX_CLK_GPT_BUS>, 449 <&clks IMX6SX_CLK_GPT_3M>; 450 clock-names = "ipg", "per"; 451 }; 452 453 gpio1: gpio@0209c000 { 454 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 455 reg = <0x0209c000 0x4000>; 456 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 458 gpio-controller; 459 #gpio-cells = <2>; 460 interrupt-controller; 461 #interrupt-cells = <2>; 462 gpio-ranges = <&iomuxc 0 5 26>; 463 }; 464 465 gpio2: gpio@020a0000 { 466 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 467 reg = <0x020a0000 0x4000>; 468 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 470 gpio-controller; 471 #gpio-cells = <2>; 472 interrupt-controller; 473 #interrupt-cells = <2>; 474 gpio-ranges = <&iomuxc 0 31 20>; 475 }; 476 477 gpio3: gpio@020a4000 { 478 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 479 reg = <0x020a4000 0x4000>; 480 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 482 gpio-controller; 483 #gpio-cells = <2>; 484 interrupt-controller; 485 #interrupt-cells = <2>; 486 gpio-ranges = <&iomuxc 0 51 29>; 487 }; 488 489 gpio4: gpio@020a8000 { 490 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 491 reg = <0x020a8000 0x4000>; 492 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 494 gpio-controller; 495 #gpio-cells = <2>; 496 interrupt-controller; 497 #interrupt-cells = <2>; 498 gpio-ranges = <&iomuxc 0 80 32>; 499 }; 500 501 gpio5: gpio@020ac000 { 502 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 503 reg = <0x020ac000 0x4000>; 504 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 506 gpio-controller; 507 #gpio-cells = <2>; 508 interrupt-controller; 509 #interrupt-cells = <2>; 510 gpio-ranges = <&iomuxc 0 112 24>; 511 }; 512 513 gpio6: gpio@020b0000 { 514 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 515 reg = <0x020b0000 0x4000>; 516 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 518 gpio-controller; 519 #gpio-cells = <2>; 520 interrupt-controller; 521 #interrupt-cells = <2>; 522 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; 523 }; 524 525 gpio7: gpio@020b4000 { 526 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 527 reg = <0x020b4000 0x4000>; 528 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 530 gpio-controller; 531 #gpio-cells = <2>; 532 interrupt-controller; 533 #interrupt-cells = <2>; 534 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; 535 }; 536 537 kpp: kpp@020b8000 { 538 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; 539 reg = <0x020b8000 0x4000>; 540 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&clks IMX6SX_CLK_DUMMY>; 542 status = "disabled"; 543 }; 544 545 wdog1: wdog@020bc000 { 546 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 547 reg = <0x020bc000 0x4000>; 548 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&clks IMX6SX_CLK_DUMMY>; 550 }; 551 552 wdog2: wdog@020c0000 { 553 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 554 reg = <0x020c0000 0x4000>; 555 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&clks IMX6SX_CLK_DUMMY>; 557 status = "disabled"; 558 }; 559 560 clks: ccm@020c4000 { 561 compatible = "fsl,imx6sx-ccm"; 562 reg = <0x020c4000 0x4000>; 563 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 565 #clock-cells = <1>; 566 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; 567 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; 568 }; 569 570 anatop: anatop@020c8000 { 571 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", 572 "syscon", "simple-bus"; 573 reg = <0x020c8000 0x1000>; 574 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 577 578 regulator-1p1 { 579 compatible = "fsl,anatop-regulator"; 580 regulator-name = "vdd1p1"; 581 regulator-min-microvolt = <800000>; 582 regulator-max-microvolt = <1375000>; 583 regulator-always-on; 584 anatop-reg-offset = <0x110>; 585 anatop-vol-bit-shift = <8>; 586 anatop-vol-bit-width = <5>; 587 anatop-min-bit-val = <4>; 588 anatop-min-voltage = <800000>; 589 anatop-max-voltage = <1375000>; 590 anatop-enable-bit = <0>; 591 }; 592 593 regulator-3p0 { 594 compatible = "fsl,anatop-regulator"; 595 regulator-name = "vdd3p0"; 596 regulator-min-microvolt = <2800000>; 597 regulator-max-microvolt = <3150000>; 598 regulator-always-on; 599 anatop-reg-offset = <0x120>; 600 anatop-vol-bit-shift = <8>; 601 anatop-vol-bit-width = <5>; 602 anatop-min-bit-val = <0>; 603 anatop-min-voltage = <2625000>; 604 anatop-max-voltage = <3400000>; 605 anatop-enable-bit = <0>; 606 }; 607 608 regulator-2p5 { 609 compatible = "fsl,anatop-regulator"; 610 regulator-name = "vdd2p5"; 611 regulator-min-microvolt = <2100000>; 612 regulator-max-microvolt = <2875000>; 613 regulator-always-on; 614 anatop-reg-offset = <0x130>; 615 anatop-vol-bit-shift = <8>; 616 anatop-vol-bit-width = <5>; 617 anatop-min-bit-val = <0>; 618 anatop-min-voltage = <2100000>; 619 anatop-max-voltage = <2875000>; 620 anatop-enable-bit = <0>; 621 }; 622 623 reg_arm: regulator-vddcore { 624 compatible = "fsl,anatop-regulator"; 625 regulator-name = "vddarm"; 626 regulator-min-microvolt = <725000>; 627 regulator-max-microvolt = <1450000>; 628 regulator-always-on; 629 anatop-reg-offset = <0x140>; 630 anatop-vol-bit-shift = <0>; 631 anatop-vol-bit-width = <5>; 632 anatop-delay-reg-offset = <0x170>; 633 anatop-delay-bit-shift = <24>; 634 anatop-delay-bit-width = <2>; 635 anatop-min-bit-val = <1>; 636 anatop-min-voltage = <725000>; 637 anatop-max-voltage = <1450000>; 638 }; 639 640 reg_pcie: regulator-vddpcie { 641 compatible = "fsl,anatop-regulator"; 642 regulator-name = "vddpcie"; 643 regulator-min-microvolt = <725000>; 644 regulator-max-microvolt = <1450000>; 645 anatop-reg-offset = <0x140>; 646 anatop-vol-bit-shift = <9>; 647 anatop-vol-bit-width = <5>; 648 anatop-delay-reg-offset = <0x170>; 649 anatop-delay-bit-shift = <26>; 650 anatop-delay-bit-width = <2>; 651 anatop-min-bit-val = <1>; 652 anatop-min-voltage = <725000>; 653 anatop-max-voltage = <1450000>; 654 }; 655 656 reg_soc: regulator-vddsoc { 657 compatible = "fsl,anatop-regulator"; 658 regulator-name = "vddsoc"; 659 regulator-min-microvolt = <725000>; 660 regulator-max-microvolt = <1450000>; 661 regulator-always-on; 662 anatop-reg-offset = <0x140>; 663 anatop-vol-bit-shift = <18>; 664 anatop-vol-bit-width = <5>; 665 anatop-delay-reg-offset = <0x170>; 666 anatop-delay-bit-shift = <28>; 667 anatop-delay-bit-width = <2>; 668 anatop-min-bit-val = <1>; 669 anatop-min-voltage = <725000>; 670 anatop-max-voltage = <1450000>; 671 }; 672 }; 673 674 tempmon: tempmon { 675 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; 676 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 677 fsl,tempmon = <&anatop>; 678 fsl,tempmon-data = <&ocotp>; 679 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; 680 }; 681 682 usbphy1: usbphy@020c9000 { 683 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; 684 reg = <0x020c9000 0x1000>; 685 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&clks IMX6SX_CLK_USBPHY1>; 687 fsl,anatop = <&anatop>; 688 }; 689 690 usbphy2: usbphy@020ca000 { 691 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; 692 reg = <0x020ca000 0x1000>; 693 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&clks IMX6SX_CLK_USBPHY2>; 695 fsl,anatop = <&anatop>; 696 }; 697 698 snvs: snvs@020cc000 { 699 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 700 reg = <0x020cc000 0x4000>; 701 702 snvs_rtc: snvs-rtc-lp { 703 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 704 regmap = <&snvs>; 705 offset = <0x34>; 706 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 707 }; 708 709 snvs_poweroff: snvs-poweroff { 710 compatible = "syscon-poweroff"; 711 regmap = <&snvs>; 712 offset = <0x38>; 713 value = <0x60>; 714 mask = <0x60>; 715 status = "disabled"; 716 }; 717 718 snvs_pwrkey: snvs-powerkey { 719 compatible = "fsl,sec-v4.0-pwrkey"; 720 regmap = <&snvs>; 721 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 722 linux,keycode = <KEY_POWER>; 723 wakeup-source; 724 }; 725 }; 726 727 epit1: epit@020d0000 { 728 reg = <0x020d0000 0x4000>; 729 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 730 }; 731 732 epit2: epit@020d4000 { 733 reg = <0x020d4000 0x4000>; 734 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 735 }; 736 737 src: src@020d8000 { 738 compatible = "fsl,imx6sx-src", "fsl,imx51-src"; 739 reg = <0x020d8000 0x4000>; 740 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 742 #reset-cells = <1>; 743 }; 744 745 gpc: gpc@020dc000 { 746 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; 747 reg = <0x020dc000 0x4000>; 748 interrupt-controller; 749 #interrupt-cells = <3>; 750 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 751 interrupt-parent = <&intc>; 752 }; 753 754 iomuxc: iomuxc@020e0000 { 755 compatible = "fsl,imx6sx-iomuxc"; 756 reg = <0x020e0000 0x4000>; 757 }; 758 759 gpr: iomuxc-gpr@020e4000 { 760 compatible = "fsl,imx6sx-iomuxc-gpr", 761 "fsl,imx6q-iomuxc-gpr", "syscon"; 762 reg = <0x020e4000 0x4000>; 763 }; 764 765 sdma: sdma@020ec000 { 766 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; 767 reg = <0x020ec000 0x4000>; 768 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&clks IMX6SX_CLK_IPG>, 770 <&clks IMX6SX_CLK_SDMA>; 771 clock-names = "ipg", "ahb"; 772 #dma-cells = <3>; 773 /* imx6sx reuses imx6q sdma firmware */ 774 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 775 }; 776 }; 777 778 aips2: aips-bus@02100000 { 779 compatible = "fsl,aips-bus", "simple-bus"; 780 #address-cells = <1>; 781 #size-cells = <1>; 782 reg = <0x02100000 0x100000>; 783 ranges; 784 785 crypto: caam@2100000 { 786 compatible = "fsl,sec-v4.0"; 787 fsl,sec-era = <4>; 788 #address-cells = <1>; 789 #size-cells = <1>; 790 reg = <0x2100000 0x10000>; 791 ranges = <0 0x2100000 0x10000>; 792 interrupt-parent = <&intc>; 793 clocks = <&clks IMX6SX_CLK_CAAM_MEM>, 794 <&clks IMX6SX_CLK_CAAM_ACLK>, 795 <&clks IMX6SX_CLK_CAAM_IPG>, 796 <&clks IMX6SX_CLK_EIM_SLOW>; 797 clock-names = "mem", "aclk", "ipg", "emi_slow"; 798 799 sec_jr0: jr0@1000 { 800 compatible = "fsl,sec-v4.0-job-ring"; 801 reg = <0x1000 0x1000>; 802 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 803 }; 804 805 sec_jr1: jr1@2000 { 806 compatible = "fsl,sec-v4.0-job-ring"; 807 reg = <0x2000 0x1000>; 808 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 809 }; 810 }; 811 812 usbotg1: usb@02184000 { 813 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 814 reg = <0x02184000 0x200>; 815 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 816 clocks = <&clks IMX6SX_CLK_USBOH3>; 817 fsl,usbphy = <&usbphy1>; 818 fsl,usbmisc = <&usbmisc 0>; 819 fsl,anatop = <&anatop>; 820 ahb-burst-config = <0x0>; 821 tx-burst-size-dword = <0x10>; 822 rx-burst-size-dword = <0x10>; 823 status = "disabled"; 824 }; 825 826 usbotg2: usb@02184200 { 827 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 828 reg = <0x02184200 0x200>; 829 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&clks IMX6SX_CLK_USBOH3>; 831 fsl,usbphy = <&usbphy2>; 832 fsl,usbmisc = <&usbmisc 1>; 833 ahb-burst-config = <0x0>; 834 tx-burst-size-dword = <0x10>; 835 rx-burst-size-dword = <0x10>; 836 status = "disabled"; 837 }; 838 839 usbh: usb@02184400 { 840 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 841 reg = <0x02184400 0x200>; 842 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&clks IMX6SX_CLK_USBOH3>; 844 fsl,usbmisc = <&usbmisc 2>; 845 phy_type = "hsic"; 846 fsl,anatop = <&anatop>; 847 dr_mode = "host"; 848 ahb-burst-config = <0x0>; 849 tx-burst-size-dword = <0x10>; 850 rx-burst-size-dword = <0x10>; 851 status = "disabled"; 852 }; 853 854 usbmisc: usbmisc@02184800 { 855 #index-cells = <1>; 856 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; 857 reg = <0x02184800 0x200>; 858 clocks = <&clks IMX6SX_CLK_USBOH3>; 859 }; 860 861 fec1: ethernet@02188000 { 862 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; 863 reg = <0x02188000 0x4000>; 864 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&clks IMX6SX_CLK_ENET>, 867 <&clks IMX6SX_CLK_ENET_AHB>, 868 <&clks IMX6SX_CLK_ENET_PTP>, 869 <&clks IMX6SX_CLK_ENET_REF>, 870 <&clks IMX6SX_CLK_ENET_PTP>; 871 clock-names = "ipg", "ahb", "ptp", 872 "enet_clk_ref", "enet_out"; 873 fsl,num-tx-queues=<3>; 874 fsl,num-rx-queues=<3>; 875 status = "disabled"; 876 }; 877 878 mlb: mlb@0218c000 { 879 reg = <0x0218c000 0x4000>; 880 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&clks IMX6SX_CLK_MLB>; 884 status = "disabled"; 885 }; 886 887 usdhc1: usdhc@02190000 { 888 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 889 reg = <0x02190000 0x4000>; 890 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&clks IMX6SX_CLK_USDHC1>, 892 <&clks IMX6SX_CLK_USDHC1>, 893 <&clks IMX6SX_CLK_USDHC1>; 894 clock-names = "ipg", "ahb", "per"; 895 bus-width = <4>; 896 status = "disabled"; 897 }; 898 899 usdhc2: usdhc@02194000 { 900 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 901 reg = <0x02194000 0x4000>; 902 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&clks IMX6SX_CLK_USDHC2>, 904 <&clks IMX6SX_CLK_USDHC2>, 905 <&clks IMX6SX_CLK_USDHC2>; 906 clock-names = "ipg", "ahb", "per"; 907 bus-width = <4>; 908 status = "disabled"; 909 }; 910 911 usdhc3: usdhc@02198000 { 912 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 913 reg = <0x02198000 0x4000>; 914 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&clks IMX6SX_CLK_USDHC3>, 916 <&clks IMX6SX_CLK_USDHC3>, 917 <&clks IMX6SX_CLK_USDHC3>; 918 clock-names = "ipg", "ahb", "per"; 919 bus-width = <4>; 920 status = "disabled"; 921 }; 922 923 usdhc4: usdhc@0219c000 { 924 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 925 reg = <0x0219c000 0x4000>; 926 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&clks IMX6SX_CLK_USDHC4>, 928 <&clks IMX6SX_CLK_USDHC4>, 929 <&clks IMX6SX_CLK_USDHC4>; 930 clock-names = "ipg", "ahb", "per"; 931 bus-width = <4>; 932 status = "disabled"; 933 }; 934 935 i2c1: i2c@021a0000 { 936 #address-cells = <1>; 937 #size-cells = <0>; 938 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 939 reg = <0x021a0000 0x4000>; 940 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&clks IMX6SX_CLK_I2C1>; 942 status = "disabled"; 943 }; 944 945 i2c2: i2c@021a4000 { 946 #address-cells = <1>; 947 #size-cells = <0>; 948 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 949 reg = <0x021a4000 0x4000>; 950 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&clks IMX6SX_CLK_I2C2>; 952 status = "disabled"; 953 }; 954 955 i2c3: i2c@021a8000 { 956 #address-cells = <1>; 957 #size-cells = <0>; 958 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 959 reg = <0x021a8000 0x4000>; 960 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&clks IMX6SX_CLK_I2C3>; 962 status = "disabled"; 963 }; 964 965 mmdc: mmdc@021b0000 { 966 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; 967 reg = <0x021b0000 0x4000>; 968 }; 969 970 fec2: ethernet@021b4000 { 971 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; 972 reg = <0x021b4000 0x4000>; 973 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 975 clocks = <&clks IMX6SX_CLK_ENET>, 976 <&clks IMX6SX_CLK_ENET_AHB>, 977 <&clks IMX6SX_CLK_ENET_PTP>, 978 <&clks IMX6SX_CLK_ENET2_REF_125M>, 979 <&clks IMX6SX_CLK_ENET_PTP>; 980 clock-names = "ipg", "ahb", "ptp", 981 "enet_clk_ref", "enet_out"; 982 status = "disabled"; 983 }; 984 985 weim: weim@021b8000 { 986 #address-cells = <2>; 987 #size-cells = <1>; 988 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; 989 reg = <0x021b8000 0x4000>; 990 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&clks IMX6SX_CLK_EIM_SLOW>; 992 fsl,weim-cs-gpr = <&gpr>; 993 status = "disabled"; 994 }; 995 996 ocotp: ocotp@021bc000 { 997 compatible = "fsl,imx6sx-ocotp", "syscon"; 998 reg = <0x021bc000 0x4000>; 999 clocks = <&clks IMX6SX_CLK_OCOTP>; 1000 }; 1001 1002 sai1: sai@021d4000 { 1003 compatible = "fsl,imx6sx-sai"; 1004 reg = <0x021d4000 0x4000>; 1005 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&clks IMX6SX_CLK_SAI1_IPG>, 1007 <&clks IMX6SX_CLK_SAI1>, 1008 <&clks 0>, <&clks 0>; 1009 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1010 dma-names = "rx", "tx"; 1011 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; 1012 status = "disabled"; 1013 }; 1014 1015 audmux: audmux@021d8000 { 1016 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; 1017 reg = <0x021d8000 0x4000>; 1018 status = "disabled"; 1019 }; 1020 1021 sai2: sai@021dc000 { 1022 compatible = "fsl,imx6sx-sai"; 1023 reg = <0x021dc000 0x4000>; 1024 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&clks IMX6SX_CLK_SAI2_IPG>, 1026 <&clks IMX6SX_CLK_SAI2>, 1027 <&clks 0>, <&clks 0>; 1028 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1029 dma-names = "rx", "tx"; 1030 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; 1031 status = "disabled"; 1032 }; 1033 1034 qspi1: qspi@021e0000 { 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 compatible = "fsl,imx6sx-qspi"; 1038 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; 1039 reg-names = "QuadSPI", "QuadSPI-memory"; 1040 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&clks IMX6SX_CLK_QSPI1>, 1042 <&clks IMX6SX_CLK_QSPI1>; 1043 clock-names = "qspi_en", "qspi"; 1044 status = "disabled"; 1045 }; 1046 1047 qspi2: qspi@021e4000 { 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 compatible = "fsl,imx6sx-qspi"; 1051 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; 1052 reg-names = "QuadSPI", "QuadSPI-memory"; 1053 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&clks IMX6SX_CLK_QSPI2>, 1055 <&clks IMX6SX_CLK_QSPI2>; 1056 clock-names = "qspi_en", "qspi"; 1057 status = "disabled"; 1058 }; 1059 1060 uart2: serial@021e8000 { 1061 compatible = "fsl,imx6sx-uart", 1062 "fsl,imx6q-uart", "fsl,imx21-uart"; 1063 reg = <0x021e8000 0x4000>; 1064 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1066 <&clks IMX6SX_CLK_UART_SERIAL>; 1067 clock-names = "ipg", "per"; 1068 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1069 dma-names = "rx", "tx"; 1070 status = "disabled"; 1071 }; 1072 1073 uart3: serial@021ec000 { 1074 compatible = "fsl,imx6sx-uart", 1075 "fsl,imx6q-uart", "fsl,imx21-uart"; 1076 reg = <0x021ec000 0x4000>; 1077 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1079 <&clks IMX6SX_CLK_UART_SERIAL>; 1080 clock-names = "ipg", "per"; 1081 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1082 dma-names = "rx", "tx"; 1083 status = "disabled"; 1084 }; 1085 1086 uart4: serial@021f0000 { 1087 compatible = "fsl,imx6sx-uart", 1088 "fsl,imx6q-uart", "fsl,imx21-uart"; 1089 reg = <0x021f0000 0x4000>; 1090 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1091 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1092 <&clks IMX6SX_CLK_UART_SERIAL>; 1093 clock-names = "ipg", "per"; 1094 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1095 dma-names = "rx", "tx"; 1096 status = "disabled"; 1097 }; 1098 1099 uart5: serial@021f4000 { 1100 compatible = "fsl,imx6sx-uart", 1101 "fsl,imx6q-uart", "fsl,imx21-uart"; 1102 reg = <0x021f4000 0x4000>; 1103 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1105 <&clks IMX6SX_CLK_UART_SERIAL>; 1106 clock-names = "ipg", "per"; 1107 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1108 dma-names = "rx", "tx"; 1109 status = "disabled"; 1110 }; 1111 1112 i2c4: i2c@021f8000 { 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1116 reg = <0x021f8000 0x4000>; 1117 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&clks IMX6SX_CLK_I2C4>; 1119 status = "disabled"; 1120 }; 1121 }; 1122 1123 aips3: aips-bus@02200000 { 1124 compatible = "fsl,aips-bus", "simple-bus"; 1125 #address-cells = <1>; 1126 #size-cells = <1>; 1127 reg = <0x02200000 0x100000>; 1128 ranges; 1129 1130 spba-bus@02200000 { 1131 compatible = "fsl,spba-bus", "simple-bus"; 1132 #address-cells = <1>; 1133 #size-cells = <1>; 1134 reg = <0x02240000 0x40000>; 1135 ranges; 1136 1137 csi1: csi@02214000 { 1138 reg = <0x02214000 0x4000>; 1139 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1140 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, 1141 <&clks IMX6SX_CLK_CSI>, 1142 <&clks IMX6SX_CLK_DCIC1>; 1143 clock-names = "disp-axi", "csi_mclk", "dcic"; 1144 status = "disabled"; 1145 }; 1146 1147 pxp: pxp@02218000 { 1148 reg = <0x02218000 0x4000>; 1149 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&clks IMX6SX_CLK_PXP_AXI>, 1151 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1152 clock-names = "pxp-axi", "disp-axi"; 1153 status = "disabled"; 1154 }; 1155 1156 csi2: csi@0221c000 { 1157 reg = <0x0221c000 0x4000>; 1158 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1159 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, 1160 <&clks IMX6SX_CLK_CSI>, 1161 <&clks IMX6SX_CLK_DCIC2>; 1162 clock-names = "disp-axi", "csi_mclk", "dcic"; 1163 status = "disabled"; 1164 }; 1165 1166 lcdif1: lcdif@02220000 { 1167 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; 1168 reg = <0x02220000 0x4000>; 1169 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>; 1170 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, 1171 <&clks IMX6SX_CLK_LCDIF_APB>, 1172 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1173 clock-names = "pix", "axi", "disp_axi"; 1174 status = "disabled"; 1175 }; 1176 1177 lcdif2: lcdif@02224000 { 1178 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; 1179 reg = <0x02224000 0x4000>; 1180 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>; 1181 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, 1182 <&clks IMX6SX_CLK_LCDIF_APB>, 1183 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1184 clock-names = "pix", "axi", "disp_axi"; 1185 status = "disabled"; 1186 }; 1187 1188 vadc: vadc@02228000 { 1189 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; 1190 reg-names = "vadc-vafe", "vadc-vdec"; 1191 clocks = <&clks IMX6SX_CLK_VADC>, 1192 <&clks IMX6SX_CLK_CSI>; 1193 clock-names = "vadc", "csi"; 1194 status = "disabled"; 1195 }; 1196 }; 1197 1198 adc1: adc@02280000 { 1199 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; 1200 reg = <0x02280000 0x4000>; 1201 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1202 clocks = <&clks IMX6SX_CLK_IPG>; 1203 clock-names = "adc"; 1204 fsl,adck-max-frequency = <30000000>, <40000000>, 1205 <20000000>; 1206 status = "disabled"; 1207 }; 1208 1209 adc2: adc@02284000 { 1210 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; 1211 reg = <0x02284000 0x4000>; 1212 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1213 clocks = <&clks IMX6SX_CLK_IPG>; 1214 clock-names = "adc"; 1215 fsl,adck-max-frequency = <30000000>, <40000000>, 1216 <20000000>; 1217 status = "disabled"; 1218 }; 1219 1220 wdog3: wdog@02288000 { 1221 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 1222 reg = <0x02288000 0x4000>; 1223 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1224 clocks = <&clks IMX6SX_CLK_DUMMY>; 1225 status = "disabled"; 1226 }; 1227 1228 ecspi5: ecspi@0228c000 { 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 1232 reg = <0x0228c000 0x4000>; 1233 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1234 clocks = <&clks IMX6SX_CLK_ECSPI5>, 1235 <&clks IMX6SX_CLK_ECSPI5>; 1236 clock-names = "ipg", "per"; 1237 status = "disabled"; 1238 }; 1239 1240 uart6: serial@022a0000 { 1241 compatible = "fsl,imx6sx-uart", 1242 "fsl,imx6q-uart", "fsl,imx21-uart"; 1243 reg = <0x022a0000 0x4000>; 1244 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1246 <&clks IMX6SX_CLK_UART_SERIAL>; 1247 clock-names = "ipg", "per"; 1248 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; 1249 dma-names = "rx", "tx"; 1250 status = "disabled"; 1251 }; 1252 1253 pwm5: pwm@022a4000 { 1254 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1255 reg = <0x022a4000 0x4000>; 1256 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&clks IMX6SX_CLK_PWM5>, 1258 <&clks IMX6SX_CLK_PWM5>; 1259 clock-names = "ipg", "per"; 1260 #pwm-cells = <2>; 1261 }; 1262 1263 pwm6: pwm@022a8000 { 1264 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1265 reg = <0x022a8000 0x4000>; 1266 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1267 clocks = <&clks IMX6SX_CLK_PWM6>, 1268 <&clks IMX6SX_CLK_PWM6>; 1269 clock-names = "ipg", "per"; 1270 #pwm-cells = <2>; 1271 }; 1272 1273 pwm7: pwm@022ac000 { 1274 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1275 reg = <0x022ac000 0x4000>; 1276 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1277 clocks = <&clks IMX6SX_CLK_PWM7>, 1278 <&clks IMX6SX_CLK_PWM7>; 1279 clock-names = "ipg", "per"; 1280 #pwm-cells = <2>; 1281 }; 1282 1283 pwm8: pwm@0022b0000 { 1284 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1285 reg = <0x0022b0000 0x4000>; 1286 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1287 clocks = <&clks IMX6SX_CLK_PWM8>, 1288 <&clks IMX6SX_CLK_PWM8>; 1289 clock-names = "ipg", "per"; 1290 #pwm-cells = <2>; 1291 }; 1292 }; 1293 1294 pcie: pcie@8ffc000 { 1295 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; 1296 reg = <0x08ffc000 0x4000>; /* DBI */ 1297 #address-cells = <3>; 1298 #size-cells = <2>; 1299 device_type = "pci"; 1300 /* configuration space */ 1301 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 1302 /* downstream I/O */ 1303 0x81000000 0 0 0x08f80000 0 0x00010000 1304 /* non-prefetchable memory */ 1305 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; 1306 bus-range = <0x00 0xff>; 1307 num-lanes = <1>; 1308 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1309 clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, 1310 <&clks IMX6SX_CLK_PCIE_AXI>, 1311 <&clks IMX6SX_CLK_LVDS1_OUT>, 1312 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1313 clock-names = "pcie_ref_125m", "pcie_axi", 1314 "lvds_gate", "display_axi"; 1315 status = "disabled"; 1316 }; 1317 }; 1318 1319 gpu-subsystem { 1320 compatible = "fsl,imx-gpu-subsystem"; 1321 cores = <&gpu>; 1322 }; 1323}; 1324