1/* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9#include <dt-bindings/clock/imx6ul-clock.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include "imx6ul-pinfunc.h" 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 /* 19 * The decompressor and also some bootloaders rely on a 20 * pre-existing /chosen node to be available to insert the 21 * command line and merge other ATAGS info. 22 * Also for U-Boot there must be a pre-existing /memory node. 23 */ 24 chosen {}; 25 memory { device_type = "memory"; reg = <0 0>; }; 26 27 aliases { 28 ethernet0 = &fec1; 29 ethernet1 = &fec2; 30 gpio0 = &gpio1; 31 gpio1 = &gpio2; 32 gpio2 = &gpio3; 33 gpio3 = &gpio4; 34 gpio4 = &gpio5; 35 i2c0 = &i2c1; 36 i2c1 = &i2c2; 37 i2c2 = &i2c3; 38 i2c3 = &i2c4; 39 mmc0 = &usdhc1; 40 mmc1 = &usdhc2; 41 serial0 = &uart1; 42 serial1 = &uart2; 43 serial2 = &uart3; 44 serial3 = &uart4; 45 serial4 = &uart5; 46 serial5 = &uart6; 47 serial6 = &uart7; 48 serial7 = &uart8; 49 sai1 = &sai1; 50 sai2 = &sai2; 51 sai3 = &sai3; 52 spi0 = &ecspi1; 53 spi1 = &ecspi2; 54 spi2 = &ecspi3; 55 spi3 = &ecspi4; 56 usbphy0 = &usbphy1; 57 usbphy1 = &usbphy2; 58 }; 59 60 cpus { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 64 cpu0: cpu@0 { 65 compatible = "arm,cortex-a7"; 66 device_type = "cpu"; 67 reg = <0>; 68 clock-latency = <61036>; /* two CLK32 periods */ 69 operating-points = < 70 /* kHz uV */ 71 528000 1175000 72 396000 1025000 73 198000 950000 74 >; 75 fsl,soc-operating-points = < 76 /* KHz uV */ 77 528000 1175000 78 396000 1175000 79 198000 1175000 80 >; 81 clocks = <&clks IMX6UL_CLK_ARM>, 82 <&clks IMX6UL_CLK_PLL2_BUS>, 83 <&clks IMX6UL_CLK_PLL2_PFD2>, 84 <&clks IMX6UL_CA7_SECONDARY_SEL>, 85 <&clks IMX6UL_CLK_STEP>, 86 <&clks IMX6UL_CLK_PLL1_SW>, 87 <&clks IMX6UL_CLK_PLL1_SYS>, 88 <&clks IMX6UL_PLL1_BYPASS>, 89 <&clks IMX6UL_CLK_PLL1>, 90 <&clks IMX6UL_PLL1_BYPASS_SRC>, 91 <&clks IMX6UL_CLK_OSC>; 92 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", 93 "secondary_sel", "step", "pll1_sw", 94 "pll1_sys", "pll1_bypass", "pll1", 95 "pll1_bypass_src", "osc"; 96 arm-supply = <®_arm>; 97 soc-supply = <®_soc>; 98 }; 99 }; 100 101 intc: interrupt-controller@00a01000 { 102 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 103 #interrupt-cells = <3>; 104 interrupt-controller; 105 reg = <0x00a01000 0x1000>, 106 <0x00a02000 0x2000>, 107 <0x00a04000 0x2000>, 108 <0x00a06000 0x2000>; 109 }; 110 111 ckil: clock-cli { 112 compatible = "fixed-clock"; 113 #clock-cells = <0>; 114 clock-frequency = <32768>; 115 clock-output-names = "ckil"; 116 }; 117 118 osc: clock-osc { 119 compatible = "fixed-clock"; 120 #clock-cells = <0>; 121 clock-frequency = <24000000>; 122 clock-output-names = "osc"; 123 }; 124 125 ipp_di0: clock-di0 { 126 compatible = "fixed-clock"; 127 #clock-cells = <0>; 128 clock-frequency = <0>; 129 clock-output-names = "ipp_di0"; 130 }; 131 132 ipp_di1: clock-di1 { 133 compatible = "fixed-clock"; 134 #clock-cells = <0>; 135 clock-frequency = <0>; 136 clock-output-names = "ipp_di1"; 137 }; 138 139 soc { 140 #address-cells = <1>; 141 #size-cells = <1>; 142 compatible = "simple-bus"; 143 interrupt-parent = <&gpc>; 144 ranges; 145 146 pmu { 147 compatible = "arm,cortex-a7-pmu"; 148 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 149 status = "disabled"; 150 }; 151 152 ocram: sram@00900000 { 153 compatible = "mmio-sram"; 154 reg = <0x00900000 0x20000>; 155 }; 156 157 dma_apbh: dma-apbh@01804000 { 158 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 159 reg = <0x01804000 0x2000>; 160 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, 161 <0 13 IRQ_TYPE_LEVEL_HIGH>, 162 <0 13 IRQ_TYPE_LEVEL_HIGH>, 163 <0 13 IRQ_TYPE_LEVEL_HIGH>; 164 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 165 #dma-cells = <1>; 166 dma-channels = <4>; 167 clocks = <&clks IMX6UL_CLK_APBHDMA>; 168 }; 169 170 gpmi: gpmi-nand@01806000 { 171 compatible = "fsl,imx6q-gpmi-nand"; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 reg = <0x01806000 0x2000>, <0x01808000 0x2000>; 175 reg-names = "gpmi-nand", "bch"; 176 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 177 interrupt-names = "bch"; 178 clocks = <&clks IMX6UL_CLK_GPMI_IO>, 179 <&clks IMX6UL_CLK_GPMI_APB>, 180 <&clks IMX6UL_CLK_GPMI_BCH>, 181 <&clks IMX6UL_CLK_GPMI_BCH_APB>, 182 <&clks IMX6UL_CLK_PER_BCH>; 183 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 184 "gpmi_bch_apb", "per1_bch"; 185 dmas = <&dma_apbh 0>; 186 dma-names = "rx-tx"; 187 status = "disabled"; 188 }; 189 190 aips1: aips-bus@02000000 { 191 compatible = "fsl,aips-bus", "simple-bus"; 192 #address-cells = <1>; 193 #size-cells = <1>; 194 reg = <0x02000000 0x100000>; 195 ranges; 196 197 spba-bus@02000000 { 198 compatible = "fsl,spba-bus", "simple-bus"; 199 #address-cells = <1>; 200 #size-cells = <1>; 201 reg = <0x02000000 0x40000>; 202 ranges; 203 204 ecspi1: ecspi@02008000 { 205 #address-cells = <1>; 206 #size-cells = <0>; 207 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 208 reg = <0x02008000 0x4000>; 209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&clks IMX6UL_CLK_ECSPI1>, 211 <&clks IMX6UL_CLK_ECSPI1>; 212 clock-names = "ipg", "per"; 213 status = "disabled"; 214 }; 215 216 ecspi2: ecspi@0200c000 { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 220 reg = <0x0200c000 0x4000>; 221 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&clks IMX6UL_CLK_ECSPI2>, 223 <&clks IMX6UL_CLK_ECSPI2>; 224 clock-names = "ipg", "per"; 225 status = "disabled"; 226 }; 227 228 ecspi3: ecspi@02010000 { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 232 reg = <0x02010000 0x4000>; 233 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&clks IMX6UL_CLK_ECSPI3>, 235 <&clks IMX6UL_CLK_ECSPI3>; 236 clock-names = "ipg", "per"; 237 status = "disabled"; 238 }; 239 240 ecspi4: ecspi@02014000 { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 244 reg = <0x02014000 0x4000>; 245 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&clks IMX6UL_CLK_ECSPI4>, 247 <&clks IMX6UL_CLK_ECSPI4>; 248 clock-names = "ipg", "per"; 249 status = "disabled"; 250 }; 251 252 uart7: serial@02018000 { 253 compatible = "fsl,imx6ul-uart", 254 "fsl,imx6q-uart"; 255 reg = <0x02018000 0x4000>; 256 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&clks IMX6UL_CLK_UART7_IPG>, 258 <&clks IMX6UL_CLK_UART7_SERIAL>; 259 clock-names = "ipg", "per"; 260 status = "disabled"; 261 }; 262 263 uart1: serial@02020000 { 264 compatible = "fsl,imx6ul-uart", 265 "fsl,imx6q-uart"; 266 reg = <0x02020000 0x4000>; 267 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&clks IMX6UL_CLK_UART1_IPG>, 269 <&clks IMX6UL_CLK_UART1_SERIAL>; 270 clock-names = "ipg", "per"; 271 status = "disabled"; 272 }; 273 274 uart8: serial@02024000 { 275 compatible = "fsl,imx6ul-uart", 276 "fsl,imx6q-uart"; 277 reg = <0x02024000 0x4000>; 278 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&clks IMX6UL_CLK_UART8_IPG>, 280 <&clks IMX6UL_CLK_UART8_SERIAL>; 281 clock-names = "ipg", "per"; 282 status = "disabled"; 283 }; 284 285 sai1: sai@02028000 { 286 #sound-dai-cells = <0>; 287 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; 288 reg = <0x02028000 0x4000>; 289 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&clks IMX6UL_CLK_SAI1_IPG>, 291 <&clks IMX6UL_CLK_SAI1>, 292 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; 293 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 294 dmas = <&sdma 35 24 0>, 295 <&sdma 36 24 0>; 296 dma-names = "rx", "tx"; 297 status = "disabled"; 298 }; 299 300 sai2: sai@0202c000 { 301 #sound-dai-cells = <0>; 302 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; 303 reg = <0x0202c000 0x4000>; 304 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&clks IMX6UL_CLK_SAI2_IPG>, 306 <&clks IMX6UL_CLK_SAI2>, 307 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; 308 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 309 dmas = <&sdma 37 24 0>, 310 <&sdma 38 24 0>; 311 dma-names = "rx", "tx"; 312 status = "disabled"; 313 }; 314 315 sai3: sai@02030000 { 316 #sound-dai-cells = <0>; 317 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; 318 reg = <0x02030000 0x4000>; 319 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&clks IMX6UL_CLK_SAI3_IPG>, 321 <&clks IMX6UL_CLK_SAI3>, 322 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; 323 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 324 dmas = <&sdma 39 24 0>, 325 <&sdma 40 24 0>; 326 dma-names = "rx", "tx"; 327 status = "disabled"; 328 }; 329 }; 330 331 tsc: tsc@02040000 { 332 compatible = "fsl,imx6ul-tsc"; 333 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; 334 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&clks IMX6UL_CLK_IPG>, 337 <&clks IMX6UL_CLK_ADC2>; 338 clock-names = "tsc", "adc"; 339 status = "disabled"; 340 }; 341 342 pwm1: pwm@02080000 { 343 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 344 reg = <0x02080000 0x4000>; 345 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&clks IMX6UL_CLK_PWM1>, 347 <&clks IMX6UL_CLK_PWM1>; 348 clock-names = "ipg", "per"; 349 #pwm-cells = <2>; 350 status = "disabled"; 351 }; 352 353 pwm2: pwm@02084000 { 354 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 355 reg = <0x02084000 0x4000>; 356 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&clks IMX6UL_CLK_PWM2>, 358 <&clks IMX6UL_CLK_PWM2>; 359 clock-names = "ipg", "per"; 360 #pwm-cells = <2>; 361 status = "disabled"; 362 }; 363 364 pwm3: pwm@02088000 { 365 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 366 reg = <0x02088000 0x4000>; 367 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&clks IMX6UL_CLK_PWM3>, 369 <&clks IMX6UL_CLK_PWM3>; 370 clock-names = "ipg", "per"; 371 #pwm-cells = <2>; 372 status = "disabled"; 373 }; 374 375 pwm4: pwm@0208c000 { 376 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 377 reg = <0x0208c000 0x4000>; 378 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&clks IMX6UL_CLK_PWM4>, 380 <&clks IMX6UL_CLK_PWM4>; 381 clock-names = "ipg", "per"; 382 #pwm-cells = <2>; 383 status = "disabled"; 384 }; 385 386 can1: flexcan@02090000 { 387 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; 388 reg = <0x02090000 0x4000>; 389 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&clks IMX6UL_CLK_CAN1_IPG>, 391 <&clks IMX6UL_CLK_CAN1_SERIAL>; 392 clock-names = "ipg", "per"; 393 status = "disabled"; 394 }; 395 396 can2: flexcan@02094000 { 397 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; 398 reg = <0x02094000 0x4000>; 399 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&clks IMX6UL_CLK_CAN2_IPG>, 401 <&clks IMX6UL_CLK_CAN2_SERIAL>; 402 clock-names = "ipg", "per"; 403 status = "disabled"; 404 }; 405 406 gpt1: gpt@02098000 { 407 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; 408 reg = <0x02098000 0x4000>; 409 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&clks IMX6UL_CLK_GPT1_BUS>, 411 <&clks IMX6UL_CLK_GPT1_SERIAL>; 412 clock-names = "ipg", "per"; 413 }; 414 415 gpio1: gpio@0209c000 { 416 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 417 reg = <0x0209c000 0x4000>; 418 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 420 gpio-controller; 421 #gpio-cells = <2>; 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, 425 <&iomuxc 16 33 16>; 426 }; 427 428 gpio2: gpio@020a0000 { 429 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 430 reg = <0x020a0000 0x4000>; 431 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 433 gpio-controller; 434 #gpio-cells = <2>; 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; 438 }; 439 440 gpio3: gpio@020a4000 { 441 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 442 reg = <0x020a4000 0x4000>; 443 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 445 gpio-controller; 446 #gpio-cells = <2>; 447 interrupt-controller; 448 #interrupt-cells = <2>; 449 gpio-ranges = <&iomuxc 0 65 29>; 450 }; 451 452 gpio4: gpio@020a8000 { 453 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 454 reg = <0x020a8000 0x4000>; 455 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 457 gpio-controller; 458 #gpio-cells = <2>; 459 interrupt-controller; 460 #interrupt-cells = <2>; 461 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; 462 }; 463 464 gpio5: gpio@020ac000 { 465 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 466 reg = <0x020ac000 0x4000>; 467 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 469 gpio-controller; 470 #gpio-cells = <2>; 471 interrupt-controller; 472 #interrupt-cells = <2>; 473 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; 474 }; 475 476 fec2: ethernet@020b4000 { 477 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; 478 reg = <0x020b4000 0x4000>; 479 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&clks IMX6UL_CLK_ENET>, 482 <&clks IMX6UL_CLK_ENET_AHB>, 483 <&clks IMX6UL_CLK_ENET_PTP>, 484 <&clks IMX6UL_CLK_ENET2_REF_125M>, 485 <&clks IMX6UL_CLK_ENET2_REF_125M>; 486 clock-names = "ipg", "ahb", "ptp", 487 "enet_clk_ref", "enet_out"; 488 fsl,num-tx-queues=<1>; 489 fsl,num-rx-queues=<1>; 490 status = "disabled"; 491 }; 492 493 kpp: kpp@020b8000 { 494 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp"; 495 reg = <0x020b8000 0x4000>; 496 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&clks IMX6UL_CLK_KPP>; 498 status = "disabled"; 499 }; 500 501 wdog1: wdog@020bc000 { 502 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 503 reg = <0x020bc000 0x4000>; 504 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&clks IMX6UL_CLK_WDOG1>; 506 }; 507 508 wdog2: wdog@020c0000 { 509 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 510 reg = <0x020c0000 0x4000>; 511 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&clks IMX6UL_CLK_WDOG2>; 513 status = "disabled"; 514 }; 515 516 clks: ccm@020c4000 { 517 compatible = "fsl,imx6ul-ccm"; 518 reg = <0x020c4000 0x4000>; 519 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 521 #clock-cells = <1>; 522 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; 523 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; 524 }; 525 526 anatop: anatop@020c8000 { 527 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", 528 "syscon", "simple-bus"; 529 reg = <0x020c8000 0x1000>; 530 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 533 534 reg_3p0: regulator-3p0 { 535 compatible = "fsl,anatop-regulator"; 536 regulator-name = "vdd3p0"; 537 regulator-min-microvolt = <2625000>; 538 regulator-max-microvolt = <3400000>; 539 anatop-reg-offset = <0x120>; 540 anatop-vol-bit-shift = <8>; 541 anatop-vol-bit-width = <5>; 542 anatop-min-bit-val = <0>; 543 anatop-min-voltage = <2625000>; 544 anatop-max-voltage = <3400000>; 545 anatop-enable-bit = <0>; 546 }; 547 548 reg_arm: regulator-vddcore { 549 compatible = "fsl,anatop-regulator"; 550 regulator-name = "cpu"; 551 regulator-min-microvolt = <725000>; 552 regulator-max-microvolt = <1450000>; 553 regulator-always-on; 554 anatop-reg-offset = <0x140>; 555 anatop-vol-bit-shift = <0>; 556 anatop-vol-bit-width = <5>; 557 anatop-delay-reg-offset = <0x170>; 558 anatop-delay-bit-shift = <24>; 559 anatop-delay-bit-width = <2>; 560 anatop-min-bit-val = <1>; 561 anatop-min-voltage = <725000>; 562 anatop-max-voltage = <1450000>; 563 }; 564 565 reg_soc: regulator-vddsoc { 566 compatible = "fsl,anatop-regulator"; 567 regulator-name = "vddsoc"; 568 regulator-min-microvolt = <725000>; 569 regulator-max-microvolt = <1450000>; 570 regulator-always-on; 571 anatop-reg-offset = <0x140>; 572 anatop-vol-bit-shift = <18>; 573 anatop-vol-bit-width = <5>; 574 anatop-delay-reg-offset = <0x170>; 575 anatop-delay-bit-shift = <28>; 576 anatop-delay-bit-width = <2>; 577 anatop-min-bit-val = <1>; 578 anatop-min-voltage = <725000>; 579 anatop-max-voltage = <1450000>; 580 }; 581 }; 582 583 usbphy1: usbphy@020c9000 { 584 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 585 reg = <0x020c9000 0x1000>; 586 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&clks IMX6UL_CLK_USBPHY1>; 588 phy-3p0-supply = <®_3p0>; 589 fsl,anatop = <&anatop>; 590 }; 591 592 usbphy2: usbphy@020ca000 { 593 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 594 reg = <0x020ca000 0x1000>; 595 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&clks IMX6UL_CLK_USBPHY2>; 597 phy-3p0-supply = <®_3p0>; 598 fsl,anatop = <&anatop>; 599 }; 600 601 snvs: snvs@020cc000 { 602 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 603 reg = <0x020cc000 0x4000>; 604 605 snvs_rtc: snvs-rtc-lp { 606 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 607 regmap = <&snvs>; 608 offset = <0x34>; 609 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 611 }; 612 613 snvs_poweroff: snvs-poweroff { 614 compatible = "syscon-poweroff"; 615 regmap = <&snvs>; 616 offset = <0x38>; 617 value = <0x60>; 618 mask = <0x60>; 619 status = "disabled"; 620 }; 621 622 snvs_pwrkey: snvs-powerkey { 623 compatible = "fsl,sec-v4.0-pwrkey"; 624 regmap = <&snvs>; 625 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 626 linux,keycode = <KEY_POWER>; 627 wakeup-source; 628 }; 629 }; 630 631 epit1: epit@020d0000 { 632 reg = <0x020d0000 0x4000>; 633 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 634 }; 635 636 epit2: epit@020d4000 { 637 reg = <0x020d4000 0x4000>; 638 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 639 }; 640 641 src: src@020d8000 { 642 compatible = "fsl,imx6ul-src", "fsl,imx51-src"; 643 reg = <0x020d8000 0x4000>; 644 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 646 #reset-cells = <1>; 647 }; 648 649 gpc: gpc@020dc000 { 650 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; 651 reg = <0x020dc000 0x4000>; 652 interrupt-controller; 653 #interrupt-cells = <3>; 654 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 655 interrupt-parent = <&intc>; 656 }; 657 658 iomuxc: iomuxc@020e0000 { 659 compatible = "fsl,imx6ul-iomuxc"; 660 reg = <0x020e0000 0x4000>; 661 }; 662 663 gpr: iomuxc-gpr@020e4000 { 664 compatible = "fsl,imx6ul-iomuxc-gpr", 665 "fsl,imx6q-iomuxc-gpr", "syscon"; 666 reg = <0x020e4000 0x4000>; 667 }; 668 669 gpt2: gpt@020e8000 { 670 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; 671 reg = <0x020e8000 0x4000>; 672 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&clks IMX6UL_CLK_GPT2_BUS>, 674 <&clks IMX6UL_CLK_GPT2_SERIAL>; 675 clock-names = "ipg", "per"; 676 }; 677 678 sdma: sdma@020ec000 { 679 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", 680 "fsl,imx35-sdma"; 681 reg = <0x020ec000 0x4000>; 682 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&clks IMX6UL_CLK_IPG>, 684 <&clks IMX6UL_CLK_SDMA>; 685 clock-names = "ipg", "ahb"; 686 #dma-cells = <3>; 687 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 688 }; 689 690 pwm5: pwm@020f0000 { 691 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 692 reg = <0x020f0000 0x4000>; 693 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&clks IMX6UL_CLK_PWM5>, 695 <&clks IMX6UL_CLK_PWM5>; 696 clock-names = "ipg", "per"; 697 #pwm-cells = <2>; 698 status = "disabled"; 699 }; 700 701 pwm6: pwm@020f4000 { 702 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 703 reg = <0x020f4000 0x4000>; 704 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&clks IMX6UL_CLK_PWM6>, 706 <&clks IMX6UL_CLK_PWM6>; 707 clock-names = "ipg", "per"; 708 #pwm-cells = <2>; 709 status = "disabled"; 710 }; 711 712 pwm7: pwm@020f8000 { 713 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 714 reg = <0x020f8000 0x4000>; 715 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&clks IMX6UL_CLK_PWM7>, 717 <&clks IMX6UL_CLK_PWM7>; 718 clock-names = "ipg", "per"; 719 #pwm-cells = <2>; 720 status = "disabled"; 721 }; 722 723 pwm8: pwm@020fc000 { 724 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 725 reg = <0x020fc000 0x4000>; 726 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&clks IMX6UL_CLK_PWM8>, 728 <&clks IMX6UL_CLK_PWM8>; 729 clock-names = "ipg", "per"; 730 #pwm-cells = <2>; 731 status = "disabled"; 732 }; 733 }; 734 735 aips2: aips-bus@02100000 { 736 compatible = "fsl,aips-bus", "simple-bus"; 737 #address-cells = <1>; 738 #size-cells = <1>; 739 reg = <0x02100000 0x100000>; 740 ranges; 741 742 usbotg1: usb@02184000 { 743 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; 744 reg = <0x02184000 0x200>; 745 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&clks IMX6UL_CLK_USBOH3>; 747 fsl,usbphy = <&usbphy1>; 748 fsl,usbmisc = <&usbmisc 0>; 749 fsl,anatop = <&anatop>; 750 ahb-burst-config = <0x0>; 751 tx-burst-size-dword = <0x10>; 752 rx-burst-size-dword = <0x10>; 753 status = "disabled"; 754 }; 755 756 usbotg2: usb@02184200 { 757 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; 758 reg = <0x02184200 0x200>; 759 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&clks IMX6UL_CLK_USBOH3>; 761 fsl,usbphy = <&usbphy2>; 762 fsl,usbmisc = <&usbmisc 1>; 763 ahb-burst-config = <0x0>; 764 tx-burst-size-dword = <0x10>; 765 rx-burst-size-dword = <0x10>; 766 status = "disabled"; 767 }; 768 769 usbmisc: usbmisc@02184800 { 770 #index-cells = <1>; 771 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; 772 reg = <0x02184800 0x200>; 773 }; 774 775 fec1: ethernet@02188000 { 776 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; 777 reg = <0x02188000 0x4000>; 778 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&clks IMX6UL_CLK_ENET>, 781 <&clks IMX6UL_CLK_ENET_AHB>, 782 <&clks IMX6UL_CLK_ENET_PTP>, 783 <&clks IMX6UL_CLK_ENET_REF>, 784 <&clks IMX6UL_CLK_ENET_REF>; 785 clock-names = "ipg", "ahb", "ptp", 786 "enet_clk_ref", "enet_out"; 787 fsl,num-tx-queues=<1>; 788 fsl,num-rx-queues=<1>; 789 status = "disabled"; 790 }; 791 792 usdhc1: usdhc@02190000 { 793 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; 794 reg = <0x02190000 0x4000>; 795 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&clks IMX6UL_CLK_USDHC1>, 797 <&clks IMX6UL_CLK_USDHC1>, 798 <&clks IMX6UL_CLK_USDHC1>; 799 clock-names = "ipg", "ahb", "per"; 800 bus-width = <4>; 801 status = "disabled"; 802 }; 803 804 usdhc2: usdhc@02194000 { 805 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; 806 reg = <0x02194000 0x4000>; 807 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 808 clocks = <&clks IMX6UL_CLK_USDHC2>, 809 <&clks IMX6UL_CLK_USDHC2>, 810 <&clks IMX6UL_CLK_USDHC2>; 811 clock-names = "ipg", "ahb", "per"; 812 bus-width = <4>; 813 status = "disabled"; 814 }; 815 816 adc1: adc@02198000 { 817 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; 818 reg = <0x02198000 0x4000>; 819 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&clks IMX6UL_CLK_ADC1>; 821 num-channels = <2>; 822 clock-names = "adc"; 823 fsl,adck-max-frequency = <30000000>, <40000000>, 824 <20000000>; 825 status = "disabled"; 826 }; 827 828 i2c1: i2c@021a0000 { 829 #address-cells = <1>; 830 #size-cells = <0>; 831 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 832 reg = <0x021a0000 0x4000>; 833 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 834 clocks = <&clks IMX6UL_CLK_I2C1>; 835 status = "disabled"; 836 }; 837 838 i2c2: i2c@021a4000 { 839 #address-cells = <1>; 840 #size-cells = <0>; 841 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 842 reg = <0x021a4000 0x4000>; 843 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&clks IMX6UL_CLK_I2C2>; 845 status = "disabled"; 846 }; 847 848 i2c3: i2c@021a8000 { 849 #address-cells = <1>; 850 #size-cells = <0>; 851 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 852 reg = <0x021a8000 0x4000>; 853 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&clks IMX6UL_CLK_I2C3>; 855 status = "disabled"; 856 }; 857 858 mmdc: mmdc@021b0000 { 859 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; 860 reg = <0x021b0000 0x4000>; 861 }; 862 863 ocotp: ocotp-ctrl@021bc000 { 864 compatible = "fsl,imx6ul-ocotp", "syscon"; 865 reg = <0x021bc000 0x4000>; 866 clocks = <&clks IMX6UL_CLK_OCOTP>; 867 }; 868 869 lcdif: lcdif@021c8000 { 870 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; 871 reg = <0x021c8000 0x4000>; 872 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, 874 <&clks IMX6UL_CLK_LCDIF_APB>, 875 <&clks IMX6UL_CLK_DUMMY>; 876 clock-names = "pix", "axi", "disp_axi"; 877 status = "disabled"; 878 }; 879 880 qspi: qspi@021e0000 { 881 #address-cells = <1>; 882 #size-cells = <0>; 883 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; 884 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; 885 reg-names = "QuadSPI", "QuadSPI-memory"; 886 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&clks IMX6UL_CLK_QSPI>, 888 <&clks IMX6UL_CLK_QSPI>; 889 clock-names = "qspi_en", "qspi"; 890 status = "disabled"; 891 }; 892 893 uart2: serial@021e8000 { 894 compatible = "fsl,imx6ul-uart", 895 "fsl,imx6q-uart"; 896 reg = <0x021e8000 0x4000>; 897 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&clks IMX6UL_CLK_UART2_IPG>, 899 <&clks IMX6UL_CLK_UART2_SERIAL>; 900 clock-names = "ipg", "per"; 901 status = "disabled"; 902 }; 903 904 uart3: serial@021ec000 { 905 compatible = "fsl,imx6ul-uart", 906 "fsl,imx6q-uart"; 907 reg = <0x021ec000 0x4000>; 908 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&clks IMX6UL_CLK_UART3_IPG>, 910 <&clks IMX6UL_CLK_UART3_SERIAL>; 911 clock-names = "ipg", "per"; 912 status = "disabled"; 913 }; 914 915 uart4: serial@021f0000 { 916 compatible = "fsl,imx6ul-uart", 917 "fsl,imx6q-uart"; 918 reg = <0x021f0000 0x4000>; 919 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&clks IMX6UL_CLK_UART4_IPG>, 921 <&clks IMX6UL_CLK_UART4_SERIAL>; 922 clock-names = "ipg", "per"; 923 status = "disabled"; 924 }; 925 926 uart5: serial@021f4000 { 927 compatible = "fsl,imx6ul-uart", 928 "fsl,imx6q-uart"; 929 reg = <0x021f4000 0x4000>; 930 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&clks IMX6UL_CLK_UART5_IPG>, 932 <&clks IMX6UL_CLK_UART5_SERIAL>; 933 clock-names = "ipg", "per"; 934 status = "disabled"; 935 }; 936 937 i2c4: i2c@021f8000 { 938 #address-cells = <1>; 939 #size-cells = <0>; 940 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 941 reg = <0x021f8000 0x4000>; 942 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&clks IMX6UL_CLK_I2C4>; 944 status = "disabled"; 945 }; 946 947 uart6: serial@021fc000 { 948 compatible = "fsl,imx6ul-uart", 949 "fsl,imx6q-uart"; 950 reg = <0x021fc000 0x4000>; 951 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&clks IMX6UL_CLK_UART6_IPG>, 953 <&clks IMX6UL_CLK_UART6_SERIAL>; 954 clock-names = "ipg", "per"; 955 status = "disabled"; 956 }; 957 }; 958 }; 959}; 960