1/* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43/dts-v1/; 44 45#include "imx7d.dtsi" 46 47/ { 48 model = "Freescale i.MX7 SabreSD Board"; 49 compatible = "fsl,imx7d-sdb", "fsl,imx7d"; 50 51 memory { 52 reg = <0x80000000 0x80000000>; 53 }; 54 55 spi4 { 56 compatible = "spi-gpio"; 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_spi4>; 59 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; 60 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; 61 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 62 num-chipselects = <1>; 63 #address-cells = <1>; 64 #size-cells = <0>; 65 66 extended_io: gpio-expander@0 { 67 compatible = "fairchild,74hc595"; 68 gpio-controller; 69 #gpio-cells = <2>; 70 reg = <0>; 71 registers-number = <1>; 72 spi-max-frequency = <100000>; 73 }; 74 }; 75 76 reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 77 compatible = "regulator-fixed"; 78 regulator-name = "usb_otg1_vbus"; 79 regulator-min-microvolt = <5000000>; 80 regulator-max-microvolt = <5000000>; 81 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 82 enable-active-high; 83 }; 84 85 reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 86 compatible = "regulator-fixed"; 87 regulator-name = "usb_otg2_vbus"; 88 regulator-min-microvolt = <5000000>; 89 regulator-max-microvolt = <5000000>; 90 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; 91 enable-active-high; 92 }; 93 94 reg_can2_3v3: regulator-can2-3v3 { 95 compatible = "regulator-fixed"; 96 regulator-name = "can2-3v3"; 97 regulator-min-microvolt = <3300000>; 98 regulator-max-microvolt = <3300000>; 99 gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; 100 }; 101 102 reg_vref_1v8: regulator-vref-1v8 { 103 compatible = "regulator-fixed"; 104 regulator-name = "vref-1v8"; 105 regulator-min-microvolt = <1800000>; 106 regulator-max-microvolt = <1800000>; 107 }; 108 109 reg_brcm: regulator-brcm { 110 compatible = "regulator-fixed"; 111 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 112 enable-active-high; 113 regulator-name = "brcm_reg"; 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_brcm_reg>; 116 regulator-min-microvolt = <3300000>; 117 regulator-max-microvolt = <3300000>; 118 startup-delay-us = <200000>; 119 }; 120 121 reg_lcd_3v3: regulator-lcd-3v3 { 122 compatible = "regulator-fixed"; 123 regulator-name = "lcd-3v3"; 124 regulator-min-microvolt = <3300000>; 125 regulator-max-microvolt = <3300000>; 126 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; 127 }; 128 129 reg_can2_3v3: regulator-can2-3v3 { 130 compatible = "regulator-fixed"; 131 regulator-name = "can2-3v3"; 132 pinctrl-names = "default"; 133 pinctrl-0 = <&pinctrl_flexcan2_reg>; 134 regulator-min-microvolt = <3300000>; 135 regulator-max-microvolt = <3300000>; 136 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; 137 }; 138 139 panel { 140 compatible = "innolux,at043tn24"; 141 pinctrl-0 = <&pinctrl_backlight>; 142 enable-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 143 power-supply = <®_lcd_3v3>; 144 145 port { 146 panel_in: endpoint { 147 remote-endpoint = <&display_out>; 148 }; 149 }; 150 }; 151}; 152 153&adc1 { 154 vref-supply = <®_vref_1v8>; 155 status = "okay"; 156}; 157 158&adc2 { 159 vref-supply = <®_vref_1v8>; 160 status = "okay"; 161}; 162 163&cpu0 { 164 arm-supply = <&sw1a_reg>; 165}; 166 167&ecspi3 { 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_ecspi3>; 170 cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; 171 status = "okay"; 172 173 tsc2046@0 { 174 compatible = "ti,tsc2046"; 175 reg = <0>; 176 spi-max-frequency = <1000000>; 177 pinctrl-names ="default"; 178 pinctrl-0 = <&pinctrl_tsc2046_pendown>; 179 interrupt-parent = <&gpio2>; 180 interrupts = <29 0>; 181 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; 182 ti,x-min = /bits/ 16 <0>; 183 ti,x-max = /bits/ 16 <0>; 184 ti,y-min = /bits/ 16 <0>; 185 ti,y-max = /bits/ 16 <0>; 186 ti,pressure-max = /bits/ 16 <0>; 187 ti,x-plate-ohms = /bits/ 16 <400>; 188 wakeup-source; 189 }; 190}; 191 192&fec1 { 193 pinctrl-names = "default"; 194 pinctrl-0 = <&pinctrl_enet1>; 195 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, 196 <&clks IMX7D_ENET1_TIME_ROOT_CLK>; 197 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 198 assigned-clock-rates = <0>, <100000000>; 199 phy-mode = "rgmii"; 200 phy-handle = <ðphy0>; 201 fsl,magic-packet; 202 phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; 203 status = "okay"; 204 205 mdio { 206 #address-cells = <1>; 207 #size-cells = <0>; 208 209 ethphy0: ethernet-phy@0 { 210 reg = <0>; 211 }; 212 213 ethphy1: ethernet-phy@1 { 214 reg = <1>; 215 }; 216 }; 217}; 218 219&fec2 { 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pinctrl_enet2>; 222 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, 223 <&clks IMX7D_ENET2_TIME_ROOT_CLK>; 224 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 225 assigned-clock-rates = <0>, <100000000>; 226 phy-mode = "rgmii"; 227 phy-handle = <ðphy1>; 228 fsl,magic-packet; 229 status = "okay"; 230}; 231 232&flexcan2 { 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_flexcan2>; 235 xceiver-supply = <®_can2_3v3>; 236 status = "okay"; 237}; 238 239&i2c1 { 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_i2c1>; 242 status = "okay"; 243 244 pmic: pfuze3000@08 { 245 compatible = "fsl,pfuze3000"; 246 reg = <0x08>; 247 248 regulators { 249 sw1a_reg: sw1a { 250 regulator-min-microvolt = <700000>; 251 regulator-max-microvolt = <1475000>; 252 regulator-boot-on; 253 regulator-always-on; 254 regulator-ramp-delay = <6250>; 255 }; 256 257 /* use sw1c_reg to align with pfuze100/pfuze200 */ 258 sw1c_reg: sw1b { 259 regulator-min-microvolt = <700000>; 260 regulator-max-microvolt = <1475000>; 261 regulator-boot-on; 262 regulator-always-on; 263 regulator-ramp-delay = <6250>; 264 }; 265 266 sw2_reg: sw2 { 267 regulator-min-microvolt = <1500000>; 268 regulator-max-microvolt = <1850000>; 269 regulator-boot-on; 270 regulator-always-on; 271 }; 272 273 sw3a_reg: sw3 { 274 regulator-min-microvolt = <900000>; 275 regulator-max-microvolt = <1650000>; 276 regulator-boot-on; 277 regulator-always-on; 278 }; 279 280 swbst_reg: swbst { 281 regulator-min-microvolt = <5000000>; 282 regulator-max-microvolt = <5150000>; 283 }; 284 285 snvs_reg: vsnvs { 286 regulator-min-microvolt = <1000000>; 287 regulator-max-microvolt = <3000000>; 288 regulator-boot-on; 289 regulator-always-on; 290 }; 291 292 vref_reg: vrefddr { 293 regulator-boot-on; 294 regulator-always-on; 295 }; 296 297 vgen1_reg: vldo1 { 298 regulator-min-microvolt = <1800000>; 299 regulator-max-microvolt = <3300000>; 300 regulator-always-on; 301 }; 302 303 vgen2_reg: vldo2 { 304 regulator-min-microvolt = <800000>; 305 regulator-max-microvolt = <1550000>; 306 }; 307 308 vgen3_reg: vccsd { 309 regulator-min-microvolt = <2850000>; 310 regulator-max-microvolt = <3300000>; 311 regulator-always-on; 312 }; 313 314 vgen4_reg: v33 { 315 regulator-min-microvolt = <2850000>; 316 regulator-max-microvolt = <3300000>; 317 regulator-always-on; 318 }; 319 320 vgen5_reg: vldo3 { 321 regulator-min-microvolt = <1800000>; 322 regulator-max-microvolt = <3300000>; 323 regulator-always-on; 324 }; 325 326 vgen6_reg: vldo4 { 327 regulator-min-microvolt = <2800000>; 328 regulator-max-microvolt = <2800000>; 329 regulator-always-on; 330 }; 331 }; 332 }; 333}; 334 335&i2c2 { 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_i2c2>; 338 status = "okay"; 339}; 340 341&i2c3 { 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pinctrl_i2c3>; 344 status = "okay"; 345}; 346 347&i2c4 { 348 pinctrl-names = "default"; 349 pinctrl-0 = <&pinctrl_i2c4>; 350 status = "okay"; 351 352 codec: wm8960@1a { 353 compatible = "wlf,wm8960"; 354 reg = <0x1a>; 355 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; 356 clock-names = "mclk"; 357 wlf,shared-lrclk; 358 }; 359}; 360 361&lcdif { 362 pinctrl-names = "default"; 363 pinctrl-0 = <&pinctrl_lcdif>; 364 status = "okay"; 365 366 port { 367 display_out: endpoint { 368 remote-endpoint = <&panel_in>; 369 }; 370 }; 371}; 372 373&pcie { 374 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; 375 status = "okay"; 376}; 377 378&uart1 { 379 pinctrl-names = "default"; 380 pinctrl-0 = <&pinctrl_uart1>; 381 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; 382 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 383 status = "okay"; 384}; 385 386&uart6 { 387 pinctrl-names = "default"; 388 pinctrl-0 = <&pinctrl_uart6>; 389 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; 390 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 391 uart-has-rtscts; 392 status = "okay"; 393}; 394 395&usbotg1 { 396 vbus-supply = <®_usb_otg1_vbus>; 397 status = "okay"; 398}; 399 400&usbotg2 { 401 vbus-supply = <®_usb_otg2_vbus>; 402 dr_mode = "host"; 403 status = "okay"; 404}; 405 406&usdhc1 { 407 pinctrl-names = "default"; 408 pinctrl-0 = <&pinctrl_usdhc1>; 409 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 410 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 411 wakeup-source; 412 keep-power-in-suspend; 413 status = "okay"; 414}; 415 416&usdhc2 { 417 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 418 pinctrl-0 = <&pinctrl_usdhc2>; 419 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 420 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 421 wakeup-source; 422 keep-power-in-suspend; 423 non-removable; 424 vmmc-supply = <®_brcm>; 425 fsl,tuning-step = <2>; 426 status = "okay"; 427}; 428 429&usdhc3 { 430 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 431 pinctrl-0 = <&pinctrl_usdhc3>; 432 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 433 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 434 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; 435 assigned-clock-rates = <400000000>; 436 bus-width = <8>; 437 fsl,tuning-step = <2>; 438 non-removable; 439 status = "okay"; 440}; 441 442&wdog1 { 443 pinctrl-names = "default"; 444 pinctrl-0 = <&pinctrl_wdog>; 445 fsl,ext-reset-output; 446}; 447 448&iomuxc { 449 pinctrl-names = "default"; 450 pinctrl-0 = <&pinctrl_hog>; 451 452 imx7d-sdb { 453 pinctrl_brcm_reg: brcmreggrp { 454 fsl,pins = < 455 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 456 >; 457 }; 458 459 pinctrl_ecspi3: ecspi3grp { 460 fsl,pins = < 461 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 462 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 463 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 464 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 465 >; 466 }; 467 468 pinctrl_enet1: enet1grp { 469 fsl,pins = < 470 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 471 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 472 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 473 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 474 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 475 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 476 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 477 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 478 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 479 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 480 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 481 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 482 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 483 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 484 >; 485 }; 486 487 pinctrl_enet2: enet2grp { 488 fsl,pins = < 489 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 490 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 491 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 492 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 493 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 494 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 495 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 496 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 497 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 498 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 499 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 500 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 501 >; 502 }; 503 504 pinctrl_flexcan2: flexcan2grp { 505 fsl,pins = < 506 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 507 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 508 >; 509 }; 510 511 pinctrl_flexcan2_reg: flexcan2reggrp { 512 fsl,pins = < 513 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ 514 >; 515 }; 516 517 518 pinctrl_hog: hoggrp { 519 fsl,pins = < 520 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 521 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ 522 >; 523 }; 524 525 pinctrl_i2c1: i2c1grp { 526 fsl,pins = < 527 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 528 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f 529 >; 530 }; 531 532 pinctrl_i2c2: i2c2grp { 533 fsl,pins = < 534 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f 535 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f 536 >; 537 }; 538 539 pinctrl_i2c3: i2c3grp { 540 fsl,pins = < 541 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f 542 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f 543 >; 544 }; 545 546 pinctrl_i2c4: i2c4grp { 547 fsl,pins = < 548 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f 549 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f 550 >; 551 }; 552 553 pinctrl_lcdif: lcdifgrp { 554 fsl,pins = < 555 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 556 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 557 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 558 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 559 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 560 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 561 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 562 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 563 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 564 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 565 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 566 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 567 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 568 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 569 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 570 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 571 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 572 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 573 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 574 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 575 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 576 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 577 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 578 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 579 MX7D_PAD_LCD_CLK__LCD_CLK 0x79 580 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 581 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 582 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 583 MX7D_PAD_LCD_RESET__LCD_RESET 0x79 584 >; 585 }; 586 587 pinctrl_spi4: spi4grp { 588 fsl,pins = < 589 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 590 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 591 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 592 >; 593 }; 594 595 pinctrl_tsc2046_pendown: tsc2046_pendown { 596 fsl,pins = < 597 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 598 >; 599 }; 600 601 pinctrl_uart1: uart1grp { 602 fsl,pins = < 603 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 604 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 605 >; 606 }; 607 608 pinctrl_uart5: uart5grp { 609 fsl,pins = < 610 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 611 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 612 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 613 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 614 >; 615 }; 616 617 pinctrl_uart6: uart6grp { 618 fsl,pins = < 619 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 620 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 621 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 622 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 623 >; 624 }; 625 626 pinctrl_usdhc1: usdhc1grp { 627 fsl,pins = < 628 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 629 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 630 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 631 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 632 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 633 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 634 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ 635 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ 636 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ 637 >; 638 }; 639 640 pinctrl_usdhc2: usdhc2grp { 641 fsl,pins = < 642 MX7D_PAD_SD2_CMD__SD2_CMD 0x59 643 MX7D_PAD_SD2_CLK__SD2_CLK 0x19 644 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 645 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 646 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 647 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 648 >; 649 }; 650 651 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { 652 fsl,pins = < 653 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a 654 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a 655 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a 656 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a 657 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a 658 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a 659 >; 660 }; 661 662 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { 663 fsl,pins = < 664 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b 665 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b 666 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b 667 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b 668 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b 669 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b 670 >; 671 }; 672 673 674 pinctrl_usdhc3: usdhc3grp { 675 fsl,pins = < 676 MX7D_PAD_SD3_CMD__SD3_CMD 0x59 677 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 678 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 679 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 680 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 681 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 682 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 683 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 684 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 685 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 686 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 687 >; 688 }; 689 690 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { 691 fsl,pins = < 692 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a 693 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a 694 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a 695 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a 696 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a 697 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a 698 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a 699 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a 700 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a 701 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a 702 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a 703 >; 704 }; 705 706 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { 707 fsl,pins = < 708 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b 709 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b 710 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b 711 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b 712 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b 713 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b 714 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b 715 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b 716 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b 717 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b 718 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b 719 >; 720 }; 721 }; 722}; 723 724&iomuxc_lpsr { 725 pinctrl_wdog: wdoggrp { 726 fsl,pins = < 727 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 728 >; 729 }; 730 731 pinctrl_backlight: backlightgrp { 732 fsl,pins = < 733 MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x110b0 734 >; 735 }; 736}; 737