1/* 2 * Copyright 2014 Texas Instruments, Inc. 3 * 4 * Keystone 2 Lamarr SoC specific device tree 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#include <dt-bindings/reset/ti-syscon.h> 12 13/ { 14 compatible = "ti,k2l", "ti,keystone"; 15 model = "Texas Instruments Keystone 2 Lamarr SoC"; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 interrupt-parent = <&gic>; 22 23 cpu@0 { 24 compatible = "arm,cortex-a15"; 25 device_type = "cpu"; 26 reg = <0>; 27 }; 28 29 cpu@1 { 30 compatible = "arm,cortex-a15"; 31 device_type = "cpu"; 32 reg = <1>; 33 }; 34 }; 35 36 aliases { 37 rproc0 = &dsp0; 38 rproc1 = &dsp1; 39 rproc2 = &dsp2; 40 rproc3 = &dsp3; 41 }; 42 43 soc { 44 /include/ "keystone-k2l-clocks.dtsi" 45 46 uart2: serial@02348400 { 47 compatible = "ti,da830-uart", "ns16550a"; 48 current-speed = <115200>; 49 reg-shift = <2>; 50 reg-io-width = <4>; 51 reg = <0x02348400 0x100>; 52 clocks = <&clkuart2>; 53 interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>; 54 }; 55 56 uart3: serial@02348800 { 57 compatible = "ti,da830-uart", "ns16550a"; 58 current-speed = <115200>; 59 reg-shift = <2>; 60 reg-io-width = <4>; 61 reg = <0x02348800 0x100>; 62 clocks = <&clkuart3>; 63 interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>; 64 }; 65 66 k2l_pmx: pinmux@02620690 { 67 compatible = "pinctrl-single"; 68 reg = <0x02620690 0xc>; 69 #address-cells = <1>; 70 #size-cells = <0>; 71 #pinctrl-cells = <2>; 72 pinctrl-single,bit-per-mux; 73 pinctrl-single,register-width = <32>; 74 pinctrl-single,function-mask = <0x1>; 75 status = "disabled"; 76 77 uart3_emifa_pins: pinmux_uart3_emifa_pins { 78 pinctrl-single,bits = < 79 /* UART3_EMIFA_SEL */ 80 0x0 0x0 0xc0 81 >; 82 }; 83 84 uart2_emifa_pins: pinmux_uart2_emifa_pins { 85 pinctrl-single,bits = < 86 /* UART2_EMIFA_SEL */ 87 0x0 0x0 0x30 88 >; 89 }; 90 91 uart01_spi2_pins: pinmux_uart01_spi2_pins { 92 pinctrl-single,bits = < 93 /* UART01_SPI2_SEL */ 94 0x0 0x0 0x4 95 >; 96 }; 97 98 dfesync_rp1_pins: pinmux_dfesync_rp1_pins{ 99 pinctrl-single,bits = < 100 /* DFESYNC_RP1_SEL */ 101 0x0 0x0 0x2 102 >; 103 }; 104 105 avsif_pins: pinmux_avsif_pins { 106 pinctrl-single,bits = < 107 /* AVSIF_SEL */ 108 0x0 0x0 0x1 109 >; 110 }; 111 112 gpio_emu_pins: pinmux_gpio_emu_pins { 113 pinctrl-single,bits = < 114 /* 115 * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33 116 * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32 117 * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31 118 * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30 119 * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29 120 * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28 121 * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27 122 * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26 123 * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25 124 * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24 125 * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23 126 * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22 127 * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21 128 * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20 129 * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19 130 */ 131 0x4 0x0000 0xFFFE0000 132 >; 133 }; 134 135 gpio_timio_pins: pinmux_gpio_timio_pins { 136 pinctrl-single,bits = < 137 /* 138 * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7 139 * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6 140 * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5 141 * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4 142 * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3 143 * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2 144 * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7 145 * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6 146 * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5 147 * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4 148 * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3 149 * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2 150 */ 151 0x4 0x0 0xFFF0 152 >; 153 }; 154 155 gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins { 156 pinctrl-single,bits = < 157 /* 158 * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4 159 * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3 160 * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2 161 * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1 162 */ 163 0x4 0x0 0xF 164 >; 165 }; 166 167 gpio_dfeio_pins: pinmux_gpio_dfeio_pins { 168 pinctrl-single,bits = < 169 /* 170 * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63 171 * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62 172 * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61 173 * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60 174 * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59 175 * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58 176 * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57 177 * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56 178 * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55 179 * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54 180 * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53 181 * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52 182 * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51 183 * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50 184 * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49 185 * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48 186 */ 187 0x8 0x0 0xFFFF0000 188 >; 189 }; 190 191 gpio_emifa_pins: pinmux_gpio_emifa_pins { 192 pinctrl-single,bits = < 193 /* 194 * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47 195 * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46 196 * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45 197 * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44 198 * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43 199 * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42 200 * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41 201 * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40 202 * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39 203 * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38 204 * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37 205 * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36 206 * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35 207 * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34 208 * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33 209 * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32 210 */ 211 0x8 0x0 0xFFFF 212 >; 213 }; 214 }; 215 216 msm_ram: msmram@0c000000 { 217 compatible = "mmio-sram"; 218 reg = <0x0c000000 0x200000>; 219 ranges = <0x0 0x0c000000 0x200000>; 220 #address-cells = <1>; 221 #size-cells = <1>; 222 223 sram-bm@1f8000 { 224 reg = <0x001f8000 0x8000>; 225 }; 226 }; 227 228 psc: power-sleep-controller@02350000 { 229 pscrst: reset-controller { 230 compatible = "ti,k2l-pscrst", "ti,syscon-reset"; 231 #reset-cells = <1>; 232 233 ti,reset-bits = < 234 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ 235 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */ 236 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */ 237 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */ 238 >; 239 }; 240 }; 241 242 osr: sram@70000000 { 243 compatible = "mmio-sram"; 244 reg = <0x70000000 0x10000>; 245 #address-cells = <1>; 246 #size-cells = <1>; 247 clocks = <&clkosr>; 248 }; 249 250 dspgpio0: keystone_dsp_gpio@02620240 { 251 compatible = "ti,keystone-dsp-gpio"; 252 gpio-controller; 253 #gpio-cells = <2>; 254 gpio,syscon-dev = <&devctrl 0x240>; 255 }; 256 257 dspgpio1: keystone_dsp_gpio@2620244 { 258 compatible = "ti,keystone-dsp-gpio"; 259 gpio-controller; 260 #gpio-cells = <2>; 261 gpio,syscon-dev = <&devctrl 0x244>; 262 }; 263 264 dspgpio2: keystone_dsp_gpio@2620248 { 265 compatible = "ti,keystone-dsp-gpio"; 266 gpio-controller; 267 #gpio-cells = <2>; 268 gpio,syscon-dev = <&devctrl 0x248>; 269 }; 270 271 dspgpio3: keystone_dsp_gpio@262024c { 272 compatible = "ti,keystone-dsp-gpio"; 273 gpio-controller; 274 #gpio-cells = <2>; 275 gpio,syscon-dev = <&devctrl 0x24c>; 276 }; 277 278 dsp0: dsp@10800000 { 279 compatible = "ti,k2l-dsp"; 280 reg = <0x10800000 0x00100000>, 281 <0x10e00000 0x00008000>, 282 <0x10f00000 0x00008000>; 283 reg-names = "l2sram", "l1pram", "l1dram"; 284 clocks = <&clkgem0>; 285 ti,syscon-dev = <&devctrl 0x844>; 286 resets = <&pscrst 0>; 287 interrupt-parent = <&kirq0>; 288 interrupts = <0 8>; 289 interrupt-names = "vring", "exception"; 290 kick-gpios = <&dspgpio0 27 0>; 291 status = "disabled"; 292 }; 293 294 dsp1: dsp@11800000 { 295 compatible = "ti,k2l-dsp"; 296 reg = <0x11800000 0x00100000>, 297 <0x11e00000 0x00008000>, 298 <0x11f00000 0x00008000>; 299 reg-names = "l2sram", "l1pram", "l1dram"; 300 clocks = <&clkgem1>; 301 ti,syscon-dev = <&devctrl 0x848>; 302 resets = <&pscrst 1>; 303 interrupt-parent = <&kirq0>; 304 interrupts = <1 9>; 305 interrupt-names = "vring", "exception"; 306 kick-gpios = <&dspgpio1 27 0>; 307 status = "disabled"; 308 }; 309 310 dsp2: dsp@12800000 { 311 compatible = "ti,k2l-dsp"; 312 reg = <0x12800000 0x00100000>, 313 <0x12e00000 0x00008000>, 314 <0x12f00000 0x00008000>; 315 reg-names = "l2sram", "l1pram", "l1dram"; 316 clocks = <&clkgem2>; 317 ti,syscon-dev = <&devctrl 0x84c>; 318 resets = <&pscrst 2>; 319 interrupt-parent = <&kirq0>; 320 interrupts = <2 10>; 321 interrupt-names = "vring", "exception"; 322 kick-gpios = <&dspgpio2 27 0>; 323 status = "disabled"; 324 }; 325 326 dsp3: dsp@13800000 { 327 compatible = "ti,k2l-dsp"; 328 reg = <0x13800000 0x00100000>, 329 <0x13e00000 0x00008000>, 330 <0x13f00000 0x00008000>; 331 reg-names = "l2sram", "l1pram", "l1dram"; 332 clocks = <&clkgem3>; 333 ti,syscon-dev = <&devctrl 0x850>; 334 resets = <&pscrst 3>; 335 interrupt-parent = <&kirq0>; 336 interrupts = <3 11>; 337 interrupt-names = "vring", "exception"; 338 kick-gpios = <&dspgpio3 27 0>; 339 status = "disabled"; 340 }; 341 342 mdio: mdio@26200f00 { 343 compatible = "ti,keystone_mdio", "ti,davinci_mdio"; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 reg = <0x26200f00 0x100>; 347 status = "disabled"; 348 clocks = <&clkcpgmac>; 349 clock-names = "fck"; 350 bus_freq = <2500000>; 351 }; 352 /include/ "keystone-k2l-netcp.dtsi" 353 }; 354}; 355 356&spi0 { 357 ti,davinci-spi-num-cs = <5>; 358}; 359 360&spi1 { 361 ti,davinci-spi-num-cs = <3>; 362}; 363 364&spi2 { 365 ti,davinci-spi-num-cs = <5>; 366 /* Pin muxed. Enabled and configured by Bootloader */ 367 status = "disabled"; 368}; 369