1/* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include "skeleton64.dtsi" 49#include <dt-bindings/interrupt-controller/arm-gic.h> 50#include <dt-bindings/thermal/thermal.h> 51 52/ { 53 compatible = "fsl,ls1021a"; 54 interrupt-parent = <&gic>; 55 56 aliases { 57 crypto = &crypto; 58 ethernet0 = &enet0; 59 ethernet1 = &enet1; 60 ethernet2 = &enet2; 61 serial0 = &lpuart0; 62 serial1 = &lpuart1; 63 serial2 = &lpuart2; 64 serial3 = &lpuart3; 65 serial4 = &lpuart4; 66 serial5 = &lpuart5; 67 sysclk = &sysclk; 68 }; 69 70 cpus { 71 #address-cells = <1>; 72 #size-cells = <0>; 73 74 cpu0: cpu@f00 { 75 compatible = "arm,cortex-a7"; 76 device_type = "cpu"; 77 reg = <0xf00>; 78 clocks = <&clockgen 1 0>; 79 #cooling-cells = <2>; 80 }; 81 82 cpu1: cpu@f01 { 83 compatible = "arm,cortex-a7"; 84 device_type = "cpu"; 85 reg = <0xf01>; 86 clocks = <&clockgen 1 0>; 87 #cooling-cells = <2>; 88 }; 89 }; 90 91 sysclk: sysclk { 92 compatible = "fixed-clock"; 93 #clock-cells = <0>; 94 clock-frequency = <100000000>; 95 clock-output-names = "sysclk"; 96 }; 97 98 timer { 99 compatible = "arm,armv7-timer"; 100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 104 }; 105 106 pmu { 107 compatible = "arm,cortex-a7-pmu"; 108 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 110 }; 111 112 soc { 113 compatible = "simple-bus"; 114 #address-cells = <2>; 115 #size-cells = <2>; 116 device_type = "soc"; 117 interrupt-parent = <&gic>; 118 ranges; 119 120 gic: interrupt-controller@1400000 { 121 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 122 #interrupt-cells = <3>; 123 interrupt-controller; 124 reg = <0x0 0x1401000 0x0 0x1000>, 125 <0x0 0x1402000 0x0 0x2000>, 126 <0x0 0x1404000 0x0 0x2000>, 127 <0x0 0x1406000 0x0 0x2000>; 128 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 129 130 }; 131 132 msi1: msi-controller@1570e00 { 133 compatible = "fsl,ls1021a-msi"; 134 reg = <0x0 0x1570e00 0x0 0x8>; 135 msi-controller; 136 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 137 }; 138 139 msi2: msi-controller@1570e08 { 140 compatible = "fsl,ls1021a-msi"; 141 reg = <0x0 0x1570e08 0x0 0x8>; 142 msi-controller; 143 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 144 }; 145 146 ifc: ifc@1530000 { 147 compatible = "fsl,ifc", "simple-bus"; 148 reg = <0x0 0x1530000 0x0 0x10000>; 149 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 150 }; 151 152 dcfg: dcfg@1ee0000 { 153 compatible = "fsl,ls1021a-dcfg", "syscon"; 154 reg = <0x0 0x1ee0000 0x0 0x10000>; 155 big-endian; 156 }; 157 158 esdhc: esdhc@1560000 { 159 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc"; 160 reg = <0x0 0x1560000 0x0 0x10000>; 161 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 162 clock-frequency = <0>; 163 voltage-ranges = <1800 1800 3300 3300>; 164 sdhci,auto-cmd12; 165 big-endian; 166 bus-width = <4>; 167 status = "disabled"; 168 }; 169 170 sata: sata@3200000 { 171 compatible = "fsl,ls1021a-ahci"; 172 reg = <0x0 0x3200000 0x0 0x10000>, 173 <0x0 0x20220520 0x0 0x4>; 174 reg-names = "ahci", "sata-ecc"; 175 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&clockgen 4 1>; 177 dma-coherent; 178 status = "disabled"; 179 }; 180 181 scfg: scfg@1570000 { 182 compatible = "fsl,ls1021a-scfg", "syscon"; 183 reg = <0x0 0x1570000 0x0 0x10000>; 184 big-endian; 185 }; 186 187 crypto: crypto@1700000 { 188 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 189 fsl,sec-era = <7>; 190 #address-cells = <1>; 191 #size-cells = <1>; 192 reg = <0x0 0x1700000 0x0 0x100000>; 193 ranges = <0x0 0x0 0x1700000 0x100000>; 194 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 195 196 sec_jr0: jr@10000 { 197 compatible = "fsl,sec-v5.0-job-ring", 198 "fsl,sec-v4.0-job-ring"; 199 reg = <0x10000 0x10000>; 200 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 201 }; 202 203 sec_jr1: jr@20000 { 204 compatible = "fsl,sec-v5.0-job-ring", 205 "fsl,sec-v4.0-job-ring"; 206 reg = <0x20000 0x10000>; 207 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 208 }; 209 210 sec_jr2: jr@30000 { 211 compatible = "fsl,sec-v5.0-job-ring", 212 "fsl,sec-v4.0-job-ring"; 213 reg = <0x30000 0x10000>; 214 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 215 }; 216 217 sec_jr3: jr@40000 { 218 compatible = "fsl,sec-v5.0-job-ring", 219 "fsl,sec-v4.0-job-ring"; 220 reg = <0x40000 0x10000>; 221 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 222 }; 223 224 }; 225 226 clockgen: clocking@1ee1000 { 227 compatible = "fsl,ls1021a-clockgen"; 228 reg = <0x0 0x1ee1000 0x0 0x1000>; 229 #clock-cells = <2>; 230 clocks = <&sysclk>; 231 }; 232 233 tmu: tmu@1f00000 { 234 compatible = "fsl,qoriq-tmu"; 235 reg = <0x0 0x1f00000 0x0 0x10000>; 236 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 237 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>; 238 fsl,tmu-calibration = <0x00000000 0x0000000f 239 0x00000001 0x00000017 240 0x00000002 0x0000001e 241 0x00000003 0x00000026 242 0x00000004 0x0000002e 243 0x00000005 0x00000035 244 0x00000006 0x0000003d 245 0x00000007 0x00000044 246 0x00000008 0x0000004c 247 0x00000009 0x00000053 248 0x0000000a 0x0000005b 249 0x0000000b 0x00000064 250 251 0x00010000 0x00000011 252 0x00010001 0x0000001c 253 0x00010002 0x00000024 254 0x00010003 0x0000002b 255 0x00010004 0x00000034 256 0x00010005 0x00000039 257 0x00010006 0x00000042 258 0x00010007 0x0000004c 259 0x00010008 0x00000051 260 0x00010009 0x0000005a 261 0x0001000a 0x00000063 262 263 0x00020000 0x00000013 264 0x00020001 0x00000019 265 0x00020002 0x00000024 266 0x00020003 0x0000002c 267 0x00020004 0x00000035 268 0x00020005 0x0000003d 269 0x00020006 0x00000046 270 0x00020007 0x00000050 271 0x00020008 0x00000059 272 273 0x00030000 0x00000002 274 0x00030001 0x0000000d 275 0x00030002 0x00000019 276 0x00030003 0x00000024>; 277 #thermal-sensor-cells = <1>; 278 }; 279 280 thermal-zones { 281 cpu_thermal: cpu-thermal { 282 polling-delay-passive = <1000>; 283 polling-delay = <5000>; 284 285 thermal-sensors = <&tmu 0>; 286 287 trips { 288 cpu_alert: cpu-alert { 289 temperature = <85000>; 290 hysteresis = <2000>; 291 type = "passive"; 292 }; 293 cpu_crit: cpu-crit { 294 temperature = <95000>; 295 hysteresis = <2000>; 296 type = "critical"; 297 }; 298 }; 299 300 cooling-maps { 301 map0 { 302 trip = <&cpu_alert>; 303 cooling-device = 304 <&cpu0 THERMAL_NO_LIMIT 305 THERMAL_NO_LIMIT>; 306 }; 307 }; 308 }; 309 }; 310 311 dspi0: dspi@2100000 { 312 compatible = "fsl,ls1021a-v1.0-dspi"; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 reg = <0x0 0x2100000 0x0 0x10000>; 316 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 317 clock-names = "dspi"; 318 clocks = <&clockgen 4 1>; 319 spi-num-chipselects = <6>; 320 big-endian; 321 status = "disabled"; 322 }; 323 324 dspi1: dspi@2110000 { 325 compatible = "fsl,ls1021a-v1.0-dspi"; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 reg = <0x0 0x2110000 0x0 0x10000>; 329 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 330 clock-names = "dspi"; 331 clocks = <&clockgen 4 1>; 332 spi-num-chipselects = <6>; 333 big-endian; 334 status = "disabled"; 335 }; 336 337 i2c0: i2c@2180000 { 338 compatible = "fsl,vf610-i2c"; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 reg = <0x0 0x2180000 0x0 0x10000>; 342 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 343 clock-names = "i2c"; 344 clocks = <&clockgen 4 1>; 345 status = "disabled"; 346 }; 347 348 i2c1: i2c@2190000 { 349 compatible = "fsl,vf610-i2c"; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 reg = <0x0 0x2190000 0x0 0x10000>; 353 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 354 clock-names = "i2c"; 355 clocks = <&clockgen 4 1>; 356 status = "disabled"; 357 }; 358 359 i2c2: i2c@21a0000 { 360 compatible = "fsl,vf610-i2c"; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 reg = <0x0 0x21a0000 0x0 0x10000>; 364 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 365 clock-names = "i2c"; 366 clocks = <&clockgen 4 1>; 367 status = "disabled"; 368 }; 369 370 uart0: serial@21c0500 { 371 compatible = "fsl,16550-FIFO64", "ns16550a"; 372 reg = <0x0 0x21c0500 0x0 0x100>; 373 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 374 clock-frequency = <0>; 375 fifo-size = <15>; 376 status = "disabled"; 377 }; 378 379 uart1: serial@21c0600 { 380 compatible = "fsl,16550-FIFO64", "ns16550a"; 381 reg = <0x0 0x21c0600 0x0 0x100>; 382 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 383 clock-frequency = <0>; 384 fifo-size = <15>; 385 status = "disabled"; 386 }; 387 388 uart2: serial@21d0500 { 389 compatible = "fsl,16550-FIFO64", "ns16550a"; 390 reg = <0x0 0x21d0500 0x0 0x100>; 391 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 392 clock-frequency = <0>; 393 fifo-size = <15>; 394 status = "disabled"; 395 }; 396 397 uart3: serial@21d0600 { 398 compatible = "fsl,16550-FIFO64", "ns16550a"; 399 reg = <0x0 0x21d0600 0x0 0x100>; 400 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 401 clock-frequency = <0>; 402 fifo-size = <15>; 403 status = "disabled"; 404 }; 405 406 gpio0: gpio@2300000 { 407 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 408 reg = <0x0 0x2300000 0x0 0x10000>; 409 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 410 gpio-controller; 411 #gpio-cells = <2>; 412 interrupt-controller; 413 #interrupt-cells = <2>; 414 }; 415 416 gpio1: gpio@2310000 { 417 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 418 reg = <0x0 0x2310000 0x0 0x10000>; 419 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 420 gpio-controller; 421 #gpio-cells = <2>; 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 }; 425 426 gpio2: gpio@2320000 { 427 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 428 reg = <0x0 0x2320000 0x0 0x10000>; 429 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 430 gpio-controller; 431 #gpio-cells = <2>; 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 }; 435 436 gpio3: gpio@2330000 { 437 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 438 reg = <0x0 0x2330000 0x0 0x10000>; 439 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 440 gpio-controller; 441 #gpio-cells = <2>; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 }; 445 446 lpuart0: serial@2950000 { 447 compatible = "fsl,ls1021a-lpuart"; 448 reg = <0x0 0x2950000 0x0 0x1000>; 449 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&sysclk>; 451 clock-names = "ipg"; 452 status = "disabled"; 453 }; 454 455 lpuart1: serial@2960000 { 456 compatible = "fsl,ls1021a-lpuart"; 457 reg = <0x0 0x2960000 0x0 0x1000>; 458 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&clockgen 4 1>; 460 clock-names = "ipg"; 461 status = "disabled"; 462 }; 463 464 lpuart2: serial@2970000 { 465 compatible = "fsl,ls1021a-lpuart"; 466 reg = <0x0 0x2970000 0x0 0x1000>; 467 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&clockgen 4 1>; 469 clock-names = "ipg"; 470 status = "disabled"; 471 }; 472 473 lpuart3: serial@2980000 { 474 compatible = "fsl,ls1021a-lpuart"; 475 reg = <0x0 0x2980000 0x0 0x1000>; 476 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&clockgen 4 1>; 478 clock-names = "ipg"; 479 status = "disabled"; 480 }; 481 482 lpuart4: serial@2990000 { 483 compatible = "fsl,ls1021a-lpuart"; 484 reg = <0x0 0x2990000 0x0 0x1000>; 485 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&clockgen 4 1>; 487 clock-names = "ipg"; 488 status = "disabled"; 489 }; 490 491 lpuart5: serial@29a0000 { 492 compatible = "fsl,ls1021a-lpuart"; 493 reg = <0x0 0x29a0000 0x0 0x1000>; 494 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&clockgen 4 1>; 496 clock-names = "ipg"; 497 status = "disabled"; 498 }; 499 500 wdog0: watchdog@2ad0000 { 501 compatible = "fsl,imx21-wdt"; 502 reg = <0x0 0x2ad0000 0x0 0x10000>; 503 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&clockgen 4 1>; 505 clock-names = "wdog-en"; 506 big-endian; 507 }; 508 509 sai1: sai@2b50000 { 510 #sound-dai-cells = <0>; 511 compatible = "fsl,vf610-sai"; 512 reg = <0x0 0x2b50000 0x0 0x10000>; 513 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 515 <&clockgen 4 1>, <&clockgen 4 1>; 516 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 517 dma-names = "tx", "rx"; 518 dmas = <&edma0 1 47>, 519 <&edma0 1 46>; 520 status = "disabled"; 521 }; 522 523 sai2: sai@2b60000 { 524 #sound-dai-cells = <0>; 525 compatible = "fsl,vf610-sai"; 526 reg = <0x0 0x2b60000 0x0 0x10000>; 527 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 529 <&clockgen 4 1>, <&clockgen 4 1>; 530 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 531 dma-names = "tx", "rx"; 532 dmas = <&edma0 1 45>, 533 <&edma0 1 44>; 534 status = "disabled"; 535 }; 536 537 edma0: edma@2c00000 { 538 #dma-cells = <2>; 539 compatible = "fsl,vf610-edma"; 540 reg = <0x0 0x2c00000 0x0 0x10000>, 541 <0x0 0x2c10000 0x0 0x10000>, 542 <0x0 0x2c20000 0x0 0x10000>; 543 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 545 interrupt-names = "edma-tx", "edma-err"; 546 dma-channels = <32>; 547 big-endian; 548 clock-names = "dmamux0", "dmamux1"; 549 clocks = <&clockgen 4 1>, 550 <&clockgen 4 1>; 551 }; 552 553 dcu: dcu@2ce0000 { 554 compatible = "fsl,ls1021a-dcu"; 555 reg = <0x0 0x2ce0000 0x0 0x10000>; 556 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&clockgen 4 0>, 558 <&clockgen 4 0>; 559 clock-names = "dcu", "pix"; 560 big-endian; 561 status = "disabled"; 562 }; 563 564 mdio0: mdio@2d24000 { 565 compatible = "gianfar"; 566 device_type = "mdio"; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 reg = <0x0 0x2d24000 0x0 0x4000>; 570 }; 571 572 mdio1: mdio@2d64000 { 573 compatible = "gianfar"; 574 device_type = "mdio"; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 reg = <0x0 0x2d64000 0x0 0x4000>, 578 <0x0 0x2d50030 0x0 0x4>; 579 }; 580 581 ptp_clock@2d10e00 { 582 compatible = "fsl,etsec-ptp"; 583 reg = <0x0 0x2d10e00 0x0 0xb0>; 584 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 585 fsl,tclk-period = <5>; 586 fsl,tmr-prsc = <2>; 587 fsl,tmr-add = <0xaaaaaaab>; 588 fsl,tmr-fiper1 = <999999990>; 589 fsl,tmr-fiper2 = <99990>; 590 fsl,max-adj = <499999999>; 591 }; 592 593 enet0: ethernet@2d10000 { 594 compatible = "fsl,etsec2"; 595 device_type = "network"; 596 #address-cells = <2>; 597 #size-cells = <2>; 598 interrupt-parent = <&gic>; 599 model = "eTSEC"; 600 fsl,magic-packet; 601 ranges; 602 dma-coherent; 603 604 queue-group@2d10000 { 605 #address-cells = <2>; 606 #size-cells = <2>; 607 reg = <0x0 0x2d10000 0x0 0x1000>; 608 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 611 }; 612 613 queue-group@2d14000 { 614 #address-cells = <2>; 615 #size-cells = <2>; 616 reg = <0x0 0x2d14000 0x0 0x1000>; 617 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 620 }; 621 }; 622 623 enet1: ethernet@2d50000 { 624 compatible = "fsl,etsec2"; 625 device_type = "network"; 626 #address-cells = <2>; 627 #size-cells = <2>; 628 interrupt-parent = <&gic>; 629 model = "eTSEC"; 630 ranges; 631 dma-coherent; 632 633 queue-group@2d50000 { 634 #address-cells = <2>; 635 #size-cells = <2>; 636 reg = <0x0 0x2d50000 0x0 0x1000>; 637 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 640 }; 641 642 queue-group@2d54000 { 643 #address-cells = <2>; 644 #size-cells = <2>; 645 reg = <0x0 0x2d54000 0x0 0x1000>; 646 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 649 }; 650 }; 651 652 enet2: ethernet@2d90000 { 653 compatible = "fsl,etsec2"; 654 device_type = "network"; 655 #address-cells = <2>; 656 #size-cells = <2>; 657 interrupt-parent = <&gic>; 658 model = "eTSEC"; 659 ranges; 660 dma-coherent; 661 662 queue-group@2d90000 { 663 #address-cells = <2>; 664 #size-cells = <2>; 665 reg = <0x0 0x2d90000 0x0 0x1000>; 666 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 669 }; 670 671 queue-group@2d94000 { 672 #address-cells = <2>; 673 #size-cells = <2>; 674 reg = <0x0 0x2d94000 0x0 0x1000>; 675 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 678 }; 679 }; 680 681 usb@8600000 { 682 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 683 reg = <0x0 0x8600000 0x0 0x1000>; 684 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 685 dr_mode = "host"; 686 phy_type = "ulpi"; 687 }; 688 689 usb3@3100000 { 690 compatible = "snps,dwc3"; 691 reg = <0x0 0x3100000 0x0 0x10000>; 692 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 693 dr_mode = "host"; 694 snps,quirk-frame-length-adjustment = <0x20>; 695 snps,dis_rxdet_inp3_quirk; 696 }; 697 698 pcie@3400000 { 699 compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; 700 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 701 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 702 reg-names = "regs", "config"; 703 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 704 fsl,pcie-scfg = <&scfg 0>; 705 #address-cells = <3>; 706 #size-cells = <2>; 707 device_type = "pci"; 708 num-lanes = <4>; 709 bus-range = <0x0 0xff>; 710 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 711 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 712 msi-parent = <&msi1>, <&msi2>; 713 #interrupt-cells = <1>; 714 interrupt-map-mask = <0 0 0 7>; 715 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 716 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 717 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 718 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 719 }; 720 721 pcie@3500000 { 722 compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; 723 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ 724 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 725 reg-names = "regs", "config"; 726 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 727 fsl,pcie-scfg = <&scfg 1>; 728 #address-cells = <3>; 729 #size-cells = <2>; 730 device_type = "pci"; 731 num-lanes = <4>; 732 bus-range = <0x0 0xff>; 733 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 734 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 735 msi-parent = <&msi1>, <&msi2>; 736 #interrupt-cells = <1>; 737 interrupt-map-mask = <0 0 0 7>; 738 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 739 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 740 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 741 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 742 }; 743 }; 744}; 745