1/* 2 * Copyright (c) 2015 MediaTek Inc. 3 * Author: Erin Lo <erin.lo@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15/dts-v1/; 16#include "mt2701.dtsi" 17 18/ { 19 model = "MediaTek MT2701 evaluation board"; 20 compatible = "mediatek,mt2701-evb", "mediatek,mt2701"; 21 22 memory { 23 reg = <0 0x80000000 0 0x40000000>; 24 }; 25 26 sound:sound { 27 compatible = "mediatek,mt2701-cs42448-machine"; 28 mediatek,platform = <&afe>; 29 /* CS42448 Machine name */ 30 audio-routing = 31 "Line Out Jack", "AOUT1L", 32 "Line Out Jack", "AOUT1R", 33 "Line Out Jack", "AOUT2L", 34 "Line Out Jack", "AOUT2R", 35 "Line Out Jack", "AOUT3L", 36 "Line Out Jack", "AOUT3R", 37 "Line Out Jack", "AOUT4L", 38 "Line Out Jack", "AOUT4R", 39 "AIN1L", "AMIC", 40 "AIN1R", "AMIC", 41 "AIN2L", "Tuner In", 42 "AIN2R", "Tuner In", 43 "AIN3L", "Satellite Tuner In", 44 "AIN3R", "Satellite Tuner In", 45 "AIN3L", "AUX In", 46 "AIN3R", "AUX In"; 47 mediatek,audio-codec = <&cs42448>; 48 mediatek,audio-codec-bt-mrg = <&bt_sco_codec>; 49 pinctrl-names = "default"; 50 pinctrl-0 = <&aud_pins_default>; 51 i2s1-in-sel-gpio1 = <&pio 53 0>; 52 i2s1-in-sel-gpio2 = <&pio 54 0>; 53 status = "okay"; 54 }; 55 56 bt_sco_codec:bt_sco_codec { 57 compatible = "linux,bt-sco"; 58 }; 59}; 60 61&auxadc { 62 status = "okay"; 63}; 64 65&i2c0 { 66 pinctrl-names = "default"; 67 pinctrl-0 = <&i2c0_pins_a>; 68 status = "okay"; 69}; 70 71&i2c1 { 72 pinctrl-names = "default"; 73 pinctrl-0 = <&i2c1_pins_a>; 74 status = "okay"; 75}; 76 77&i2c2 { 78 pinctrl-names = "default"; 79 pinctrl-0 = <&i2c2_pins_a>; 80 status = "okay"; 81 cs42448: cs42448@48 { 82 compatible = "cirrus,cs42448"; 83 reg = <0x48>; 84 clocks = <&topckgen CLK_TOP_AUD_I2S1_MCLK>; 85 clock-names = "mclk"; 86 }; 87}; 88 89&pio { 90 i2c0_pins_a: i2c0@0 { 91 pins1 { 92 pinmux = <MT2701_PIN_75_SDA0__FUNC_SDA0>, 93 <MT2701_PIN_76_SCL0__FUNC_SCL0>; 94 bias-disable; 95 }; 96 }; 97 98 i2c1_pins_a: i2c1@0 { 99 pins1 { 100 pinmux = <MT2701_PIN_57_SDA1__FUNC_SDA1>, 101 <MT2701_PIN_58_SCL1__FUNC_SCL1>; 102 bias-disable; 103 }; 104 }; 105 106 i2c2_pins_a: i2c2@0 { 107 pins1 { 108 pinmux = <MT2701_PIN_77_SDA2__FUNC_SDA2>, 109 <MT2701_PIN_78_SCL2__FUNC_SCL2>; 110 bias-disable; 111 }; 112 }; 113 114 spi_pins_a: spi0@0 { 115 pins_spi { 116 pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>, 117 <MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK>, 118 <MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI>, 119 <MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO>; 120 bias-disable; 121 }; 122 }; 123 124 aud_pins_default: audiodefault { 125 pins_cmd_dat { 126 pinmux = <MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA>, 127 <MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN>, 128 <MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK>, 129 <MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK>, 130 <MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK>, 131 <MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA>, 132 <MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN>, 133 <MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK>, 134 <MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK>, 135 <MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK>, 136 <MT2701_PIN_203_PWM0__FUNC_I2S2_DATA>, 137 <MT2701_PIN_204_PWM1__FUNC_I2S3_DATA>, 138 <MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53>, 139 <MT2701_PIN_54_SPI0_CK__FUNC_GPIO54>, 140 <MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK>, 141 <MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC>, 142 <MT2701_PIN_20_PCM_RX__FUNC_MRG_TX>, 143 <MT2701_PIN_21_PCM_TX__FUNC_MRG_RX>; 144 drive-strength = <MTK_DRIVE_12mA>; 145 bias-pull-down; 146 }; 147 }; 148 149 spi_pins_b: spi1@0 { 150 pins_spi { 151 pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>, 152 <MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI>, 153 <MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO>, 154 <MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK>; 155 bias-disable; 156 }; 157 }; 158 159 spi_pins_c: spi2@0 { 160 pins_spi { 161 pinmux = <MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS>, 162 <MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI>, 163 <MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO>, 164 <MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK>; 165 bias-disable; 166 }; 167 }; 168}; 169 170&spi0 { 171 pinctrl-names = "default"; 172 pinctrl-0 = <&spi_pins_a>; 173 status = "disabled"; 174}; 175 176&spi1 { 177 pinctrl-names = "default"; 178 pinctrl-0 = <&spi_pins_b>; 179 status = "disabled"; 180}; 181 182&spi2 { 183 pinctrl-names = "default"; 184 pinctrl-0 = <&spi_pins_c>; 185 status = "disabled"; 186}; 187 188&nor_flash { 189 pinctrl-names = "default"; 190 pinctrl-0 = <&nor_pins_default>; 191 status = "okay"; 192 flash@0 { 193 compatible = "jedec,spi-nor"; 194 reg = <0>; 195 }; 196}; 197 198&pio { 199 nor_pins_default: nor { 200 pins1 { 201 pinmux = <MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS>, 202 <MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK>, 203 <MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0>, 204 <MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1>, 205 <MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2>, 206 <MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3>; 207 drive-strength = <MTK_DRIVE_4mA>; 208 bias-pull-up; 209 }; 210 }; 211}; 212 213&uart0 { 214 status = "okay"; 215}; 216