1/* 2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8/dts-v1/; 9 10#include "omap36xx.dtsi" 11#include "omap3-evm-common.dtsi" 12 13 14/ { 15 model = "TI OMAP37XX EVM (TMDSEVM3730)"; 16 compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3"; 17 18 memory@80000000 { 19 device_type = "memory"; 20 reg = <0x80000000 0x10000000>; /* 256 MB */ 21 }; 22 23 wl12xx_vmmc: wl12xx_vmmc { 24 pinctrl-names = "default"; 25 pinctrl-0 = <&wl12xx_gpio>; 26 }; 27}; 28 29&dss { 30 pinctrl-names = "default"; 31 pinctrl-0 = < 32 &dss_dpi_pins1 33 &dss_dpi_pins2 34 >; 35}; 36 37&hsusb2_phy { 38 pinctrl-names = "default"; 39 pinctrl-0 = <&ehci_phy_pins>; 40}; 41 42&omap3_pmx_core { 43 pinctrl-names = "default"; 44 pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; 45 46 dss_dpi_pins1: pinmux_dss_dpi_pins2 { 47 pinctrl-single,pins = < 48 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 49 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 50 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 51 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 52 53 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ 54 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ 55 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ 56 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ 57 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ 58 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ 59 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ 60 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ 61 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ 62 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ 63 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ 64 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ 65 66 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ 67 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ 68 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ 69 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ 70 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ 71 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ 72 >; 73 }; 74 75 mmc1_pins: pinmux_mmc1_pins { 76 pinctrl-single,pins = < 77 OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ 78 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ 79 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ 80 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 81 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 82 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ 83 OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ 84 OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ 85 OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ 86 OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ 87 >; 88 }; 89 90 /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ 91 mmc2_pins: pinmux_mmc2_pins { 92 pinctrl-single,pins = < 93 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ 94 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ 95 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ 96 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ 97 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ 98 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ 99 >; 100 }; 101 102 uart3_pins: pinmux_uart3_pins { 103 pinctrl-single,pins = < 104 OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 105 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 106 >; 107 }; 108 109 /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ 110 on_board_gpio_61: pinmux_ehci_port_select_pins { 111 pinctrl-single,pins = < 112 OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) 113 >; 114 }; 115 116 /* Used by OHCI and EHCI. OHCI won't work without external phy */ 117 hsusb2_pins: pinmux_hsusb2_pins { 118 pinctrl-single,pins = < 119 120 /* mcspi1_cs3.hsusb2_data2 */ 121 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) 122 123 /* mcspi2_clk.hsusb2_data7 */ 124 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) 125 126 /* mcspi2_simo.hsusb2_data4 */ 127 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) 128 129 /* mcspi2_somi.hsusb2_data5 */ 130 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) 131 132 /* mcspi2_cs0.hsusb2_data6 */ 133 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) 134 135 /* mcspi2_cs1.hsusb2_data3 */ 136 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) 137 >; 138 }; 139 140 wl12xx_gpio: pinmux_wl12xx_gpio { 141 pinctrl-single,pins = < 142 OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ 143 OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ 144 >; 145 }; 146 147 smsc911x_pins: pinmux_smsc911x_pins { 148 pinctrl-single,pins = < 149 OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ 150 >; 151 }; 152}; 153 154&omap3_pmx_core2 { 155 pinctrl-names = "default"; 156 pinctrl-0 = <&hsusb2_2_pins>; 157 158 ehci_phy_pins: pinmux_ehci_phy_pins { 159 pinctrl-single,pins = < 160 161 /* EHCI PHY reset GPIO etk_d7.gpio_21 */ 162 OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) 163 164 /* EHCI VBUS etk_d8.gpio_22 */ 165 OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) 166 >; 167 }; 168 169 /* Used by OHCI and EHCI. OHCI won't work without external phy */ 170 hsusb2_2_pins: pinmux_hsusb2_2_pins { 171 pinctrl-single,pins = < 172 173 /* etk_d10.hsusb2_clk */ 174 OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) 175 176 /* etk_d11.hsusb2_stp */ 177 OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) 178 179 /* etk_d12.hsusb2_dir */ 180 OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) 181 182 /* etk_d13.hsusb2_nxt */ 183 OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) 184 185 /* etk_d14.hsusb2_data0 */ 186 OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) 187 188 /* etk_d15.hsusb2_data1 */ 189 OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) 190 >; 191 }; 192}; 193 194&omap3_pmx_wkup { 195 dss_dpi_pins2: pinmux_dss_dpi_pins1 { 196 pinctrl-single,pins = < 197 OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ 198 OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ 199 OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ 200 OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ 201 OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ 202 OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ 203 >; 204 }; 205}; 206 207&mmc1 { 208 pinctrl-names = "default"; 209 pinctrl-0 = <&mmc1_pins>; 210}; 211 212&mmc2 { 213 pinctrl-names = "default"; 214 pinctrl-0 = <&mmc2_pins>; 215}; 216 217&mmc3 { 218 status = "disabled"; 219}; 220 221&uart1 { 222 interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; 223}; 224 225&uart2 { 226 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; 227}; 228 229&uart3 { 230 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&uart3_pins>; 233}; 234 235/* 236 * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface 237 * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. 238 */ 239&gpio2 { 240 en_usb2_port { 241 gpio-hog; 242 gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ 243 output-low; 244 line-name = "enable usb2 port"; 245 }; 246}; 247 248/* T2_GPIO_2 low to route GPIO_61 to on-board devices */ 249&twl_gpio { 250 en_on_board_gpio_61 { 251 gpio-hog; 252 gpios = <2 GPIO_ACTIVE_HIGH>; 253 output-low; 254 line-name = "en_hsusb2_clk"; 255 }; 256}; 257 258&gpmc { 259 ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ 260 <5 0 0x2c000000 0x01000000>; 261 262 nand@0,0 { 263 compatible = "ti,omap2-nand"; 264 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 265 interrupt-parent = <&gpmc>; 266 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 267 <1 IRQ_TYPE_NONE>; /* termcount */ 268 linux,mtd-name= "hynix,h8kds0un0mer-4em"; 269 nand-bus-width = <16>; 270 gpmc,device-width = <2>; 271 ti,nand-ecc-opt = "bch8"; 272 273 gpmc,sync-clk-ps = <0>; 274 gpmc,cs-on-ns = <0>; 275 gpmc,cs-rd-off-ns = <44>; 276 gpmc,cs-wr-off-ns = <44>; 277 gpmc,adv-on-ns = <6>; 278 gpmc,adv-rd-off-ns = <34>; 279 gpmc,adv-wr-off-ns = <44>; 280 gpmc,we-off-ns = <40>; 281 gpmc,oe-off-ns = <54>; 282 gpmc,access-ns = <64>; 283 gpmc,rd-cycle-ns = <82>; 284 gpmc,wr-cycle-ns = <82>; 285 gpmc,wr-access-ns = <40>; 286 gpmc,wr-data-mux-bus-ns = <0>; 287 288 #address-cells = <1>; 289 #size-cells = <1>; 290 291 partition@0 { 292 label = "X-Loader"; 293 reg = <0 0x80000>; 294 }; 295 partition@0x80000 { 296 label = "U-Boot"; 297 reg = <0x80000 0x1c0000>; 298 }; 299 partition@0x1c0000 { 300 label = "Environment"; 301 reg = <0x240000 0x40000>; 302 }; 303 partition@0x280000 { 304 label = "Kernel"; 305 reg = <0x280000 0x500000>; 306 }; 307 partition@0x780000 { 308 label = "Filesystem"; 309 reg = <0x780000 0x1f880000>; 310 }; 311 }; 312 313 ethernet@gpmc { 314 pinctrl-names = "default"; 315 pinctrl-0 = <&smsc911x_pins>; 316 }; 317}; 318