1/* 2 * Device Tree Source for OMAP3 SoC 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/omap.h> 14 15/ { 16 compatible = "ti,omap3430", "ti,omap3"; 17 interrupt-parent = <&intc>; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 chosen { }; 21 22 aliases { 23 i2c0 = &i2c1; 24 i2c1 = &i2c2; 25 i2c2 = &i2c3; 26 serial0 = &uart1; 27 serial1 = &uart2; 28 serial2 = &uart3; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu@0 { 36 compatible = "arm,cortex-a8"; 37 device_type = "cpu"; 38 reg = <0x0>; 39 40 clocks = <&dpll1_ck>; 41 clock-names = "cpu"; 42 43 clock-latency = <300000>; /* From omap-cpufreq driver */ 44 }; 45 }; 46 47 pmu@54000000 { 48 compatible = "arm,cortex-a8-pmu"; 49 reg = <0x54000000 0x800000>; 50 interrupts = <3>; 51 ti,hwmods = "debugss"; 52 }; 53 54 /* 55 * The soc node represents the soc top level view. It is used for IPs 56 * that are not memory mapped in the MPU view or for the MPU itself. 57 */ 58 soc { 59 compatible = "ti,omap-infra"; 60 mpu { 61 compatible = "ti,omap3-mpu"; 62 ti,hwmods = "mpu"; 63 }; 64 65 iva: iva { 66 compatible = "ti,iva2.2"; 67 ti,hwmods = "iva"; 68 69 dsp { 70 compatible = "ti,omap3-c64"; 71 }; 72 }; 73 }; 74 75 /* 76 * XXX: Use a flat representation of the OMAP3 interconnect. 77 * The real OMAP interconnect network is quite complex. 78 * Since it will not bring real advantage to represent that in DT for 79 * the moment, just use a fake OCP bus entry to represent the whole bus 80 * hierarchy. 81 */ 82 ocp@68000000 { 83 compatible = "ti,omap3-l3-smx", "simple-bus"; 84 reg = <0x68000000 0x10000>; 85 interrupts = <9 10>; 86 #address-cells = <1>; 87 #size-cells = <1>; 88 ranges; 89 ti,hwmods = "l3_main"; 90 91 l4_core: l4@48000000 { 92 compatible = "ti,omap3-l4-core", "simple-bus"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 ranges = <0 0x48000000 0x1000000>; 96 97 scm: scm@2000 { 98 compatible = "ti,omap3-scm", "simple-bus"; 99 reg = <0x2000 0x2000>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges = <0 0x2000 0x2000>; 103 104 omap3_pmx_core: pinmux@30 { 105 compatible = "ti,omap3-padconf", 106 "pinctrl-single"; 107 reg = <0x30 0x238>; 108 #address-cells = <1>; 109 #size-cells = <0>; 110 #pinctrl-cells = <1>; 111 #interrupt-cells = <1>; 112 interrupt-controller; 113 pinctrl-single,register-width = <16>; 114 pinctrl-single,function-mask = <0xff1f>; 115 }; 116 117 scm_conf: scm_conf@270 { 118 compatible = "syscon", "simple-bus"; 119 reg = <0x270 0x330>; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges = <0 0x270 0x330>; 123 124 pbias_regulator: pbias_regulator@2b0 { 125 compatible = "ti,pbias-omap3", "ti,pbias-omap"; 126 reg = <0x2b0 0x4>; 127 syscon = <&scm_conf>; 128 pbias_mmc_reg: pbias_mmc_omap2430 { 129 regulator-name = "pbias_mmc_omap2430"; 130 regulator-min-microvolt = <1800000>; 131 regulator-max-microvolt = <3000000>; 132 }; 133 }; 134 135 scm_clocks: clocks { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 }; 139 }; 140 141 scm_clockdomains: clockdomains { 142 }; 143 144 omap3_pmx_wkup: pinmux@a00 { 145 compatible = "ti,omap3-padconf", 146 "pinctrl-single"; 147 reg = <0xa00 0x5c>; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 #pinctrl-cells = <1>; 151 #interrupt-cells = <1>; 152 interrupt-controller; 153 pinctrl-single,register-width = <16>; 154 pinctrl-single,function-mask = <0xff1f>; 155 }; 156 }; 157 }; 158 159 aes: aes@480c5000 { 160 compatible = "ti,omap3-aes"; 161 ti,hwmods = "aes"; 162 reg = <0x480c5000 0x50>; 163 interrupts = <0>; 164 dmas = <&sdma 65 &sdma 66>; 165 dma-names = "tx", "rx"; 166 }; 167 168 prm: prm@48306000 { 169 compatible = "ti,omap3-prm"; 170 reg = <0x48306000 0x4000>; 171 interrupts = <11>; 172 173 prm_clocks: clocks { 174 #address-cells = <1>; 175 #size-cells = <0>; 176 }; 177 178 prm_clockdomains: clockdomains { 179 }; 180 }; 181 182 cm: cm@48004000 { 183 compatible = "ti,omap3-cm"; 184 reg = <0x48004000 0x4000>; 185 186 cm_clocks: clocks { 187 #address-cells = <1>; 188 #size-cells = <0>; 189 }; 190 191 cm_clockdomains: clockdomains { 192 }; 193 }; 194 195 counter32k: counter@48320000 { 196 compatible = "ti,omap-counter32k"; 197 reg = <0x48320000 0x20>; 198 ti,hwmods = "counter_32k"; 199 }; 200 201 intc: interrupt-controller@48200000 { 202 compatible = "ti,omap3-intc"; 203 interrupt-controller; 204 #interrupt-cells = <1>; 205 reg = <0x48200000 0x1000>; 206 }; 207 208 sdma: dma-controller@48056000 { 209 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; 210 reg = <0x48056000 0x1000>; 211 interrupts = <12>, 212 <13>, 213 <14>, 214 <15>; 215 #dma-cells = <1>; 216 dma-channels = <32>; 217 dma-requests = <96>; 218 }; 219 220 gpio1: gpio@48310000 { 221 compatible = "ti,omap3-gpio"; 222 reg = <0x48310000 0x200>; 223 interrupts = <29>; 224 ti,hwmods = "gpio1"; 225 ti,gpio-always-on; 226 gpio-controller; 227 #gpio-cells = <2>; 228 interrupt-controller; 229 #interrupt-cells = <2>; 230 }; 231 232 gpio2: gpio@49050000 { 233 compatible = "ti,omap3-gpio"; 234 reg = <0x49050000 0x200>; 235 interrupts = <30>; 236 ti,hwmods = "gpio2"; 237 gpio-controller; 238 #gpio-cells = <2>; 239 interrupt-controller; 240 #interrupt-cells = <2>; 241 }; 242 243 gpio3: gpio@49052000 { 244 compatible = "ti,omap3-gpio"; 245 reg = <0x49052000 0x200>; 246 interrupts = <31>; 247 ti,hwmods = "gpio3"; 248 gpio-controller; 249 #gpio-cells = <2>; 250 interrupt-controller; 251 #interrupt-cells = <2>; 252 }; 253 254 gpio4: gpio@49054000 { 255 compatible = "ti,omap3-gpio"; 256 reg = <0x49054000 0x200>; 257 interrupts = <32>; 258 ti,hwmods = "gpio4"; 259 gpio-controller; 260 #gpio-cells = <2>; 261 interrupt-controller; 262 #interrupt-cells = <2>; 263 }; 264 265 gpio5: gpio@49056000 { 266 compatible = "ti,omap3-gpio"; 267 reg = <0x49056000 0x200>; 268 interrupts = <33>; 269 ti,hwmods = "gpio5"; 270 gpio-controller; 271 #gpio-cells = <2>; 272 interrupt-controller; 273 #interrupt-cells = <2>; 274 }; 275 276 gpio6: gpio@49058000 { 277 compatible = "ti,omap3-gpio"; 278 reg = <0x49058000 0x200>; 279 interrupts = <34>; 280 ti,hwmods = "gpio6"; 281 gpio-controller; 282 #gpio-cells = <2>; 283 interrupt-controller; 284 #interrupt-cells = <2>; 285 }; 286 287 uart1: serial@4806a000 { 288 compatible = "ti,omap3-uart"; 289 reg = <0x4806a000 0x2000>; 290 interrupts-extended = <&intc 72>; 291 dmas = <&sdma 49 &sdma 50>; 292 dma-names = "tx", "rx"; 293 ti,hwmods = "uart1"; 294 clock-frequency = <48000000>; 295 }; 296 297 uart2: serial@4806c000 { 298 compatible = "ti,omap3-uart"; 299 reg = <0x4806c000 0x400>; 300 interrupts-extended = <&intc 73>; 301 dmas = <&sdma 51 &sdma 52>; 302 dma-names = "tx", "rx"; 303 ti,hwmods = "uart2"; 304 clock-frequency = <48000000>; 305 }; 306 307 uart3: serial@49020000 { 308 compatible = "ti,omap3-uart"; 309 reg = <0x49020000 0x400>; 310 interrupts-extended = <&intc 74>; 311 dmas = <&sdma 53 &sdma 54>; 312 dma-names = "tx", "rx"; 313 ti,hwmods = "uart3"; 314 clock-frequency = <48000000>; 315 }; 316 317 i2c1: i2c@48070000 { 318 compatible = "ti,omap3-i2c"; 319 reg = <0x48070000 0x80>; 320 interrupts = <56>; 321 dmas = <&sdma 27 &sdma 28>; 322 dma-names = "tx", "rx"; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 ti,hwmods = "i2c1"; 326 }; 327 328 i2c2: i2c@48072000 { 329 compatible = "ti,omap3-i2c"; 330 reg = <0x48072000 0x80>; 331 interrupts = <57>; 332 dmas = <&sdma 29 &sdma 30>; 333 dma-names = "tx", "rx"; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 ti,hwmods = "i2c2"; 337 }; 338 339 i2c3: i2c@48060000 { 340 compatible = "ti,omap3-i2c"; 341 reg = <0x48060000 0x80>; 342 interrupts = <61>; 343 dmas = <&sdma 25 &sdma 26>; 344 dma-names = "tx", "rx"; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 ti,hwmods = "i2c3"; 348 }; 349 350 mailbox: mailbox@48094000 { 351 compatible = "ti,omap3-mailbox"; 352 ti,hwmods = "mailbox"; 353 reg = <0x48094000 0x200>; 354 interrupts = <26>; 355 #mbox-cells = <1>; 356 ti,mbox-num-users = <2>; 357 ti,mbox-num-fifos = <2>; 358 mbox_dsp: dsp { 359 ti,mbox-tx = <0 0 0>; 360 ti,mbox-rx = <1 0 0>; 361 }; 362 }; 363 364 mcspi1: spi@48098000 { 365 compatible = "ti,omap2-mcspi"; 366 reg = <0x48098000 0x100>; 367 interrupts = <65>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 ti,hwmods = "mcspi1"; 371 ti,spi-num-cs = <4>; 372 dmas = <&sdma 35>, 373 <&sdma 36>, 374 <&sdma 37>, 375 <&sdma 38>, 376 <&sdma 39>, 377 <&sdma 40>, 378 <&sdma 41>, 379 <&sdma 42>; 380 dma-names = "tx0", "rx0", "tx1", "rx1", 381 "tx2", "rx2", "tx3", "rx3"; 382 }; 383 384 mcspi2: spi@4809a000 { 385 compatible = "ti,omap2-mcspi"; 386 reg = <0x4809a000 0x100>; 387 interrupts = <66>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 ti,hwmods = "mcspi2"; 391 ti,spi-num-cs = <2>; 392 dmas = <&sdma 43>, 393 <&sdma 44>, 394 <&sdma 45>, 395 <&sdma 46>; 396 dma-names = "tx0", "rx0", "tx1", "rx1"; 397 }; 398 399 mcspi3: spi@480b8000 { 400 compatible = "ti,omap2-mcspi"; 401 reg = <0x480b8000 0x100>; 402 interrupts = <91>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 ti,hwmods = "mcspi3"; 406 ti,spi-num-cs = <2>; 407 dmas = <&sdma 15>, 408 <&sdma 16>, 409 <&sdma 23>, 410 <&sdma 24>; 411 dma-names = "tx0", "rx0", "tx1", "rx1"; 412 }; 413 414 mcspi4: spi@480ba000 { 415 compatible = "ti,omap2-mcspi"; 416 reg = <0x480ba000 0x100>; 417 interrupts = <48>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 ti,hwmods = "mcspi4"; 421 ti,spi-num-cs = <1>; 422 dmas = <&sdma 70>, <&sdma 71>; 423 dma-names = "tx0", "rx0"; 424 }; 425 426 hdqw1w: 1w@480b2000 { 427 compatible = "ti,omap3-1w"; 428 reg = <0x480b2000 0x1000>; 429 interrupts = <58>; 430 ti,hwmods = "hdq1w"; 431 }; 432 433 mmc1: mmc@4809c000 { 434 compatible = "ti,omap3-hsmmc"; 435 reg = <0x4809c000 0x200>; 436 interrupts = <83>; 437 ti,hwmods = "mmc1"; 438 ti,dual-volt; 439 dmas = <&sdma 61>, <&sdma 62>; 440 dma-names = "tx", "rx"; 441 pbias-supply = <&pbias_mmc_reg>; 442 }; 443 444 mmc2: mmc@480b4000 { 445 compatible = "ti,omap3-hsmmc"; 446 reg = <0x480b4000 0x200>; 447 interrupts = <86>; 448 ti,hwmods = "mmc2"; 449 dmas = <&sdma 47>, <&sdma 48>; 450 dma-names = "tx", "rx"; 451 }; 452 453 mmc3: mmc@480ad000 { 454 compatible = "ti,omap3-hsmmc"; 455 reg = <0x480ad000 0x200>; 456 interrupts = <94>; 457 ti,hwmods = "mmc3"; 458 dmas = <&sdma 77>, <&sdma 78>; 459 dma-names = "tx", "rx"; 460 }; 461 462 mmu_isp: mmu@480bd400 { 463 #iommu-cells = <0>; 464 compatible = "ti,omap2-iommu"; 465 reg = <0x480bd400 0x80>; 466 interrupts = <24>; 467 ti,hwmods = "mmu_isp"; 468 ti,#tlb-entries = <8>; 469 }; 470 471 mmu_iva: mmu@5d000000 { 472 #iommu-cells = <0>; 473 compatible = "ti,omap2-iommu"; 474 reg = <0x5d000000 0x80>; 475 interrupts = <28>; 476 ti,hwmods = "mmu_iva"; 477 status = "disabled"; 478 }; 479 480 wdt2: wdt@48314000 { 481 compatible = "ti,omap3-wdt"; 482 reg = <0x48314000 0x80>; 483 ti,hwmods = "wd_timer2"; 484 }; 485 486 mcbsp1: mcbsp@48074000 { 487 compatible = "ti,omap3-mcbsp"; 488 reg = <0x48074000 0xff>; 489 reg-names = "mpu"; 490 interrupts = <16>, /* OCP compliant interrupt */ 491 <59>, /* TX interrupt */ 492 <60>; /* RX interrupt */ 493 interrupt-names = "common", "tx", "rx"; 494 ti,buffer-size = <128>; 495 ti,hwmods = "mcbsp1"; 496 dmas = <&sdma 31>, 497 <&sdma 32>; 498 dma-names = "tx", "rx"; 499 clocks = <&mcbsp1_fck>; 500 clock-names = "fck"; 501 status = "disabled"; 502 }; 503 504 mcbsp2: mcbsp@49022000 { 505 compatible = "ti,omap3-mcbsp"; 506 reg = <0x49022000 0xff>, 507 <0x49028000 0xff>; 508 reg-names = "mpu", "sidetone"; 509 interrupts = <17>, /* OCP compliant interrupt */ 510 <62>, /* TX interrupt */ 511 <63>, /* RX interrupt */ 512 <4>; /* Sidetone */ 513 interrupt-names = "common", "tx", "rx", "sidetone"; 514 ti,buffer-size = <1280>; 515 ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; 516 dmas = <&sdma 33>, 517 <&sdma 34>; 518 dma-names = "tx", "rx"; 519 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; 520 clock-names = "fck", "ick"; 521 status = "disabled"; 522 }; 523 524 mcbsp3: mcbsp@49024000 { 525 compatible = "ti,omap3-mcbsp"; 526 reg = <0x49024000 0xff>, 527 <0x4902a000 0xff>; 528 reg-names = "mpu", "sidetone"; 529 interrupts = <22>, /* OCP compliant interrupt */ 530 <89>, /* TX interrupt */ 531 <90>, /* RX interrupt */ 532 <5>; /* Sidetone */ 533 interrupt-names = "common", "tx", "rx", "sidetone"; 534 ti,buffer-size = <128>; 535 ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; 536 dmas = <&sdma 17>, 537 <&sdma 18>; 538 dma-names = "tx", "rx"; 539 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; 540 clock-names = "fck", "ick"; 541 status = "disabled"; 542 }; 543 544 mcbsp4: mcbsp@49026000 { 545 compatible = "ti,omap3-mcbsp"; 546 reg = <0x49026000 0xff>; 547 reg-names = "mpu"; 548 interrupts = <23>, /* OCP compliant interrupt */ 549 <54>, /* TX interrupt */ 550 <55>; /* RX interrupt */ 551 interrupt-names = "common", "tx", "rx"; 552 ti,buffer-size = <128>; 553 ti,hwmods = "mcbsp4"; 554 dmas = <&sdma 19>, 555 <&sdma 20>; 556 dma-names = "tx", "rx"; 557 clocks = <&mcbsp4_fck>; 558 clock-names = "fck"; 559 status = "disabled"; 560 }; 561 562 mcbsp5: mcbsp@48096000 { 563 compatible = "ti,omap3-mcbsp"; 564 reg = <0x48096000 0xff>; 565 reg-names = "mpu"; 566 interrupts = <27>, /* OCP compliant interrupt */ 567 <81>, /* TX interrupt */ 568 <82>; /* RX interrupt */ 569 interrupt-names = "common", "tx", "rx"; 570 ti,buffer-size = <128>; 571 ti,hwmods = "mcbsp5"; 572 dmas = <&sdma 21>, 573 <&sdma 22>; 574 dma-names = "tx", "rx"; 575 clocks = <&mcbsp5_fck>; 576 clock-names = "fck"; 577 status = "disabled"; 578 }; 579 580 sham: sham@480c3000 { 581 compatible = "ti,omap3-sham"; 582 ti,hwmods = "sham"; 583 reg = <0x480c3000 0x64>; 584 interrupts = <49>; 585 dmas = <&sdma 69>; 586 dma-names = "rx"; 587 }; 588 589 smartreflex_core: smartreflex@480cb000 { 590 compatible = "ti,omap3-smartreflex-core"; 591 ti,hwmods = "smartreflex_core"; 592 reg = <0x480cb000 0x400>; 593 interrupts = <19>; 594 }; 595 596 smartreflex_mpu_iva: smartreflex@480c9000 { 597 compatible = "ti,omap3-smartreflex-iva"; 598 ti,hwmods = "smartreflex_mpu_iva"; 599 reg = <0x480c9000 0x400>; 600 interrupts = <18>; 601 }; 602 603 timer1: timer@48318000 { 604 compatible = "ti,omap3430-timer"; 605 reg = <0x48318000 0x400>; 606 interrupts = <37>; 607 ti,hwmods = "timer1"; 608 ti,timer-alwon; 609 }; 610 611 timer2: timer@49032000 { 612 compatible = "ti,omap3430-timer"; 613 reg = <0x49032000 0x400>; 614 interrupts = <38>; 615 ti,hwmods = "timer2"; 616 }; 617 618 timer3: timer@49034000 { 619 compatible = "ti,omap3430-timer"; 620 reg = <0x49034000 0x400>; 621 interrupts = <39>; 622 ti,hwmods = "timer3"; 623 }; 624 625 timer4: timer@49036000 { 626 compatible = "ti,omap3430-timer"; 627 reg = <0x49036000 0x400>; 628 interrupts = <40>; 629 ti,hwmods = "timer4"; 630 }; 631 632 timer5: timer@49038000 { 633 compatible = "ti,omap3430-timer"; 634 reg = <0x49038000 0x400>; 635 interrupts = <41>; 636 ti,hwmods = "timer5"; 637 ti,timer-dsp; 638 }; 639 640 timer6: timer@4903a000 { 641 compatible = "ti,omap3430-timer"; 642 reg = <0x4903a000 0x400>; 643 interrupts = <42>; 644 ti,hwmods = "timer6"; 645 ti,timer-dsp; 646 }; 647 648 timer7: timer@4903c000 { 649 compatible = "ti,omap3430-timer"; 650 reg = <0x4903c000 0x400>; 651 interrupts = <43>; 652 ti,hwmods = "timer7"; 653 ti,timer-dsp; 654 }; 655 656 timer8: timer@4903e000 { 657 compatible = "ti,omap3430-timer"; 658 reg = <0x4903e000 0x400>; 659 interrupts = <44>; 660 ti,hwmods = "timer8"; 661 ti,timer-pwm; 662 ti,timer-dsp; 663 }; 664 665 timer9: timer@49040000 { 666 compatible = "ti,omap3430-timer"; 667 reg = <0x49040000 0x400>; 668 interrupts = <45>; 669 ti,hwmods = "timer9"; 670 ti,timer-pwm; 671 }; 672 673 timer10: timer@48086000 { 674 compatible = "ti,omap3430-timer"; 675 reg = <0x48086000 0x400>; 676 interrupts = <46>; 677 ti,hwmods = "timer10"; 678 ti,timer-pwm; 679 }; 680 681 timer11: timer@48088000 { 682 compatible = "ti,omap3430-timer"; 683 reg = <0x48088000 0x400>; 684 interrupts = <47>; 685 ti,hwmods = "timer11"; 686 ti,timer-pwm; 687 }; 688 689 timer12: timer@48304000 { 690 compatible = "ti,omap3430-timer"; 691 reg = <0x48304000 0x400>; 692 interrupts = <95>; 693 ti,hwmods = "timer12"; 694 ti,timer-alwon; 695 ti,timer-secure; 696 }; 697 698 usbhstll: usbhstll@48062000 { 699 compatible = "ti,usbhs-tll"; 700 reg = <0x48062000 0x1000>; 701 interrupts = <78>; 702 ti,hwmods = "usb_tll_hs"; 703 }; 704 705 usbhshost: usbhshost@48064000 { 706 compatible = "ti,usbhs-host"; 707 reg = <0x48064000 0x400>; 708 ti,hwmods = "usb_host_hs"; 709 #address-cells = <1>; 710 #size-cells = <1>; 711 ranges; 712 713 usbhsohci: ohci@48064400 { 714 compatible = "ti,ohci-omap3"; 715 reg = <0x48064400 0x400>; 716 interrupts = <76>; 717 }; 718 719 usbhsehci: ehci@48064800 { 720 compatible = "ti,ehci-omap"; 721 reg = <0x48064800 0x400>; 722 interrupts = <77>; 723 }; 724 }; 725 726 gpmc: gpmc@6e000000 { 727 compatible = "ti,omap3430-gpmc"; 728 ti,hwmods = "gpmc"; 729 reg = <0x6e000000 0x02d0>; 730 interrupts = <20>; 731 dmas = <&sdma 4>; 732 dma-names = "rxtx"; 733 gpmc,num-cs = <8>; 734 gpmc,num-waitpins = <4>; 735 #address-cells = <2>; 736 #size-cells = <1>; 737 interrupt-controller; 738 #interrupt-cells = <2>; 739 gpio-controller; 740 #gpio-cells = <2>; 741 }; 742 743 usb_otg_hs: usb_otg_hs@480ab000 { 744 compatible = "ti,omap3-musb"; 745 reg = <0x480ab000 0x1000>; 746 interrupts = <92>, <93>; 747 interrupt-names = "mc", "dma"; 748 ti,hwmods = "usb_otg_hs"; 749 multipoint = <1>; 750 num-eps = <16>; 751 ram-bits = <12>; 752 }; 753 754 dss: dss@48050000 { 755 compatible = "ti,omap3-dss"; 756 reg = <0x48050000 0x200>; 757 status = "disabled"; 758 ti,hwmods = "dss_core"; 759 clocks = <&dss1_alwon_fck>; 760 clock-names = "fck"; 761 #address-cells = <1>; 762 #size-cells = <1>; 763 ranges; 764 765 dispc@48050400 { 766 compatible = "ti,omap3-dispc"; 767 reg = <0x48050400 0x400>; 768 interrupts = <25>; 769 ti,hwmods = "dss_dispc"; 770 clocks = <&dss1_alwon_fck>; 771 clock-names = "fck"; 772 }; 773 774 dsi: encoder@4804fc00 { 775 compatible = "ti,omap3-dsi"; 776 reg = <0x4804fc00 0x200>, 777 <0x4804fe00 0x40>, 778 <0x4804ff00 0x20>; 779 reg-names = "proto", "phy", "pll"; 780 interrupts = <25>; 781 status = "disabled"; 782 ti,hwmods = "dss_dsi1"; 783 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; 784 clock-names = "fck", "sys_clk"; 785 }; 786 787 rfbi: encoder@48050800 { 788 compatible = "ti,omap3-rfbi"; 789 reg = <0x48050800 0x100>; 790 status = "disabled"; 791 ti,hwmods = "dss_rfbi"; 792 clocks = <&dss1_alwon_fck>, <&dss_ick>; 793 clock-names = "fck", "ick"; 794 }; 795 796 venc: encoder@48050c00 { 797 compatible = "ti,omap3-venc"; 798 reg = <0x48050c00 0x100>; 799 status = "disabled"; 800 ti,hwmods = "dss_venc"; 801 clocks = <&dss_tv_fck>; 802 clock-names = "fck"; 803 }; 804 }; 805 806 ssi: ssi-controller@48058000 { 807 compatible = "ti,omap3-ssi"; 808 ti,hwmods = "ssi"; 809 810 status = "disabled"; 811 812 reg = <0x48058000 0x1000>, 813 <0x48059000 0x1000>; 814 reg-names = "sys", 815 "gdd"; 816 817 interrupts = <71>; 818 interrupt-names = "gdd_mpu"; 819 820 #address-cells = <1>; 821 #size-cells = <1>; 822 ranges; 823 824 ssi_port1: ssi-port@4805a000 { 825 compatible = "ti,omap3-ssi-port"; 826 827 reg = <0x4805a000 0x800>, 828 <0x4805a800 0x800>; 829 reg-names = "tx", 830 "rx"; 831 832 interrupts = <67>, 833 <68>; 834 }; 835 836 ssi_port2: ssi-port@4805b000 { 837 compatible = "ti,omap3-ssi-port"; 838 839 reg = <0x4805b000 0x800>, 840 <0x4805b800 0x800>; 841 reg-names = "tx", 842 "rx"; 843 844 interrupts = <69>, 845 <70>; 846 }; 847 }; 848 }; 849}; 850 851/include/ "omap3xxx-clocks.dtsi" 852