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1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/pinctrl/omap.h>
13
14/ {
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	compatible = "ti,omap5";
19	interrupt-parent = <&wakeupgen>;
20	chosen { };
21
22	aliases {
23		i2c0 = &i2c1;
24		i2c1 = &i2c2;
25		i2c2 = &i2c3;
26		i2c3 = &i2c4;
27		i2c4 = &i2c5;
28		serial0 = &uart1;
29		serial1 = &uart2;
30		serial2 = &uart3;
31		serial3 = &uart4;
32		serial4 = &uart5;
33		serial5 = &uart6;
34	};
35
36	cpus {
37		#address-cells = <1>;
38		#size-cells = <0>;
39
40		cpu0: cpu@0 {
41			device_type = "cpu";
42			compatible = "arm,cortex-a15";
43			reg = <0x0>;
44
45			operating-points = <
46				/* kHz    uV */
47				1000000 1060000
48				1500000 1250000
49			>;
50
51			clocks = <&dpll_mpu_ck>;
52			clock-names = "cpu";
53
54			clock-latency = <300000>; /* From omap-cpufreq driver */
55
56			/* cooling options */
57			cooling-min-level = <0>;
58			cooling-max-level = <2>;
59			#cooling-cells = <2>; /* min followed by max */
60		};
61		cpu@1 {
62			device_type = "cpu";
63			compatible = "arm,cortex-a15";
64			reg = <0x1>;
65		};
66	};
67
68	thermal-zones {
69		#include "omap4-cpu-thermal.dtsi"
70		#include "omap5-gpu-thermal.dtsi"
71		#include "omap5-core-thermal.dtsi"
72	};
73
74	timer {
75		compatible = "arm,armv7-timer";
76		/* PPI secure/nonsecure IRQ */
77		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
78			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
79			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
81		interrupt-parent = <&gic>;
82	};
83
84	pmu {
85		compatible = "arm,cortex-a15-pmu";
86		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
87			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
88	};
89
90	gic: interrupt-controller@48211000 {
91		compatible = "arm,cortex-a15-gic";
92		interrupt-controller;
93		#interrupt-cells = <3>;
94		reg = <0 0x48211000 0 0x1000>,
95		      <0 0x48212000 0 0x2000>,
96		      <0 0x48214000 0 0x2000>,
97		      <0 0x48216000 0 0x2000>;
98		interrupt-parent = <&gic>;
99	};
100
101	wakeupgen: interrupt-controller@48281000 {
102		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
103		interrupt-controller;
104		#interrupt-cells = <3>;
105		reg = <0 0x48281000 0 0x1000>;
106		interrupt-parent = <&gic>;
107	};
108
109	/*
110	 * The soc node represents the soc top level view. It is used for IPs
111	 * that are not memory mapped in the MPU view or for the MPU itself.
112	 */
113	soc {
114		compatible = "ti,omap-infra";
115		mpu {
116			compatible = "ti,omap4-mpu";
117			ti,hwmods = "mpu";
118			sram = <&ocmcram>;
119		};
120	};
121
122	/*
123	 * XXX: Use a flat representation of the OMAP3 interconnect.
124	 * The real OMAP interconnect network is quite complex.
125	 * Since it will not bring real advantage to represent that in DT for
126	 * the moment, just use a fake OCP bus entry to represent the whole bus
127	 * hierarchy.
128	 */
129	ocp {
130		compatible = "ti,omap5-l3-noc", "simple-bus";
131		#address-cells = <1>;
132		#size-cells = <1>;
133		ranges = <0 0 0 0xc0000000>;
134		dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
135		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
136		reg = <0 0x44000000 0 0x2000>,
137		      <0 0x44800000 0 0x3000>,
138		      <0 0x45000000 0 0x4000>;
139		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
140			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
141
142		l4_cfg: l4@4a000000 {
143			compatible = "ti,omap5-l4-cfg", "simple-bus";
144			#address-cells = <1>;
145			#size-cells = <1>;
146			ranges = <0 0x4a000000 0x22a000>;
147
148			scm_core: scm@2000 {
149				compatible = "ti,omap5-scm-core", "simple-bus";
150				reg = <0x2000 0x1000>;
151				#address-cells = <1>;
152				#size-cells = <1>;
153				ranges = <0 0x2000 0x800>;
154
155				scm_conf: scm_conf@0 {
156					compatible = "syscon";
157					reg = <0x0 0x800>;
158					#address-cells = <1>;
159					#size-cells = <1>;
160				};
161			};
162
163			scm_padconf_core: scm@2800 {
164				compatible = "ti,omap5-scm-padconf-core",
165					     "simple-bus";
166				#address-cells = <1>;
167				#size-cells = <1>;
168				ranges = <0 0x2800 0x800>;
169
170				omap5_pmx_core: pinmux@40 {
171					compatible = "ti,omap5-padconf",
172						     "pinctrl-single";
173					reg = <0x40 0x01b6>;
174					#address-cells = <1>;
175					#size-cells = <0>;
176					#pinctrl-cells = <1>;
177					#interrupt-cells = <1>;
178					interrupt-controller;
179					pinctrl-single,register-width = <16>;
180					pinctrl-single,function-mask = <0x7fff>;
181				};
182
183				omap5_padconf_global: omap5_padconf_global@5a0 {
184					compatible = "syscon",
185						     "simple-bus";
186					reg = <0x5a0 0xec>;
187					#address-cells = <1>;
188					#size-cells = <1>;
189					ranges = <0 0x5a0 0xec>;
190
191					pbias_regulator: pbias_regulator@60 {
192						compatible = "ti,pbias-omap5", "ti,pbias-omap";
193						reg = <0x60 0x4>;
194						syscon = <&omap5_padconf_global>;
195						pbias_mmc_reg: pbias_mmc_omap5 {
196							regulator-name = "pbias_mmc_omap5";
197							regulator-min-microvolt = <1800000>;
198							regulator-max-microvolt = <3000000>;
199						};
200					};
201				};
202			};
203
204			cm_core_aon: cm_core_aon@4000 {
205				compatible = "ti,omap5-cm-core-aon";
206				reg = <0x4000 0x2000>;
207
208				cm_core_aon_clocks: clocks {
209					#address-cells = <1>;
210					#size-cells = <0>;
211				};
212
213				cm_core_aon_clockdomains: clockdomains {
214				};
215			};
216
217			cm_core: cm_core@8000 {
218				compatible = "ti,omap5-cm-core";
219				reg = <0x8000 0x3000>;
220
221				cm_core_clocks: clocks {
222					#address-cells = <1>;
223					#size-cells = <0>;
224				};
225
226				cm_core_clockdomains: clockdomains {
227				};
228			};
229		};
230
231		l4_wkup: l4@4ae00000 {
232			compatible = "ti,omap5-l4-wkup", "simple-bus";
233			#address-cells = <1>;
234			#size-cells = <1>;
235			ranges = <0 0x4ae00000 0x2b000>;
236
237			counter32k: counter@4000 {
238				compatible = "ti,omap-counter32k";
239				reg = <0x4000 0x40>;
240				ti,hwmods = "counter_32k";
241			};
242
243			prm: prm@6000 {
244				compatible = "ti,omap5-prm";
245				reg = <0x6000 0x3000>;
246				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
247
248				prm_clocks: clocks {
249					#address-cells = <1>;
250					#size-cells = <0>;
251				};
252
253				prm_clockdomains: clockdomains {
254				};
255			};
256
257			scrm: scrm@a000 {
258				compatible = "ti,omap5-scrm";
259				reg = <0xa000 0x2000>;
260
261				scrm_clocks: clocks {
262					#address-cells = <1>;
263					#size-cells = <0>;
264				};
265
266				scrm_clockdomains: clockdomains {
267				};
268			};
269
270			omap5_pmx_wkup: pinmux@c840 {
271				compatible = "ti,omap5-padconf",
272					     "pinctrl-single";
273				reg = <0xc840 0x003c>;
274				#address-cells = <1>;
275				#size-cells = <0>;
276				#pinctrl-cells = <1>;
277				#interrupt-cells = <1>;
278				interrupt-controller;
279				pinctrl-single,register-width = <16>;
280				pinctrl-single,function-mask = <0x7fff>;
281			};
282		};
283
284		ocmcram: ocmcram@40300000 {
285			compatible = "mmio-sram";
286			reg = <0x40300000 0x20000>; /* 128k */
287		};
288
289		sdma: dma-controller@4a056000 {
290			compatible = "ti,omap4430-sdma";
291			reg = <0x4a056000 0x1000>;
292			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
293				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
294				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
295				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
296			#dma-cells = <1>;
297			dma-channels = <32>;
298			dma-requests = <127>;
299		};
300
301		gpio1: gpio@4ae10000 {
302			compatible = "ti,omap4-gpio";
303			reg = <0x4ae10000 0x200>;
304			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
305			ti,hwmods = "gpio1";
306			ti,gpio-always-on;
307			gpio-controller;
308			#gpio-cells = <2>;
309			interrupt-controller;
310			#interrupt-cells = <2>;
311		};
312
313		gpio2: gpio@48055000 {
314			compatible = "ti,omap4-gpio";
315			reg = <0x48055000 0x200>;
316			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
317			ti,hwmods = "gpio2";
318			gpio-controller;
319			#gpio-cells = <2>;
320			interrupt-controller;
321			#interrupt-cells = <2>;
322		};
323
324		gpio3: gpio@48057000 {
325			compatible = "ti,omap4-gpio";
326			reg = <0x48057000 0x200>;
327			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
328			ti,hwmods = "gpio3";
329			gpio-controller;
330			#gpio-cells = <2>;
331			interrupt-controller;
332			#interrupt-cells = <2>;
333		};
334
335		gpio4: gpio@48059000 {
336			compatible = "ti,omap4-gpio";
337			reg = <0x48059000 0x200>;
338			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
339			ti,hwmods = "gpio4";
340			gpio-controller;
341			#gpio-cells = <2>;
342			interrupt-controller;
343			#interrupt-cells = <2>;
344		};
345
346		gpio5: gpio@4805b000 {
347			compatible = "ti,omap4-gpio";
348			reg = <0x4805b000 0x200>;
349			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
350			ti,hwmods = "gpio5";
351			gpio-controller;
352			#gpio-cells = <2>;
353			interrupt-controller;
354			#interrupt-cells = <2>;
355		};
356
357		gpio6: gpio@4805d000 {
358			compatible = "ti,omap4-gpio";
359			reg = <0x4805d000 0x200>;
360			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
361			ti,hwmods = "gpio6";
362			gpio-controller;
363			#gpio-cells = <2>;
364			interrupt-controller;
365			#interrupt-cells = <2>;
366		};
367
368		gpio7: gpio@48051000 {
369			compatible = "ti,omap4-gpio";
370			reg = <0x48051000 0x200>;
371			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
372			ti,hwmods = "gpio7";
373			gpio-controller;
374			#gpio-cells = <2>;
375			interrupt-controller;
376			#interrupt-cells = <2>;
377		};
378
379		gpio8: gpio@48053000 {
380			compatible = "ti,omap4-gpio";
381			reg = <0x48053000 0x200>;
382			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
383			ti,hwmods = "gpio8";
384			gpio-controller;
385			#gpio-cells = <2>;
386			interrupt-controller;
387			#interrupt-cells = <2>;
388		};
389
390		gpmc: gpmc@50000000 {
391			compatible = "ti,omap4430-gpmc";
392			reg = <0x50000000 0x1000>;
393			#address-cells = <2>;
394			#size-cells = <1>;
395			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
396			dmas = <&sdma 4>;
397			dma-names = "rxtx";
398			gpmc,num-cs = <8>;
399			gpmc,num-waitpins = <4>;
400			ti,hwmods = "gpmc";
401			clocks = <&l3_iclk_div>;
402			clock-names = "fck";
403			interrupt-controller;
404			#interrupt-cells = <2>;
405			gpio-controller;
406			#gpio-cells = <2>;
407		};
408
409		i2c1: i2c@48070000 {
410			compatible = "ti,omap4-i2c";
411			reg = <0x48070000 0x100>;
412			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
413			#address-cells = <1>;
414			#size-cells = <0>;
415			ti,hwmods = "i2c1";
416		};
417
418		i2c2: i2c@48072000 {
419			compatible = "ti,omap4-i2c";
420			reg = <0x48072000 0x100>;
421			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
422			#address-cells = <1>;
423			#size-cells = <0>;
424			ti,hwmods = "i2c2";
425		};
426
427		i2c3: i2c@48060000 {
428			compatible = "ti,omap4-i2c";
429			reg = <0x48060000 0x100>;
430			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
431			#address-cells = <1>;
432			#size-cells = <0>;
433			ti,hwmods = "i2c3";
434		};
435
436		i2c4: i2c@4807a000 {
437			compatible = "ti,omap4-i2c";
438			reg = <0x4807a000 0x100>;
439			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
440			#address-cells = <1>;
441			#size-cells = <0>;
442			ti,hwmods = "i2c4";
443		};
444
445		i2c5: i2c@4807c000 {
446			compatible = "ti,omap4-i2c";
447			reg = <0x4807c000 0x100>;
448			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
449			#address-cells = <1>;
450			#size-cells = <0>;
451			ti,hwmods = "i2c5";
452		};
453
454		hwspinlock: spinlock@4a0f6000 {
455			compatible = "ti,omap4-hwspinlock";
456			reg = <0x4a0f6000 0x1000>;
457			ti,hwmods = "spinlock";
458			#hwlock-cells = <1>;
459		};
460
461		mcspi1: spi@48098000 {
462			compatible = "ti,omap4-mcspi";
463			reg = <0x48098000 0x200>;
464			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
465			#address-cells = <1>;
466			#size-cells = <0>;
467			ti,hwmods = "mcspi1";
468			ti,spi-num-cs = <4>;
469			dmas = <&sdma 35>,
470			       <&sdma 36>,
471			       <&sdma 37>,
472			       <&sdma 38>,
473			       <&sdma 39>,
474			       <&sdma 40>,
475			       <&sdma 41>,
476			       <&sdma 42>;
477			dma-names = "tx0", "rx0", "tx1", "rx1",
478				    "tx2", "rx2", "tx3", "rx3";
479		};
480
481		mcspi2: spi@4809a000 {
482			compatible = "ti,omap4-mcspi";
483			reg = <0x4809a000 0x200>;
484			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
485			#address-cells = <1>;
486			#size-cells = <0>;
487			ti,hwmods = "mcspi2";
488			ti,spi-num-cs = <2>;
489			dmas = <&sdma 43>,
490			       <&sdma 44>,
491			       <&sdma 45>,
492			       <&sdma 46>;
493			dma-names = "tx0", "rx0", "tx1", "rx1";
494		};
495
496		mcspi3: spi@480b8000 {
497			compatible = "ti,omap4-mcspi";
498			reg = <0x480b8000 0x200>;
499			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
500			#address-cells = <1>;
501			#size-cells = <0>;
502			ti,hwmods = "mcspi3";
503			ti,spi-num-cs = <2>;
504			dmas = <&sdma 15>, <&sdma 16>;
505			dma-names = "tx0", "rx0";
506		};
507
508		mcspi4: spi@480ba000 {
509			compatible = "ti,omap4-mcspi";
510			reg = <0x480ba000 0x200>;
511			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
512			#address-cells = <1>;
513			#size-cells = <0>;
514			ti,hwmods = "mcspi4";
515			ti,spi-num-cs = <1>;
516			dmas = <&sdma 70>, <&sdma 71>;
517			dma-names = "tx0", "rx0";
518		};
519
520		uart1: serial@4806a000 {
521			compatible = "ti,omap4-uart";
522			reg = <0x4806a000 0x100>;
523			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
524			ti,hwmods = "uart1";
525			clock-frequency = <48000000>;
526		};
527
528		uart2: serial@4806c000 {
529			compatible = "ti,omap4-uart";
530			reg = <0x4806c000 0x100>;
531			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
532			ti,hwmods = "uart2";
533			clock-frequency = <48000000>;
534		};
535
536		uart3: serial@48020000 {
537			compatible = "ti,omap4-uart";
538			reg = <0x48020000 0x100>;
539			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
540			ti,hwmods = "uart3";
541			clock-frequency = <48000000>;
542		};
543
544		uart4: serial@4806e000 {
545			compatible = "ti,omap4-uart";
546			reg = <0x4806e000 0x100>;
547			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
548			ti,hwmods = "uart4";
549			clock-frequency = <48000000>;
550		};
551
552		uart5: serial@48066000 {
553			compatible = "ti,omap4-uart";
554			reg = <0x48066000 0x100>;
555			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
556			ti,hwmods = "uart5";
557			clock-frequency = <48000000>;
558		};
559
560		uart6: serial@48068000 {
561			compatible = "ti,omap4-uart";
562			reg = <0x48068000 0x100>;
563			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
564			ti,hwmods = "uart6";
565			clock-frequency = <48000000>;
566		};
567
568		mmc1: mmc@4809c000 {
569			compatible = "ti,omap4-hsmmc";
570			reg = <0x4809c000 0x400>;
571			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
572			ti,hwmods = "mmc1";
573			ti,dual-volt;
574			ti,needs-special-reset;
575			dmas = <&sdma 61>, <&sdma 62>;
576			dma-names = "tx", "rx";
577			pbias-supply = <&pbias_mmc_reg>;
578		};
579
580		mmc2: mmc@480b4000 {
581			compatible = "ti,omap4-hsmmc";
582			reg = <0x480b4000 0x400>;
583			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
584			ti,hwmods = "mmc2";
585			ti,needs-special-reset;
586			dmas = <&sdma 47>, <&sdma 48>;
587			dma-names = "tx", "rx";
588		};
589
590		mmc3: mmc@480ad000 {
591			compatible = "ti,omap4-hsmmc";
592			reg = <0x480ad000 0x400>;
593			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
594			ti,hwmods = "mmc3";
595			ti,needs-special-reset;
596			dmas = <&sdma 77>, <&sdma 78>;
597			dma-names = "tx", "rx";
598		};
599
600		mmc4: mmc@480d1000 {
601			compatible = "ti,omap4-hsmmc";
602			reg = <0x480d1000 0x400>;
603			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
604			ti,hwmods = "mmc4";
605			ti,needs-special-reset;
606			dmas = <&sdma 57>, <&sdma 58>;
607			dma-names = "tx", "rx";
608		};
609
610		mmc5: mmc@480d5000 {
611			compatible = "ti,omap4-hsmmc";
612			reg = <0x480d5000 0x400>;
613			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
614			ti,hwmods = "mmc5";
615			ti,needs-special-reset;
616			dmas = <&sdma 59>, <&sdma 60>;
617			dma-names = "tx", "rx";
618		};
619
620		mmu_dsp: mmu@4a066000 {
621			compatible = "ti,omap4-iommu";
622			reg = <0x4a066000 0x100>;
623			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
624			ti,hwmods = "mmu_dsp";
625			#iommu-cells = <0>;
626		};
627
628		mmu_ipu: mmu@55082000 {
629			compatible = "ti,omap4-iommu";
630			reg = <0x55082000 0x100>;
631			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
632			ti,hwmods = "mmu_ipu";
633			#iommu-cells = <0>;
634			ti,iommu-bus-err-back;
635		};
636
637		keypad: keypad@4ae1c000 {
638			compatible = "ti,omap4-keypad";
639			reg = <0x4ae1c000 0x400>;
640			ti,hwmods = "kbd";
641		};
642
643		mcpdm: mcpdm@40132000 {
644			compatible = "ti,omap4-mcpdm";
645			reg = <0x40132000 0x7f>, /* MPU private access */
646			      <0x49032000 0x7f>; /* L3 Interconnect */
647			reg-names = "mpu", "dma";
648			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
649			ti,hwmods = "mcpdm";
650			dmas = <&sdma 65>,
651			       <&sdma 66>;
652			dma-names = "up_link", "dn_link";
653			status = "disabled";
654		};
655
656		dmic: dmic@4012e000 {
657			compatible = "ti,omap4-dmic";
658			reg = <0x4012e000 0x7f>, /* MPU private access */
659			      <0x4902e000 0x7f>; /* L3 Interconnect */
660			reg-names = "mpu", "dma";
661			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
662			ti,hwmods = "dmic";
663			dmas = <&sdma 67>;
664			dma-names = "up_link";
665			status = "disabled";
666		};
667
668		mcbsp1: mcbsp@40122000 {
669			compatible = "ti,omap4-mcbsp";
670			reg = <0x40122000 0xff>, /* MPU private access */
671			      <0x49022000 0xff>; /* L3 Interconnect */
672			reg-names = "mpu", "dma";
673			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
674			interrupt-names = "common";
675			ti,buffer-size = <128>;
676			ti,hwmods = "mcbsp1";
677			dmas = <&sdma 33>,
678			       <&sdma 34>;
679			dma-names = "tx", "rx";
680			status = "disabled";
681		};
682
683		mcbsp2: mcbsp@40124000 {
684			compatible = "ti,omap4-mcbsp";
685			reg = <0x40124000 0xff>, /* MPU private access */
686			      <0x49024000 0xff>; /* L3 Interconnect */
687			reg-names = "mpu", "dma";
688			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
689			interrupt-names = "common";
690			ti,buffer-size = <128>;
691			ti,hwmods = "mcbsp2";
692			dmas = <&sdma 17>,
693			       <&sdma 18>;
694			dma-names = "tx", "rx";
695			status = "disabled";
696		};
697
698		mcbsp3: mcbsp@40126000 {
699			compatible = "ti,omap4-mcbsp";
700			reg = <0x40126000 0xff>, /* MPU private access */
701			      <0x49026000 0xff>; /* L3 Interconnect */
702			reg-names = "mpu", "dma";
703			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
704			interrupt-names = "common";
705			ti,buffer-size = <128>;
706			ti,hwmods = "mcbsp3";
707			dmas = <&sdma 19>,
708			       <&sdma 20>;
709			dma-names = "tx", "rx";
710			status = "disabled";
711		};
712
713		mailbox: mailbox@4a0f4000 {
714			compatible = "ti,omap4-mailbox";
715			reg = <0x4a0f4000 0x200>;
716			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
717			ti,hwmods = "mailbox";
718			#mbox-cells = <1>;
719			ti,mbox-num-users = <3>;
720			ti,mbox-num-fifos = <8>;
721			mbox_ipu: mbox_ipu {
722				ti,mbox-tx = <0 0 0>;
723				ti,mbox-rx = <1 0 0>;
724			};
725			mbox_dsp: mbox_dsp {
726				ti,mbox-tx = <3 0 0>;
727				ti,mbox-rx = <2 0 0>;
728			};
729		};
730
731		timer1: timer@4ae18000 {
732			compatible = "ti,omap5430-timer";
733			reg = <0x4ae18000 0x80>;
734			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
735			ti,hwmods = "timer1";
736			ti,timer-alwon;
737		};
738
739		timer2: timer@48032000 {
740			compatible = "ti,omap5430-timer";
741			reg = <0x48032000 0x80>;
742			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
743			ti,hwmods = "timer2";
744		};
745
746		timer3: timer@48034000 {
747			compatible = "ti,omap5430-timer";
748			reg = <0x48034000 0x80>;
749			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
750			ti,hwmods = "timer3";
751		};
752
753		timer4: timer@48036000 {
754			compatible = "ti,omap5430-timer";
755			reg = <0x48036000 0x80>;
756			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
757			ti,hwmods = "timer4";
758		};
759
760		timer5: timer@40138000 {
761			compatible = "ti,omap5430-timer";
762			reg = <0x40138000 0x80>,
763			      <0x49038000 0x80>;
764			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
765			ti,hwmods = "timer5";
766			ti,timer-dsp;
767			ti,timer-pwm;
768		};
769
770		timer6: timer@4013a000 {
771			compatible = "ti,omap5430-timer";
772			reg = <0x4013a000 0x80>,
773			      <0x4903a000 0x80>;
774			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
775			ti,hwmods = "timer6";
776			ti,timer-dsp;
777			ti,timer-pwm;
778		};
779
780		timer7: timer@4013c000 {
781			compatible = "ti,omap5430-timer";
782			reg = <0x4013c000 0x80>,
783			      <0x4903c000 0x80>;
784			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
785			ti,hwmods = "timer7";
786			ti,timer-dsp;
787		};
788
789		timer8: timer@4013e000 {
790			compatible = "ti,omap5430-timer";
791			reg = <0x4013e000 0x80>,
792			      <0x4903e000 0x80>;
793			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
794			ti,hwmods = "timer8";
795			ti,timer-dsp;
796			ti,timer-pwm;
797		};
798
799		timer9: timer@4803e000 {
800			compatible = "ti,omap5430-timer";
801			reg = <0x4803e000 0x80>;
802			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
803			ti,hwmods = "timer9";
804			ti,timer-pwm;
805		};
806
807		timer10: timer@48086000 {
808			compatible = "ti,omap5430-timer";
809			reg = <0x48086000 0x80>;
810			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
811			ti,hwmods = "timer10";
812			ti,timer-pwm;
813		};
814
815		timer11: timer@48088000 {
816			compatible = "ti,omap5430-timer";
817			reg = <0x48088000 0x80>;
818			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
819			ti,hwmods = "timer11";
820			ti,timer-pwm;
821		};
822
823		wdt2: wdt@4ae14000 {
824			compatible = "ti,omap5-wdt", "ti,omap3-wdt";
825			reg = <0x4ae14000 0x80>;
826			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
827			ti,hwmods = "wd_timer2";
828		};
829
830		dmm@4e000000 {
831			compatible = "ti,omap5-dmm";
832			reg = <0x4e000000 0x800>;
833			interrupts = <0 113 0x4>;
834			ti,hwmods = "dmm";
835		};
836
837		emif1: emif@4c000000 {
838			compatible	= "ti,emif-4d5";
839			ti,hwmods	= "emif1";
840			ti,no-idle-on-init;
841			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
842			reg = <0x4c000000 0x400>;
843			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
844			hw-caps-read-idle-ctrl;
845			hw-caps-ll-interface;
846			hw-caps-temp-alert;
847		};
848
849		emif2: emif@4d000000 {
850			compatible	= "ti,emif-4d5";
851			ti,hwmods	= "emif2";
852			ti,no-idle-on-init;
853			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
854			reg = <0x4d000000 0x400>;
855			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
856			hw-caps-read-idle-ctrl;
857			hw-caps-ll-interface;
858			hw-caps-temp-alert;
859		};
860
861		usb3: omap_dwc3@4a020000 {
862			compatible = "ti,dwc3";
863			ti,hwmods = "usb_otg_ss";
864			reg = <0x4a020000 0x10000>;
865			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
866			#address-cells = <1>;
867			#size-cells = <1>;
868			utmi-mode = <2>;
869			ranges;
870			dwc3: dwc3@4a030000 {
871				compatible = "snps,dwc3";
872				reg = <0x4a030000 0x10000>;
873				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
874					     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
875					     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
876				interrupt-names = "peripheral",
877						  "host",
878						  "otg";
879				phys = <&usb2_phy>, <&usb3_phy>;
880				phy-names = "usb2-phy", "usb3-phy";
881				dr_mode = "peripheral";
882			};
883		};
884
885		ocp2scp@4a080000 {
886			compatible = "ti,omap-ocp2scp";
887			#address-cells = <1>;
888			#size-cells = <1>;
889			reg = <0x4a080000 0x20>;
890			ranges;
891			ti,hwmods = "ocp2scp1";
892			usb2_phy: usb2phy@4a084000 {
893				compatible = "ti,omap-usb2";
894				reg = <0x4a084000 0x7c>;
895				syscon-phy-power = <&scm_conf 0x300>;
896				clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
897				clock-names = "wkupclk", "refclk";
898				#phy-cells = <0>;
899			};
900
901			usb3_phy: usb3phy@4a084400 {
902				compatible = "ti,omap-usb3";
903				reg = <0x4a084400 0x80>,
904				      <0x4a084800 0x64>,
905				      <0x4a084c00 0x40>;
906				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
907				syscon-phy-power = <&scm_conf 0x370>;
908				clocks = <&usb_phy_cm_clk32k>,
909					 <&sys_clkin>,
910					 <&usb_otg_ss_refclk960m>;
911				clock-names =	"wkupclk",
912						"sysclk",
913						"refclk";
914				#phy-cells = <0>;
915			};
916		};
917
918		usbhstll: usbhstll@4a062000 {
919			compatible = "ti,usbhs-tll";
920			reg = <0x4a062000 0x1000>;
921			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
922			ti,hwmods = "usb_tll_hs";
923		};
924
925		usbhshost: usbhshost@4a064000 {
926			compatible = "ti,usbhs-host";
927			reg = <0x4a064000 0x800>;
928			ti,hwmods = "usb_host_hs";
929			#address-cells = <1>;
930			#size-cells = <1>;
931			ranges;
932			clocks = <&l3init_60m_fclk>,
933				 <&xclk60mhsp1_ck>,
934				 <&xclk60mhsp2_ck>;
935			clock-names = "refclk_60m_int",
936				      "refclk_60m_ext_p1",
937				      "refclk_60m_ext_p2";
938
939			usbhsohci: ohci@4a064800 {
940				compatible = "ti,ohci-omap3";
941				reg = <0x4a064800 0x400>;
942				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
943			};
944
945			usbhsehci: ehci@4a064c00 {
946				compatible = "ti,ehci-omap";
947				reg = <0x4a064c00 0x400>;
948				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
949			};
950		};
951
952		bandgap: bandgap@4a0021e0 {
953			reg = <0x4a0021e0 0xc
954			       0x4a00232c 0xc
955			       0x4a002380 0x2c
956			       0x4a0023C0 0x3c>;
957			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
958			compatible = "ti,omap5430-bandgap";
959
960			#thermal-sensor-cells = <1>;
961		};
962
963		/* OCP2SCP3 */
964		ocp2scp@4a090000 {
965			compatible = "ti,omap-ocp2scp";
966			#address-cells = <1>;
967			#size-cells = <1>;
968			reg = <0x4a090000 0x20>;
969			ranges;
970			ti,hwmods = "ocp2scp3";
971			sata_phy: phy@4a096000 {
972				compatible = "ti,phy-pipe3-sata";
973				reg = <0x4A096000 0x80>, /* phy_rx */
974				      <0x4A096400 0x64>, /* phy_tx */
975				      <0x4A096800 0x40>; /* pll_ctrl */
976				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
977				syscon-phy-power = <&scm_conf 0x374>;
978				clocks = <&sys_clkin>, <&sata_ref_clk>;
979				clock-names = "sysclk", "refclk";
980				#phy-cells = <0>;
981			};
982		};
983
984		sata: sata@4a141100 {
985			compatible = "snps,dwc-ahci";
986			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
987			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
988			phys = <&sata_phy>;
989			phy-names = "sata-phy";
990			clocks = <&sata_ref_clk>;
991			ti,hwmods = "sata";
992			ports-implemented = <0x1>;
993		};
994
995		dss: dss@58000000 {
996			compatible = "ti,omap5-dss";
997			reg = <0x58000000 0x80>;
998			status = "disabled";
999			ti,hwmods = "dss_core";
1000			clocks = <&dss_dss_clk>;
1001			clock-names = "fck";
1002			#address-cells = <1>;
1003			#size-cells = <1>;
1004			ranges;
1005
1006			dispc@58001000 {
1007				compatible = "ti,omap5-dispc";
1008				reg = <0x58001000 0x1000>;
1009				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1010				ti,hwmods = "dss_dispc";
1011				clocks = <&dss_dss_clk>;
1012				clock-names = "fck";
1013			};
1014
1015			rfbi: encoder@58002000  {
1016				compatible = "ti,omap5-rfbi";
1017				reg = <0x58002000 0x100>;
1018				status = "disabled";
1019				ti,hwmods = "dss_rfbi";
1020				clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1021				clock-names = "fck", "ick";
1022			};
1023
1024			dsi1: encoder@58004000 {
1025				compatible = "ti,omap5-dsi";
1026				reg = <0x58004000 0x200>,
1027				      <0x58004200 0x40>,
1028				      <0x58004300 0x40>;
1029				reg-names = "proto", "phy", "pll";
1030				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1031				status = "disabled";
1032				ti,hwmods = "dss_dsi1";
1033				clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1034				clock-names = "fck", "sys_clk";
1035			};
1036
1037			dsi2: encoder@58005000 {
1038				compatible = "ti,omap5-dsi";
1039				reg = <0x58009000 0x200>,
1040				      <0x58009200 0x40>,
1041				      <0x58009300 0x40>;
1042				reg-names = "proto", "phy", "pll";
1043				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1044				status = "disabled";
1045				ti,hwmods = "dss_dsi2";
1046				clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1047				clock-names = "fck", "sys_clk";
1048			};
1049
1050			hdmi: encoder@58060000 {
1051				compatible = "ti,omap5-hdmi";
1052				reg = <0x58040000 0x200>,
1053				      <0x58040200 0x80>,
1054				      <0x58040300 0x80>,
1055				      <0x58060000 0x19000>;
1056				reg-names = "wp", "pll", "phy", "core";
1057				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1058				status = "disabled";
1059				ti,hwmods = "dss_hdmi";
1060				clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1061				clock-names = "fck", "sys_clk";
1062				dmas = <&sdma 76>;
1063				dma-names = "audio_tx";
1064			};
1065		};
1066
1067		abb_mpu: regulator-abb-mpu {
1068			compatible = "ti,abb-v2";
1069			regulator-name = "abb_mpu";
1070			#address-cells = <0>;
1071			#size-cells = <0>;
1072			clocks = <&sys_clkin>;
1073			ti,settling-time = <50>;
1074			ti,clock-cycles = <16>;
1075
1076			reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1077			      <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1078			reg-names = "base-address", "int-address",
1079				    "efuse-address", "ldo-address";
1080			ti,tranxdone-status-mask = <0x80>;
1081			/* LDOVBBMPU_MUX_CTRL */
1082			ti,ldovbb-override-mask = <0x400>;
1083			/* LDOVBBMPU_VSET_OUT */
1084			ti,ldovbb-vset-mask = <0x1F>;
1085
1086			/*
1087			 * NOTE: only FBB mode used but actual vset will
1088			 * determine final biasing
1089			 */
1090			ti,abb_info = <
1091			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
1092			1060000		0	0x0	0 0x02000000 0x01F00000
1093			1250000		0	0x4	0 0x02000000 0x01F00000
1094			>;
1095		};
1096
1097		abb_mm: regulator-abb-mm {
1098			compatible = "ti,abb-v2";
1099			regulator-name = "abb_mm";
1100			#address-cells = <0>;
1101			#size-cells = <0>;
1102			clocks = <&sys_clkin>;
1103			ti,settling-time = <50>;
1104			ti,clock-cycles = <16>;
1105
1106			reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1107			      <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1108			reg-names = "base-address", "int-address",
1109				    "efuse-address", "ldo-address";
1110			ti,tranxdone-status-mask = <0x80000000>;
1111			/* LDOVBBMM_MUX_CTRL */
1112			ti,ldovbb-override-mask = <0x400>;
1113			/* LDOVBBMM_VSET_OUT */
1114			ti,ldovbb-vset-mask = <0x1F>;
1115
1116			/*
1117			 * NOTE: only FBB mode used but actual vset will
1118			 * determine final biasing
1119			 */
1120			ti,abb_info = <
1121			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
1122			1025000		0	0x0	0 0x02000000 0x01F00000
1123			1120000		0	0x4	0 0x02000000 0x01F00000
1124			>;
1125		};
1126	};
1127};
1128
1129&cpu_thermal {
1130	polling-delay = <500>; /* milliseconds */
1131	coefficients = <65 (-1791)>;
1132};
1133
1134/include/ "omap54xx-clocks.dtsi"
1135
1136&gpu_thermal {
1137	coefficients = <117 (-2992)>;
1138};
1139
1140&core_thermal {
1141	coefficients = <0 2000>;
1142};
1143