1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include "skeleton.dtsi" 5#include <dt-bindings/clock/qcom,gcc-msm8960.h> 6#include <dt-bindings/reset/qcom,gcc-msm8960.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8960.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/soc/qcom,gsbi.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12/ { 13 model = "Qualcomm APQ8064"; 14 compatible = "qcom,apq8064"; 15 interrupt-parent = <&intc>; 16 17 reserved-memory { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 ranges; 21 22 smem_region: smem@80000000 { 23 reg = <0x80000000 0x200000>; 24 no-map; 25 }; 26 27 wcnss_mem: wcnss@8f000000 { 28 reg = <0x8f000000 0x700000>; 29 no-map; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 CPU0: cpu@0 { 38 compatible = "qcom,krait"; 39 enable-method = "qcom,kpss-acc-v1"; 40 device_type = "cpu"; 41 reg = <0>; 42 next-level-cache = <&L2>; 43 qcom,acc = <&acc0>; 44 qcom,saw = <&saw0>; 45 cpu-idle-states = <&CPU_SPC>; 46 }; 47 48 CPU1: cpu@1 { 49 compatible = "qcom,krait"; 50 enable-method = "qcom,kpss-acc-v1"; 51 device_type = "cpu"; 52 reg = <1>; 53 next-level-cache = <&L2>; 54 qcom,acc = <&acc1>; 55 qcom,saw = <&saw1>; 56 cpu-idle-states = <&CPU_SPC>; 57 }; 58 59 CPU2: cpu@2 { 60 compatible = "qcom,krait"; 61 enable-method = "qcom,kpss-acc-v1"; 62 device_type = "cpu"; 63 reg = <2>; 64 next-level-cache = <&L2>; 65 qcom,acc = <&acc2>; 66 qcom,saw = <&saw2>; 67 cpu-idle-states = <&CPU_SPC>; 68 }; 69 70 CPU3: cpu@3 { 71 compatible = "qcom,krait"; 72 enable-method = "qcom,kpss-acc-v1"; 73 device_type = "cpu"; 74 reg = <3>; 75 next-level-cache = <&L2>; 76 qcom,acc = <&acc3>; 77 qcom,saw = <&saw3>; 78 cpu-idle-states = <&CPU_SPC>; 79 }; 80 81 L2: l2-cache { 82 compatible = "cache"; 83 cache-level = <2>; 84 }; 85 86 idle-states { 87 CPU_SPC: spc { 88 compatible = "qcom,idle-state-spc", 89 "arm,idle-state"; 90 entry-latency-us = <400>; 91 exit-latency-us = <900>; 92 min-residency-us = <3000>; 93 }; 94 }; 95 }; 96 97 thermal-zones { 98 cpu-thermal0 { 99 polling-delay-passive = <250>; 100 polling-delay = <1000>; 101 102 thermal-sensors = <&gcc 7>; 103 coefficients = <1199 0>; 104 105 trips { 106 cpu_alert0: trip0 { 107 temperature = <75000>; 108 hysteresis = <2000>; 109 type = "passive"; 110 }; 111 cpu_crit0: trip1 { 112 temperature = <110000>; 113 hysteresis = <2000>; 114 type = "critical"; 115 }; 116 }; 117 }; 118 119 cpu-thermal1 { 120 polling-delay-passive = <250>; 121 polling-delay = <1000>; 122 123 thermal-sensors = <&gcc 8>; 124 coefficients = <1132 0>; 125 126 trips { 127 cpu_alert1: trip0 { 128 temperature = <75000>; 129 hysteresis = <2000>; 130 type = "passive"; 131 }; 132 cpu_crit1: trip1 { 133 temperature = <110000>; 134 hysteresis = <2000>; 135 type = "critical"; 136 }; 137 }; 138 }; 139 140 cpu-thermal2 { 141 polling-delay-passive = <250>; 142 polling-delay = <1000>; 143 144 thermal-sensors = <&gcc 9>; 145 coefficients = <1199 0>; 146 147 trips { 148 cpu_alert2: trip0 { 149 temperature = <75000>; 150 hysteresis = <2000>; 151 type = "passive"; 152 }; 153 cpu_crit2: trip1 { 154 temperature = <110000>; 155 hysteresis = <2000>; 156 type = "critical"; 157 }; 158 }; 159 }; 160 161 cpu-thermal3 { 162 polling-delay-passive = <250>; 163 polling-delay = <1000>; 164 165 thermal-sensors = <&gcc 10>; 166 coefficients = <1132 0>; 167 168 trips { 169 cpu_alert3: trip0 { 170 temperature = <75000>; 171 hysteresis = <2000>; 172 type = "passive"; 173 }; 174 cpu_crit3: trip1 { 175 temperature = <110000>; 176 hysteresis = <2000>; 177 type = "critical"; 178 }; 179 }; 180 }; 181 }; 182 183 cpu-pmu { 184 compatible = "qcom,krait-pmu"; 185 interrupts = <1 10 0x304>; 186 }; 187 188 clocks { 189 cxo_board: cxo_board { 190 compatible = "fixed-clock"; 191 #clock-cells = <0>; 192 clock-frequency = <19200000>; 193 }; 194 195 pxo_board { 196 compatible = "fixed-clock"; 197 #clock-cells = <0>; 198 clock-frequency = <27000000>; 199 }; 200 201 sleep_clk: sleep_clk { 202 compatible = "fixed-clock"; 203 #clock-cells = <0>; 204 clock-frequency = <32768>; 205 }; 206 }; 207 208 sfpb_mutex: hwmutex { 209 compatible = "qcom,sfpb-mutex"; 210 syscon = <&sfpb_wrapper_mutex 0x604 0x4>; 211 #hwlock-cells = <1>; 212 }; 213 214 smem { 215 compatible = "qcom,smem"; 216 memory-region = <&smem_region>; 217 218 hwlocks = <&sfpb_mutex 3>; 219 }; 220 221 smd { 222 compatible = "qcom,smd"; 223 224 modem@0 { 225 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; 226 227 qcom,ipc = <&l2cc 8 3>; 228 qcom,smd-edge = <0>; 229 230 status = "disabled"; 231 }; 232 233 q6@1 { 234 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; 235 236 qcom,ipc = <&l2cc 8 15>; 237 qcom,smd-edge = <1>; 238 239 status = "disabled"; 240 }; 241 242 dsps@3 { 243 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; 244 245 qcom,ipc = <&sps_sic_non_secure 0x4080 0>; 246 qcom,smd-edge = <3>; 247 248 status = "disabled"; 249 }; 250 251 riva@6 { 252 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; 253 254 qcom,ipc = <&l2cc 8 25>; 255 qcom,smd-edge = <6>; 256 257 status = "disabled"; 258 }; 259 }; 260 261 smsm { 262 compatible = "qcom,smsm"; 263 264 #address-cells = <1>; 265 #size-cells = <0>; 266 267 qcom,ipc-1 = <&l2cc 8 4>; 268 qcom,ipc-2 = <&l2cc 8 14>; 269 qcom,ipc-3 = <&l2cc 8 23>; 270 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; 271 272 apps_smsm: apps@0 { 273 reg = <0>; 274 #qcom,smem-state-cells = <1>; 275 }; 276 277 modem_smsm: modem@1 { 278 reg = <1>; 279 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; 280 281 interrupt-controller; 282 #interrupt-cells = <2>; 283 }; 284 285 q6_smsm: q6@2 { 286 reg = <2>; 287 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; 288 289 interrupt-controller; 290 #interrupt-cells = <2>; 291 }; 292 293 wcnss_smsm: wcnss@3 { 294 reg = <3>; 295 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; 296 297 interrupt-controller; 298 #interrupt-cells = <2>; 299 }; 300 301 dsps_smsm: dsps@4 { 302 reg = <4>; 303 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; 304 305 interrupt-controller; 306 #interrupt-cells = <2>; 307 }; 308 }; 309 310 firmware { 311 scm { 312 compatible = "qcom,scm-apq8064"; 313 314 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; 315 clock-names = "core"; 316 }; 317 }; 318 319 soc: soc { 320 #address-cells = <1>; 321 #size-cells = <1>; 322 ranges; 323 compatible = "simple-bus"; 324 325 tlmm_pinmux: pinctrl@800000 { 326 compatible = "qcom,apq8064-pinctrl"; 327 reg = <0x800000 0x4000>; 328 329 gpio-controller; 330 #gpio-cells = <2>; 331 interrupt-controller; 332 #interrupt-cells = <2>; 333 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; 334 335 pinctrl-names = "default"; 336 pinctrl-0 = <&ps_hold>; 337 }; 338 339 sfpb_wrapper_mutex: syscon@1200000 { 340 compatible = "syscon"; 341 reg = <0x01200000 0x8000>; 342 }; 343 344 intc: interrupt-controller@2000000 { 345 compatible = "qcom,msm-qgic2"; 346 interrupt-controller; 347 #interrupt-cells = <3>; 348 reg = <0x02000000 0x1000>, 349 <0x02002000 0x1000>; 350 }; 351 352 timer@200a000 { 353 compatible = "qcom,kpss-timer", 354 "qcom,kpss-wdt-apq8064", "qcom,msm-timer"; 355 interrupts = <1 1 0x301>, 356 <1 2 0x301>, 357 <1 3 0x301>; 358 reg = <0x0200a000 0x100>; 359 clock-frequency = <27000000>, 360 <32768>; 361 cpu-offset = <0x80000>; 362 }; 363 364 acc0: clock-controller@2088000 { 365 compatible = "qcom,kpss-acc-v1"; 366 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 367 }; 368 369 acc1: clock-controller@2098000 { 370 compatible = "qcom,kpss-acc-v1"; 371 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 372 }; 373 374 acc2: clock-controller@20a8000 { 375 compatible = "qcom,kpss-acc-v1"; 376 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; 377 }; 378 379 acc3: clock-controller@20b8000 { 380 compatible = "qcom,kpss-acc-v1"; 381 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; 382 }; 383 384 saw0: power-controller@2089000 { 385 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 386 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 387 regulator; 388 }; 389 390 saw1: power-controller@2099000 { 391 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 392 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 393 regulator; 394 }; 395 396 saw2: power-controller@20a9000 { 397 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 398 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; 399 regulator; 400 }; 401 402 saw3: power-controller@20b9000 { 403 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 404 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; 405 regulator; 406 }; 407 408 sps_sic_non_secure: sps-sic-non-secure@12100000 { 409 compatible = "syscon"; 410 reg = <0x12100000 0x10000>; 411 }; 412 413 gsbi1: gsbi@12440000 { 414 status = "disabled"; 415 compatible = "qcom,gsbi-v1.0.0"; 416 cell-index = <1>; 417 reg = <0x12440000 0x100>; 418 clocks = <&gcc GSBI1_H_CLK>; 419 clock-names = "iface"; 420 #address-cells = <1>; 421 #size-cells = <1>; 422 ranges; 423 424 syscon-tcsr = <&tcsr>; 425 426 gsbi1_serial: serial@12450000 { 427 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 428 reg = <0x12450000 0x100>, 429 <0x12400000 0x03>; 430 interrupts = <0 193 0x0>; 431 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 432 clock-names = "core", "iface"; 433 status = "disabled"; 434 }; 435 436 gsbi1_i2c: i2c@12460000 { 437 compatible = "qcom,i2c-qup-v1.1.1"; 438 pinctrl-0 = <&i2c1_pins>; 439 pinctrl-1 = <&i2c1_pins_sleep>; 440 pinctrl-names = "default", "sleep"; 441 reg = <0x12460000 0x1000>; 442 interrupts = <0 194 IRQ_TYPE_NONE>; 443 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 444 clock-names = "core", "iface"; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 }; 448 449 }; 450 451 gsbi2: gsbi@12480000 { 452 status = "disabled"; 453 compatible = "qcom,gsbi-v1.0.0"; 454 cell-index = <2>; 455 reg = <0x12480000 0x100>; 456 clocks = <&gcc GSBI2_H_CLK>; 457 clock-names = "iface"; 458 #address-cells = <1>; 459 #size-cells = <1>; 460 ranges; 461 462 syscon-tcsr = <&tcsr>; 463 464 gsbi2_i2c: i2c@124a0000 { 465 compatible = "qcom,i2c-qup-v1.1.1"; 466 reg = <0x124a0000 0x1000>; 467 pinctrl-0 = <&i2c2_pins>; 468 pinctrl-1 = <&i2c2_pins_sleep>; 469 pinctrl-names = "default", "sleep"; 470 interrupts = <0 196 IRQ_TYPE_NONE>; 471 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 472 clock-names = "core", "iface"; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 }; 476 }; 477 478 gsbi3: gsbi@16200000 { 479 status = "disabled"; 480 compatible = "qcom,gsbi-v1.0.0"; 481 cell-index = <3>; 482 reg = <0x16200000 0x100>; 483 clocks = <&gcc GSBI3_H_CLK>; 484 clock-names = "iface"; 485 #address-cells = <1>; 486 #size-cells = <1>; 487 ranges; 488 gsbi3_i2c: i2c@16280000 { 489 compatible = "qcom,i2c-qup-v1.1.1"; 490 pinctrl-0 = <&i2c3_pins>; 491 pinctrl-1 = <&i2c3_pins_sleep>; 492 pinctrl-names = "default", "sleep"; 493 reg = <0x16280000 0x1000>; 494 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; 495 clocks = <&gcc GSBI3_QUP_CLK>, 496 <&gcc GSBI3_H_CLK>; 497 clock-names = "core", "iface"; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 }; 501 }; 502 503 gsbi4: gsbi@16300000 { 504 status = "disabled"; 505 compatible = "qcom,gsbi-v1.0.0"; 506 cell-index = <4>; 507 reg = <0x16300000 0x03>; 508 clocks = <&gcc GSBI4_H_CLK>; 509 clock-names = "iface"; 510 #address-cells = <1>; 511 #size-cells = <1>; 512 ranges; 513 514 gsbi4_i2c: i2c@16380000 { 515 compatible = "qcom,i2c-qup-v1.1.1"; 516 pinctrl-0 = <&i2c4_pins>; 517 pinctrl-1 = <&i2c4_pins_sleep>; 518 pinctrl-names = "default", "sleep"; 519 reg = <0x16380000 0x1000>; 520 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>; 521 clocks = <&gcc GSBI4_QUP_CLK>, 522 <&gcc GSBI4_H_CLK>; 523 clock-names = "core", "iface"; 524 }; 525 }; 526 527 gsbi5: gsbi@1a200000 { 528 status = "disabled"; 529 compatible = "qcom,gsbi-v1.0.0"; 530 cell-index = <5>; 531 reg = <0x1a200000 0x03>; 532 clocks = <&gcc GSBI5_H_CLK>; 533 clock-names = "iface"; 534 #address-cells = <1>; 535 #size-cells = <1>; 536 ranges; 537 538 gsbi5_serial: serial@1a240000 { 539 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 540 reg = <0x1a240000 0x100>, 541 <0x1a200000 0x03>; 542 interrupts = <0 154 0x0>; 543 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 544 clock-names = "core", "iface"; 545 status = "disabled"; 546 }; 547 548 gsbi5_spi: spi@1a280000 { 549 compatible = "qcom,spi-qup-v1.1.1"; 550 reg = <0x1a280000 0x1000>; 551 interrupts = <0 155 0>; 552 pinctrl-0 = <&spi5_default>; 553 pinctrl-1 = <&spi5_sleep>; 554 pinctrl-names = "default", "sleep"; 555 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 556 clock-names = "core", "iface"; 557 status = "disabled"; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 }; 561 }; 562 563 gsbi6: gsbi@16500000 { 564 status = "disabled"; 565 compatible = "qcom,gsbi-v1.0.0"; 566 cell-index = <6>; 567 reg = <0x16500000 0x03>; 568 clocks = <&gcc GSBI6_H_CLK>; 569 clock-names = "iface"; 570 #address-cells = <1>; 571 #size-cells = <1>; 572 ranges; 573 574 gsbi6_serial: serial@16540000 { 575 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 576 reg = <0x16540000 0x100>, 577 <0x16500000 0x03>; 578 interrupts = <0 156 0x0>; 579 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 580 clock-names = "core", "iface"; 581 status = "disabled"; 582 }; 583 584 gsbi6_i2c: i2c@16580000 { 585 compatible = "qcom,i2c-qup-v1.1.1"; 586 pinctrl-0 = <&i2c6_pins>; 587 pinctrl-1 = <&i2c6_pins_sleep>; 588 pinctrl-names = "default", "sleep"; 589 reg = <0x16580000 0x1000>; 590 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; 591 clocks = <&gcc GSBI6_QUP_CLK>, 592 <&gcc GSBI6_H_CLK>; 593 clock-names = "core", "iface"; 594 }; 595 }; 596 597 gsbi7: gsbi@16600000 { 598 status = "disabled"; 599 compatible = "qcom,gsbi-v1.0.0"; 600 cell-index = <7>; 601 reg = <0x16600000 0x100>; 602 clocks = <&gcc GSBI7_H_CLK>; 603 clock-names = "iface"; 604 #address-cells = <1>; 605 #size-cells = <1>; 606 ranges; 607 syscon-tcsr = <&tcsr>; 608 609 gsbi7_serial: serial@16640000 { 610 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 611 reg = <0x16640000 0x1000>, 612 <0x16600000 0x1000>; 613 interrupts = <0 158 0x0>; 614 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 615 clock-names = "core", "iface"; 616 status = "disabled"; 617 }; 618 619 gsbi7_i2c: i2c@16680000 { 620 compatible = "qcom,i2c-qup-v1.1.1"; 621 pinctrl-0 = <&i2c7_pins>; 622 pinctrl-1 = <&i2c7_pins_sleep>; 623 pinctrl-names = "default", "sleep"; 624 reg = <0x16680000 0x1000>; 625 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; 626 clocks = <&gcc GSBI7_QUP_CLK>, 627 <&gcc GSBI7_H_CLK>; 628 clock-names = "core", "iface"; 629 status = "disabled"; 630 }; 631 }; 632 633 rng@1a500000 { 634 compatible = "qcom,prng"; 635 reg = <0x1a500000 0x200>; 636 clocks = <&gcc PRNG_CLK>; 637 clock-names = "core"; 638 }; 639 640 ssbi@c00000 { 641 compatible = "qcom,ssbi"; 642 reg = <0x00c00000 0x1000>; 643 qcom,controller-type = "pmic-arbiter"; 644 645 pm8821: pmic@1 { 646 compatible = "qcom,pm8821"; 647 interrupt-parent = <&tlmm_pinmux>; 648 interrupts = <76 IRQ_TYPE_LEVEL_LOW>; 649 #interrupt-cells = <2>; 650 interrupt-controller; 651 #address-cells = <1>; 652 #size-cells = <0>; 653 654 pm8821_mpps: mpps@50 { 655 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp"; 656 reg = <0x50>; 657 interrupts = <24 IRQ_TYPE_NONE>, 658 <25 IRQ_TYPE_NONE>, 659 <26 IRQ_TYPE_NONE>, 660 <27 IRQ_TYPE_NONE>; 661 gpio-controller; 662 #gpio-cells = <2>; 663 }; 664 }; 665 }; 666 667 qcom,ssbi@500000 { 668 compatible = "qcom,ssbi"; 669 reg = <0x00500000 0x1000>; 670 qcom,controller-type = "pmic-arbiter"; 671 672 pmicintc: pmic@0 { 673 compatible = "qcom,pm8921"; 674 interrupt-parent = <&tlmm_pinmux>; 675 interrupts = <74 8>; 676 #interrupt-cells = <2>; 677 interrupt-controller; 678 #address-cells = <1>; 679 #size-cells = <0>; 680 681 pm8921_gpio: gpio@150 { 682 683 compatible = "qcom,pm8921-gpio", 684 "qcom,ssbi-gpio"; 685 reg = <0x150>; 686 interrupts = <192 IRQ_TYPE_NONE>, 687 <193 IRQ_TYPE_NONE>, 688 <194 IRQ_TYPE_NONE>, 689 <195 IRQ_TYPE_NONE>, 690 <196 IRQ_TYPE_NONE>, 691 <197 IRQ_TYPE_NONE>, 692 <198 IRQ_TYPE_NONE>, 693 <199 IRQ_TYPE_NONE>, 694 <200 IRQ_TYPE_NONE>, 695 <201 IRQ_TYPE_NONE>, 696 <202 IRQ_TYPE_NONE>, 697 <203 IRQ_TYPE_NONE>, 698 <204 IRQ_TYPE_NONE>, 699 <205 IRQ_TYPE_NONE>, 700 <206 IRQ_TYPE_NONE>, 701 <207 IRQ_TYPE_NONE>, 702 <208 IRQ_TYPE_NONE>, 703 <209 IRQ_TYPE_NONE>, 704 <210 IRQ_TYPE_NONE>, 705 <211 IRQ_TYPE_NONE>, 706 <212 IRQ_TYPE_NONE>, 707 <213 IRQ_TYPE_NONE>, 708 <214 IRQ_TYPE_NONE>, 709 <215 IRQ_TYPE_NONE>, 710 <216 IRQ_TYPE_NONE>, 711 <217 IRQ_TYPE_NONE>, 712 <218 IRQ_TYPE_NONE>, 713 <219 IRQ_TYPE_NONE>, 714 <220 IRQ_TYPE_NONE>, 715 <221 IRQ_TYPE_NONE>, 716 <222 IRQ_TYPE_NONE>, 717 <223 IRQ_TYPE_NONE>, 718 <224 IRQ_TYPE_NONE>, 719 <225 IRQ_TYPE_NONE>, 720 <226 IRQ_TYPE_NONE>, 721 <227 IRQ_TYPE_NONE>, 722 <228 IRQ_TYPE_NONE>, 723 <229 IRQ_TYPE_NONE>, 724 <230 IRQ_TYPE_NONE>, 725 <231 IRQ_TYPE_NONE>, 726 <232 IRQ_TYPE_NONE>, 727 <233 IRQ_TYPE_NONE>, 728 <234 IRQ_TYPE_NONE>, 729 <235 IRQ_TYPE_NONE>; 730 gpio-controller; 731 #gpio-cells = <2>; 732 733 }; 734 735 pm8921_mpps: mpps@50 { 736 compatible = "qcom,pm8921-mpp", 737 "qcom,ssbi-mpp"; 738 reg = <0x50>; 739 gpio-controller; 740 #gpio-cells = <2>; 741 interrupts = 742 <128 IRQ_TYPE_NONE>, 743 <129 IRQ_TYPE_NONE>, 744 <130 IRQ_TYPE_NONE>, 745 <131 IRQ_TYPE_NONE>, 746 <132 IRQ_TYPE_NONE>, 747 <133 IRQ_TYPE_NONE>, 748 <134 IRQ_TYPE_NONE>, 749 <135 IRQ_TYPE_NONE>, 750 <136 IRQ_TYPE_NONE>, 751 <137 IRQ_TYPE_NONE>, 752 <138 IRQ_TYPE_NONE>, 753 <139 IRQ_TYPE_NONE>; 754 }; 755 756 rtc@11d { 757 compatible = "qcom,pm8921-rtc"; 758 interrupt-parent = <&pmicintc>; 759 interrupts = <39 1>; 760 reg = <0x11d>; 761 allow-set-time; 762 }; 763 764 pwrkey@1c { 765 compatible = "qcom,pm8921-pwrkey"; 766 reg = <0x1c>; 767 interrupt-parent = <&pmicintc>; 768 interrupts = <50 1>, <51 1>; 769 debounce = <15625>; 770 pull-up; 771 }; 772 }; 773 }; 774 775 qfprom: qfprom@700000 { 776 compatible = "qcom,qfprom"; 777 reg = <0x00700000 0x1000>; 778 #address-cells = <1>; 779 #size-cells = <1>; 780 ranges; 781 tsens_calib: calib { 782 reg = <0x404 0x10>; 783 }; 784 tsens_backup: backup_calib { 785 reg = <0x414 0x10>; 786 }; 787 }; 788 789 gcc: clock-controller@900000 { 790 compatible = "qcom,gcc-apq8064"; 791 reg = <0x00900000 0x4000>; 792 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 793 nvmem-cell-names = "calib", "calib_backup"; 794 #clock-cells = <1>; 795 #reset-cells = <1>; 796 #thermal-sensor-cells = <1>; 797 }; 798 799 lcc: clock-controller@28000000 { 800 compatible = "qcom,lcc-apq8064"; 801 reg = <0x28000000 0x1000>; 802 #clock-cells = <1>; 803 #reset-cells = <1>; 804 }; 805 806 mmcc: clock-controller@4000000 { 807 compatible = "qcom,mmcc-apq8064"; 808 reg = <0x4000000 0x1000>; 809 #clock-cells = <1>; 810 #reset-cells = <1>; 811 }; 812 813 l2cc: clock-controller@2011000 { 814 compatible = "syscon"; 815 reg = <0x2011000 0x1000>; 816 }; 817 818 rpm@108000 { 819 compatible = "qcom,rpm-apq8064"; 820 reg = <0x108000 0x1000>; 821 qcom,ipc = <&l2cc 0x8 2>; 822 823 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 824 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 825 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 826 interrupt-names = "ack", "err", "wakeup"; 827 828 rpmcc: clock-controller { 829 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; 830 #clock-cells = <1>; 831 }; 832 833 regulators { 834 compatible = "qcom,rpm-pm8921-regulators"; 835 836 pm8921_s1: s1 {}; 837 pm8921_s2: s2 {}; 838 pm8921_s3: s3 {}; 839 pm8921_s4: s4 {}; 840 pm8921_s7: s7 {}; 841 pm8921_s8: s8 {}; 842 843 pm8921_l1: l1 {}; 844 pm8921_l2: l2 {}; 845 pm8921_l3: l3 {}; 846 pm8921_l4: l4 {}; 847 pm8921_l5: l5 {}; 848 pm8921_l6: l6 {}; 849 pm8921_l7: l7 {}; 850 pm8921_l8: l8 {}; 851 pm8921_l9: l9 {}; 852 pm8921_l10: l10 {}; 853 pm8921_l11: l11 {}; 854 pm8921_l12: l12 {}; 855 pm8921_l14: l14 {}; 856 pm8921_l15: l15 {}; 857 pm8921_l16: l16 {}; 858 pm8921_l17: l17 {}; 859 pm8921_l18: l18 {}; 860 pm8921_l21: l21 {}; 861 pm8921_l22: l22 {}; 862 pm8921_l23: l23 {}; 863 pm8921_l24: l24 {}; 864 pm8921_l25: l25 {}; 865 pm8921_l26: l26 {}; 866 pm8921_l27: l27 {}; 867 pm8921_l28: l28 {}; 868 pm8921_l29: l29 {}; 869 870 pm8921_lvs1: lvs1 {}; 871 pm8921_lvs2: lvs2 {}; 872 pm8921_lvs3: lvs3 {}; 873 pm8921_lvs4: lvs4 {}; 874 pm8921_lvs5: lvs5 {}; 875 pm8921_lvs6: lvs6 {}; 876 pm8921_lvs7: lvs7 {}; 877 878 pm8921_usb_switch: usb-switch {}; 879 880 pm8921_hdmi_switch: hdmi-switch { 881 bias-pull-down; 882 }; 883 884 pm8921_ncp: ncp {}; 885 }; 886 }; 887 888 usb1: usb@12500000 { 889 compatible = "qcom,ci-hdrc"; 890 reg = <0x12500000 0x200>, 891 <0x12500200 0x200>; 892 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; 894 clock-names = "core", "iface"; 895 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; 896 assigned-clock-rates = <60000000>; 897 resets = <&gcc USB_HS1_RESET>; 898 reset-names = "core"; 899 phy_type = "ulpi"; 900 ahb-burst-config = <0>; 901 phys = <&usb_hs1_phy>; 902 phy-names = "usb-phy"; 903 status = "disabled"; 904 #reset-cells = <1>; 905 906 ulpi { 907 usb_hs1_phy: phy { 908 compatible = "qcom,usb-hs-phy-apq8064", 909 "qcom,usb-hs-phy"; 910 #phy-cells = <0>; 911 clocks = <&sleep_clk>, <&cxo_board>; 912 clock-names = "sleep", "ref"; 913 resets = <&usb1 0>; 914 reset-names = "por"; 915 }; 916 }; 917 }; 918 919 usb3: usb@12520000 { 920 compatible = "qcom,ci-hdrc"; 921 reg = <0x12520000 0x200>, 922 <0x12520200 0x200>; 923 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; 925 clock-names = "core", "iface"; 926 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; 927 assigned-clock-rates = <60000000>; 928 resets = <&gcc USB_HS3_RESET>; 929 reset-names = "core"; 930 phy_type = "ulpi"; 931 ahb-burst-config = <0>; 932 phys = <&usb_hs3_phy>; 933 phy-names = "usb-phy"; 934 status = "disabled"; 935 #reset-cells = <1>; 936 937 ulpi { 938 usb_hs3_phy: phy { 939 compatible = "qcom,usb-hs-phy-apq8064", 940 "qcom,usb-hs-phy"; 941 #phy-cells = <0>; 942 clocks = <&sleep_clk>, <&cxo_board>; 943 clock-names = "sleep", "ref"; 944 resets = <&usb3 0>; 945 reset-names = "por"; 946 }; 947 }; 948 }; 949 950 usb4: usb@12530000 { 951 compatible = "qcom,ci-hdrc"; 952 reg = <0x12530000 0x200>, 953 <0x12530200 0x200>; 954 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; 956 clock-names = "core", "iface"; 957 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; 958 assigned-clock-rates = <60000000>; 959 resets = <&gcc USB_HS4_RESET>; 960 reset-names = "core"; 961 phy_type = "ulpi"; 962 ahb-burst-config = <0>; 963 phys = <&usb_hs4_phy>; 964 phy-names = "usb-phy"; 965 status = "disabled"; 966 #reset-cells = <1>; 967 968 ulpi { 969 usb_hs4_phy: phy { 970 compatible = "qcom,usb-hs-phy-apq8064", 971 "qcom,usb-hs-phy"; 972 #phy-cells = <0>; 973 clocks = <&sleep_clk>, <&cxo_board>; 974 clock-names = "sleep", "ref"; 975 resets = <&usb4 0>; 976 reset-names = "por"; 977 }; 978 }; 979 }; 980 981 sata_phy0: phy@1b400000 { 982 compatible = "qcom,apq8064-sata-phy"; 983 status = "disabled"; 984 reg = <0x1b400000 0x200>; 985 reg-names = "phy_mem"; 986 clocks = <&gcc SATA_PHY_CFG_CLK>; 987 clock-names = "cfg"; 988 #phy-cells = <0>; 989 }; 990 991 sata0: sata@29000000 { 992 compatible = "qcom,apq8064-ahci", "generic-ahci"; 993 status = "disabled"; 994 reg = <0x29000000 0x180>; 995 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>; 996 997 clocks = <&gcc SFAB_SATA_S_H_CLK>, 998 <&gcc SATA_H_CLK>, 999 <&gcc SATA_A_CLK>, 1000 <&gcc SATA_RXOOB_CLK>, 1001 <&gcc SATA_PMALIVE_CLK>; 1002 clock-names = "slave_iface", 1003 "iface", 1004 "bus", 1005 "rxoob", 1006 "core_pmalive"; 1007 1008 assigned-clocks = <&gcc SATA_RXOOB_CLK>, 1009 <&gcc SATA_PMALIVE_CLK>; 1010 assigned-clock-rates = <100000000>, <100000000>; 1011 1012 phys = <&sata_phy0>; 1013 phy-names = "sata-phy"; 1014 ports-implemented = <0x1>; 1015 }; 1016 1017 /* Temporary fixed regulator */ 1018 sdcc1bam:dma@12402000{ 1019 compatible = "qcom,bam-v1.3.0"; 1020 reg = <0x12402000 0x8000>; 1021 interrupts = <0 98 0>; 1022 clocks = <&gcc SDC1_H_CLK>; 1023 clock-names = "bam_clk"; 1024 #dma-cells = <1>; 1025 qcom,ee = <0>; 1026 }; 1027 1028 sdcc3bam:dma@12182000{ 1029 compatible = "qcom,bam-v1.3.0"; 1030 reg = <0x12182000 0x8000>; 1031 interrupts = <0 96 0>; 1032 clocks = <&gcc SDC3_H_CLK>; 1033 clock-names = "bam_clk"; 1034 #dma-cells = <1>; 1035 qcom,ee = <0>; 1036 }; 1037 1038 sdcc4bam:dma@121c2000{ 1039 compatible = "qcom,bam-v1.3.0"; 1040 reg = <0x121c2000 0x8000>; 1041 interrupts = <0 95 0>; 1042 clocks = <&gcc SDC4_H_CLK>; 1043 clock-names = "bam_clk"; 1044 #dma-cells = <1>; 1045 qcom,ee = <0>; 1046 }; 1047 1048 amba { 1049 compatible = "simple-bus"; 1050 #address-cells = <1>; 1051 #size-cells = <1>; 1052 ranges; 1053 sdcc1: sdcc@12400000 { 1054 status = "disabled"; 1055 compatible = "arm,pl18x", "arm,primecell"; 1056 pinctrl-names = "default"; 1057 pinctrl-0 = <&sdcc1_pins>; 1058 arm,primecell-periphid = <0x00051180>; 1059 reg = <0x12400000 0x2000>; 1060 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1061 interrupt-names = "cmd_irq"; 1062 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 1063 clock-names = "mclk", "apb_pclk"; 1064 bus-width = <8>; 1065 max-frequency = <96000000>; 1066 non-removable; 1067 cap-sd-highspeed; 1068 cap-mmc-highspeed; 1069 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 1070 dma-names = "tx", "rx"; 1071 }; 1072 1073 sdcc3: sdcc@12180000 { 1074 compatible = "arm,pl18x", "arm,primecell"; 1075 arm,primecell-periphid = <0x00051180>; 1076 status = "disabled"; 1077 reg = <0x12180000 0x2000>; 1078 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1079 interrupt-names = "cmd_irq"; 1080 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 1081 clock-names = "mclk", "apb_pclk"; 1082 bus-width = <4>; 1083 cap-sd-highspeed; 1084 cap-mmc-highspeed; 1085 max-frequency = <192000000>; 1086 no-1-8-v; 1087 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 1088 dma-names = "tx", "rx"; 1089 }; 1090 1091 sdcc4: sdcc@121c0000 { 1092 compatible = "arm,pl18x", "arm,primecell"; 1093 arm,primecell-periphid = <0x00051180>; 1094 status = "disabled"; 1095 reg = <0x121c0000 0x2000>; 1096 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1097 interrupt-names = "cmd_irq"; 1098 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 1099 clock-names = "mclk", "apb_pclk"; 1100 bus-width = <4>; 1101 cap-sd-highspeed; 1102 cap-mmc-highspeed; 1103 max-frequency = <48000000>; 1104 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; 1105 dma-names = "tx", "rx"; 1106 pinctrl-names = "default"; 1107 pinctrl-0 = <&sdc4_gpios>; 1108 }; 1109 }; 1110 1111 tcsr: syscon@1a400000 { 1112 compatible = "qcom,tcsr-apq8064", "syscon"; 1113 reg = <0x1a400000 0x100>; 1114 }; 1115 1116 gpu: adreno-3xx@4300000 { 1117 compatible = "qcom,adreno-3xx"; 1118 reg = <0x04300000 0x20000>; 1119 reg-names = "kgsl_3d0_reg_memory"; 1120 interrupts = <GIC_SPI 80 0>; 1121 interrupt-names = "kgsl_3d0_irq"; 1122 clock-names = 1123 "core_clk", 1124 "iface_clk", 1125 "mem_clk", 1126 "mem_iface_clk"; 1127 clocks = 1128 <&mmcc GFX3D_CLK>, 1129 <&mmcc GFX3D_AHB_CLK>, 1130 <&mmcc GFX3D_AXI_CLK>, 1131 <&mmcc MMSS_IMEM_AHB_CLK>; 1132 qcom,chipid = <0x03020002>; 1133 1134 iommus = <&gfx3d 0 1135 &gfx3d 1 1136 &gfx3d 2 1137 &gfx3d 3 1138 &gfx3d 4 1139 &gfx3d 5 1140 &gfx3d 6 1141 &gfx3d 7 1142 &gfx3d 8 1143 &gfx3d 9 1144 &gfx3d 10 1145 &gfx3d 11 1146 &gfx3d 12 1147 &gfx3d 13 1148 &gfx3d 14 1149 &gfx3d 15 1150 &gfx3d 16 1151 &gfx3d 17 1152 &gfx3d 18 1153 &gfx3d 19 1154 &gfx3d 20 1155 &gfx3d 21 1156 &gfx3d 22 1157 &gfx3d 23 1158 &gfx3d 24 1159 &gfx3d 25 1160 &gfx3d 26 1161 &gfx3d 27 1162 &gfx3d 28 1163 &gfx3d 29 1164 &gfx3d 30 1165 &gfx3d 31 1166 &gfx3d1 0 1167 &gfx3d1 1 1168 &gfx3d1 2 1169 &gfx3d1 3 1170 &gfx3d1 4 1171 &gfx3d1 5 1172 &gfx3d1 6 1173 &gfx3d1 7 1174 &gfx3d1 8 1175 &gfx3d1 9 1176 &gfx3d1 10 1177 &gfx3d1 11 1178 &gfx3d1 12 1179 &gfx3d1 13 1180 &gfx3d1 14 1181 &gfx3d1 15 1182 &gfx3d1 16 1183 &gfx3d1 17 1184 &gfx3d1 18 1185 &gfx3d1 19 1186 &gfx3d1 20 1187 &gfx3d1 21 1188 &gfx3d1 22 1189 &gfx3d1 23 1190 &gfx3d1 24 1191 &gfx3d1 25 1192 &gfx3d1 26 1193 &gfx3d1 27 1194 &gfx3d1 28 1195 &gfx3d1 29 1196 &gfx3d1 30 1197 &gfx3d1 31>; 1198 1199 qcom,gpu-pwrlevels { 1200 compatible = "qcom,gpu-pwrlevels"; 1201 qcom,gpu-pwrlevel@0 { 1202 qcom,gpu-freq = <450000000>; 1203 }; 1204 qcom,gpu-pwrlevel@1 { 1205 qcom,gpu-freq = <27000000>; 1206 }; 1207 }; 1208 }; 1209 1210 mmss_sfpb: syscon@5700000 { 1211 compatible = "syscon"; 1212 reg = <0x5700000 0x70>; 1213 }; 1214 1215 dsi0: mdss_dsi@4700000 { 1216 compatible = "qcom,mdss-dsi-ctrl"; 1217 label = "MDSS DSI CTRL->0"; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 interrupts = <GIC_SPI 82 0>; 1221 reg = <0x04700000 0x200>; 1222 reg-names = "dsi_ctrl"; 1223 1224 clocks = <&mmcc DSI_M_AHB_CLK>, 1225 <&mmcc DSI_S_AHB_CLK>, 1226 <&mmcc AMP_AHB_CLK>, 1227 <&mmcc DSI_CLK>, 1228 <&mmcc DSI1_BYTE_CLK>, 1229 <&mmcc DSI_PIXEL_CLK>, 1230 <&mmcc DSI1_ESC_CLK>; 1231 clock-names = "iface_clk", "bus_clk", "core_mmss_clk", 1232 "src_clk", "byte_clk", "pixel_clk", 1233 "core_clk"; 1234 1235 assigned-clocks = <&mmcc DSI1_BYTE_SRC>, 1236 <&mmcc DSI1_ESC_SRC>, 1237 <&mmcc DSI_SRC>, 1238 <&mmcc DSI_PIXEL_SRC>; 1239 assigned-clock-parents = <&dsi0_phy 0>, 1240 <&dsi0_phy 0>, 1241 <&dsi0_phy 1>, 1242 <&dsi0_phy 1>; 1243 syscon-sfpb = <&mmss_sfpb>; 1244 phys = <&dsi0_phy>; 1245 ports { 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 1249 port@0 { 1250 reg = <0>; 1251 dsi0_in: endpoint { 1252 }; 1253 }; 1254 1255 port@1 { 1256 reg = <1>; 1257 dsi0_out: endpoint { 1258 }; 1259 }; 1260 }; 1261 }; 1262 1263 1264 dsi0_phy: dsi-phy@4700200 { 1265 compatible = "qcom,dsi-phy-28nm-8960"; 1266 #clock-cells = <1>; 1267 1268 reg = <0x04700200 0x100>, 1269 <0x04700300 0x200>, 1270 <0x04700500 0x5c>; 1271 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; 1272 clock-names = "iface_clk"; 1273 clocks = <&mmcc DSI_M_AHB_CLK>; 1274 }; 1275 1276 1277 mdp_port0: iommu@7500000 { 1278 compatible = "qcom,apq8064-iommu"; 1279 #iommu-cells = <1>; 1280 clock-names = 1281 "smmu_pclk", 1282 "iommu_clk"; 1283 clocks = 1284 <&mmcc SMMU_AHB_CLK>, 1285 <&mmcc MDP_AXI_CLK>; 1286 reg = <0x07500000 0x100000>; 1287 interrupts = 1288 <GIC_SPI 63 0>, 1289 <GIC_SPI 64 0>; 1290 qcom,ncb = <2>; 1291 }; 1292 1293 mdp_port1: iommu@7600000 { 1294 compatible = "qcom,apq8064-iommu"; 1295 #iommu-cells = <1>; 1296 clock-names = 1297 "smmu_pclk", 1298 "iommu_clk"; 1299 clocks = 1300 <&mmcc SMMU_AHB_CLK>, 1301 <&mmcc MDP_AXI_CLK>; 1302 reg = <0x07600000 0x100000>; 1303 interrupts = 1304 <GIC_SPI 61 0>, 1305 <GIC_SPI 62 0>; 1306 qcom,ncb = <2>; 1307 }; 1308 1309 gfx3d: iommu@7c00000 { 1310 compatible = "qcom,apq8064-iommu"; 1311 #iommu-cells = <1>; 1312 clock-names = 1313 "smmu_pclk", 1314 "iommu_clk"; 1315 clocks = 1316 <&mmcc SMMU_AHB_CLK>, 1317 <&mmcc GFX3D_AXI_CLK>; 1318 reg = <0x07c00000 0x100000>; 1319 interrupts = 1320 <GIC_SPI 69 0>, 1321 <GIC_SPI 70 0>; 1322 qcom,ncb = <3>; 1323 }; 1324 1325 gfx3d1: iommu@7d00000 { 1326 compatible = "qcom,apq8064-iommu"; 1327 #iommu-cells = <1>; 1328 clock-names = 1329 "smmu_pclk", 1330 "iommu_clk"; 1331 clocks = 1332 <&mmcc SMMU_AHB_CLK>, 1333 <&mmcc GFX3D_AXI_CLK>; 1334 reg = <0x07d00000 0x100000>; 1335 interrupts = 1336 <GIC_SPI 210 0>, 1337 <GIC_SPI 211 0>; 1338 qcom,ncb = <3>; 1339 }; 1340 1341 pcie: pci@1b500000 { 1342 compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; 1343 reg = <0x1b500000 0x1000 1344 0x1b502000 0x80 1345 0x1b600000 0x100 1346 0x0ff00000 0x100000>; 1347 reg-names = "dbi", "elbi", "parf", "config"; 1348 device_type = "pci"; 1349 linux,pci-domain = <0>; 1350 bus-range = <0x00 0xff>; 1351 num-lanes = <1>; 1352 #address-cells = <3>; 1353 #size-cells = <2>; 1354 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ 1355 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */ 1356 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; 1357 interrupt-names = "msi"; 1358 #interrupt-cells = <1>; 1359 interrupt-map-mask = <0 0 0 0x7>; 1360 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1361 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1362 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1363 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1364 clocks = <&gcc PCIE_A_CLK>, 1365 <&gcc PCIE_H_CLK>, 1366 <&gcc PCIE_PHY_REF_CLK>; 1367 clock-names = "core", "iface", "phy"; 1368 resets = <&gcc PCIE_ACLK_RESET>, 1369 <&gcc PCIE_HCLK_RESET>, 1370 <&gcc PCIE_POR_RESET>, 1371 <&gcc PCIE_PCI_RESET>, 1372 <&gcc PCIE_PHY_RESET>; 1373 reset-names = "axi", "ahb", "por", "pci", "phy"; 1374 status = "disabled"; 1375 }; 1376 1377 hdmi: hdmi-tx@4a00000 { 1378 compatible = "qcom,hdmi-tx-8960"; 1379 pinctrl-names = "default"; 1380 pinctrl-0 = <&hdmi_pinctrl>; 1381 reg = <0x04a00000 0x2f0>; 1382 reg-names = "core_physical"; 1383 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1384 clocks = <&mmcc HDMI_APP_CLK>, 1385 <&mmcc HDMI_M_AHB_CLK>, 1386 <&mmcc HDMI_S_AHB_CLK>; 1387 clock-names = "core_clk", 1388 "master_iface_clk", 1389 "slave_iface_clk"; 1390 1391 phys = <&hdmi_phy>; 1392 phy-names = "hdmi-phy"; 1393 1394 ports { 1395 #address-cells = <1>; 1396 #size-cells = <0>; 1397 1398 port@0 { 1399 reg = <0>; 1400 hdmi_in: endpoint { 1401 }; 1402 }; 1403 1404 port@1 { 1405 reg = <1>; 1406 hdmi_out: endpoint { 1407 }; 1408 }; 1409 }; 1410 }; 1411 1412 hdmi_phy: hdmi-phy@4a00400 { 1413 compatible = "qcom,hdmi-phy-8960"; 1414 reg = <0x4a00400 0x60>, 1415 <0x4a00500 0x100>; 1416 reg-names = "hdmi_phy", 1417 "hdmi_pll"; 1418 1419 clocks = <&mmcc HDMI_S_AHB_CLK>; 1420 clock-names = "slave_iface_clk"; 1421 }; 1422 1423 mdp: mdp@5100000 { 1424 compatible = "qcom,mdp4"; 1425 reg = <0x05100000 0xf0000>; 1426 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1427 clocks = <&mmcc MDP_CLK>, 1428 <&mmcc MDP_AHB_CLK>, 1429 <&mmcc MDP_AXI_CLK>, 1430 <&mmcc MDP_LUT_CLK>, 1431 <&mmcc HDMI_TV_CLK>, 1432 <&mmcc MDP_TV_CLK>; 1433 clock-names = "core_clk", 1434 "iface_clk", 1435 "bus_clk", 1436 "lut_clk", 1437 "hdmi_clk", 1438 "tv_clk"; 1439 1440 iommus = <&mdp_port0 0 1441 &mdp_port0 2 1442 &mdp_port1 0 1443 &mdp_port1 2>; 1444 1445 ports { 1446 #address-cells = <1>; 1447 #size-cells = <0>; 1448 1449 port@0 { 1450 reg = <0>; 1451 mdp_lvds_out: endpoint { 1452 }; 1453 }; 1454 1455 port@1 { 1456 reg = <1>; 1457 mdp_dsi1_out: endpoint { 1458 }; 1459 }; 1460 1461 port@2 { 1462 reg = <2>; 1463 mdp_dsi2_out: endpoint { 1464 }; 1465 }; 1466 1467 port@3 { 1468 reg = <3>; 1469 mdp_dtv_out: endpoint { 1470 }; 1471 }; 1472 }; 1473 }; 1474 1475 riva: riva-pil@3204000 { 1476 compatible = "qcom,riva-pil"; 1477 1478 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; 1479 reg-names = "ccu", "dxe", "pmu"; 1480 1481 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, 1482 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; 1483 interrupt-names = "wdog", "fatal"; 1484 1485 memory-region = <&wcnss_mem>; 1486 1487 vddcx-supply = <&pm8921_s3>; 1488 vddmx-supply = <&pm8921_l24>; 1489 vddpx-supply = <&pm8921_s4>; 1490 1491 status = "disabled"; 1492 1493 iris { 1494 compatible = "qcom,wcn3660"; 1495 1496 clocks = <&cxo_board>; 1497 clock-names = "xo"; 1498 1499 vddxo-supply = <&pm8921_l4>; 1500 vddrfa-supply = <&pm8921_s2>; 1501 vddpa-supply = <&pm8921_l10>; 1502 vdddig-supply = <&pm8921_lvs2>; 1503 }; 1504 1505 smd-edge { 1506 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; 1507 1508 qcom,ipc = <&l2cc 8 25>; 1509 qcom,smd-edge = <6>; 1510 1511 label = "riva"; 1512 1513 wcnss { 1514 compatible = "qcom,wcnss"; 1515 qcom,smd-channels = "WCNSS_CTRL"; 1516 1517 qcom,mmio = <&riva>; 1518 1519 bt { 1520 compatible = "qcom,wcnss-bt"; 1521 }; 1522 1523 wifi { 1524 compatible = "qcom,wcnss-wlan"; 1525 1526 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1528 interrupt-names = "tx", "rx"; 1529 1530 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1531 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1532 }; 1533 }; 1534 }; 1535 }; 1536 1537 etb@1a01000 { 1538 compatible = "coresight-etb10", "arm,primecell"; 1539 reg = <0x1a01000 0x1000>; 1540 1541 clocks = <&rpmcc RPM_QDSS_CLK>; 1542 clock-names = "apb_pclk"; 1543 1544 port { 1545 etb_in: endpoint { 1546 slave-mode; 1547 remote-endpoint = <&replicator_out0>; 1548 }; 1549 }; 1550 }; 1551 1552 tpiu@1a03000 { 1553 compatible = "arm,coresight-tpiu", "arm,primecell"; 1554 reg = <0x1a03000 0x1000>; 1555 1556 clocks = <&rpmcc RPM_QDSS_CLK>; 1557 clock-names = "apb_pclk"; 1558 1559 port { 1560 tpiu_in: endpoint { 1561 slave-mode; 1562 remote-endpoint = <&replicator_out1>; 1563 }; 1564 }; 1565 }; 1566 1567 replicator { 1568 compatible = "arm,coresight-replicator"; 1569 1570 clocks = <&rpmcc RPM_QDSS_CLK>; 1571 clock-names = "apb_pclk"; 1572 1573 ports { 1574 #address-cells = <1>; 1575 #size-cells = <0>; 1576 1577 port@0 { 1578 reg = <0>; 1579 replicator_out0: endpoint { 1580 remote-endpoint = <&etb_in>; 1581 }; 1582 }; 1583 port@1 { 1584 reg = <1>; 1585 replicator_out1: endpoint { 1586 remote-endpoint = <&tpiu_in>; 1587 }; 1588 }; 1589 port@2 { 1590 reg = <0>; 1591 replicator_in: endpoint { 1592 slave-mode; 1593 remote-endpoint = <&funnel_out>; 1594 }; 1595 }; 1596 }; 1597 }; 1598 1599 funnel@1a04000 { 1600 compatible = "arm,coresight-funnel", "arm,primecell"; 1601 reg = <0x1a04000 0x1000>; 1602 1603 clocks = <&rpmcc RPM_QDSS_CLK>; 1604 clock-names = "apb_pclk"; 1605 1606 ports { 1607 #address-cells = <1>; 1608 #size-cells = <0>; 1609 1610 /* 1611 * Not described input ports: 1612 * 2 - connected to STM component 1613 * 3 - not-connected 1614 * 6 - not-connected 1615 * 7 - not-connected 1616 */ 1617 port@0 { 1618 reg = <0>; 1619 funnel_in0: endpoint { 1620 slave-mode; 1621 remote-endpoint = <&etm0_out>; 1622 }; 1623 }; 1624 port@1 { 1625 reg = <1>; 1626 funnel_in1: endpoint { 1627 slave-mode; 1628 remote-endpoint = <&etm1_out>; 1629 }; 1630 }; 1631 port@4 { 1632 reg = <4>; 1633 funnel_in4: endpoint { 1634 slave-mode; 1635 remote-endpoint = <&etm2_out>; 1636 }; 1637 }; 1638 port@5 { 1639 reg = <5>; 1640 funnel_in5: endpoint { 1641 slave-mode; 1642 remote-endpoint = <&etm3_out>; 1643 }; 1644 }; 1645 port@8 { 1646 reg = <0>; 1647 funnel_out: endpoint { 1648 remote-endpoint = <&replicator_in>; 1649 }; 1650 }; 1651 }; 1652 }; 1653 1654 etm@1a1c000 { 1655 compatible = "arm,coresight-etm3x", "arm,primecell"; 1656 reg = <0x1a1c000 0x1000>; 1657 1658 clocks = <&rpmcc RPM_QDSS_CLK>; 1659 clock-names = "apb_pclk"; 1660 1661 cpu = <&CPU0>; 1662 1663 port { 1664 etm0_out: endpoint { 1665 remote-endpoint = <&funnel_in0>; 1666 }; 1667 }; 1668 }; 1669 1670 etm@1a1d000 { 1671 compatible = "arm,coresight-etm3x", "arm,primecell"; 1672 reg = <0x1a1d000 0x1000>; 1673 1674 clocks = <&rpmcc RPM_QDSS_CLK>; 1675 clock-names = "apb_pclk"; 1676 1677 cpu = <&CPU1>; 1678 1679 port { 1680 etm1_out: endpoint { 1681 remote-endpoint = <&funnel_in1>; 1682 }; 1683 }; 1684 }; 1685 1686 etm@1a1e000 { 1687 compatible = "arm,coresight-etm3x", "arm,primecell"; 1688 reg = <0x1a1e000 0x1000>; 1689 1690 clocks = <&rpmcc RPM_QDSS_CLK>; 1691 clock-names = "apb_pclk"; 1692 1693 cpu = <&CPU2>; 1694 1695 port { 1696 etm2_out: endpoint { 1697 remote-endpoint = <&funnel_in4>; 1698 }; 1699 }; 1700 }; 1701 1702 etm@1a1f000 { 1703 compatible = "arm,coresight-etm3x", "arm,primecell"; 1704 reg = <0x1a1f000 0x1000>; 1705 1706 clocks = <&rpmcc RPM_QDSS_CLK>; 1707 clock-names = "apb_pclk"; 1708 1709 cpu = <&CPU3>; 1710 1711 port { 1712 etm3_out: endpoint { 1713 remote-endpoint = <&funnel_in5>; 1714 }; 1715 }; 1716 }; 1717 }; 1718}; 1719#include "qcom-apq8064-pins.dtsi" 1720