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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4/include/ "skeleton.dtsi"
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/clock/qcom,gcc-msm8660.h>
9#include <dt-bindings/soc/qcom,gsbi.h>
10
11/ {
12	model = "Qualcomm MSM8660";
13	compatible = "qcom,msm8660";
14	interrupt-parent = <&intc>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu@0 {
21			compatible = "qcom,scorpion";
22			enable-method = "qcom,gcc-msm8660";
23			device_type = "cpu";
24			reg = <0>;
25			next-level-cache = <&L2>;
26		};
27
28		cpu@1 {
29			compatible = "qcom,scorpion";
30			enable-method = "qcom,gcc-msm8660";
31			device_type = "cpu";
32			reg = <1>;
33			next-level-cache = <&L2>;
34		};
35
36		L2: l2-cache {
37			compatible = "cache";
38			cache-level = <2>;
39		};
40	};
41
42	cpu-pmu {
43		compatible = "qcom,scorpion-mp-pmu";
44		interrupts = <1 9 0x304>;
45	};
46
47	clocks {
48		cxo_board {
49			compatible = "fixed-clock";
50			#clock-cells = <0>;
51			clock-frequency = <19200000>;
52		};
53
54		pxo_board {
55			compatible = "fixed-clock";
56			#clock-cells = <0>;
57			clock-frequency = <27000000>;
58		};
59
60		sleep_clk {
61			compatible = "fixed-clock";
62			#clock-cells = <0>;
63			clock-frequency = <32768>;
64		};
65	};
66
67	/*
68	 * These channels from the ADC are simply hardware monitors.
69	 * That is why the ADC is referred to as "HKADC" - HouseKeeping
70	 * ADC.
71	 */
72	iio-hwmon {
73		compatible = "iio-hwmon";
74		io-channels = <&xoadc 0x00 0x01>, /* Battery */
75			    <&xoadc 0x00 0x02>, /* DC in (charger) */
76			    <&xoadc 0x00 0x04>, /* VPH the main system voltage */
77			    <&xoadc 0x00 0x0b>, /* Die temperature */
78			    <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
79			    <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
80			    <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
81	};
82
83	soc: soc {
84		#address-cells = <1>;
85		#size-cells = <1>;
86		ranges;
87		compatible = "simple-bus";
88
89		intc: interrupt-controller@2080000 {
90			compatible = "qcom,msm-8660-qgic";
91			interrupt-controller;
92			#interrupt-cells = <3>;
93			reg = < 0x02080000 0x1000 >,
94			      < 0x02081000 0x1000 >;
95		};
96
97		timer@2000000 {
98			compatible = "qcom,scss-timer", "qcom,msm-timer";
99			interrupts = <1 0 0x301>,
100				     <1 1 0x301>,
101				     <1 2 0x301>;
102			reg = <0x02000000 0x100>;
103			clock-frequency = <27000000>,
104					  <32768>;
105			cpu-offset = <0x40000>;
106		};
107
108		tlmm: pinctrl@800000 {
109			compatible = "qcom,msm8660-pinctrl";
110			reg = <0x800000 0x4000>;
111
112			gpio-controller;
113			#gpio-cells = <2>;
114			interrupts = <0 16 0x4>;
115			interrupt-controller;
116			#interrupt-cells = <2>;
117
118		};
119
120		gcc: clock-controller@900000 {
121			compatible = "qcom,gcc-msm8660";
122			#clock-cells = <1>;
123			#reset-cells = <1>;
124			reg = <0x900000 0x4000>;
125		};
126
127
128		gsbi8: gsbi@19800000 {
129			compatible = "qcom,gsbi-v1.0.0";
130			cell-index = <12>;
131			reg = <0x19800000 0x100>;
132			clocks = <&gcc GSBI8_H_CLK>;
133			clock-names = "iface";
134			#address-cells = <1>;
135			#size-cells = <1>;
136			ranges;
137
138			syscon-tcsr = <&tcsr>;
139
140			gsbi8_i2c: i2c@19880000 {
141				compatible = "qcom,i2c-qup-v1.1.1";
142				reg = <0x19880000 0x1000>;
143				interrupts = <GIC_SPI 161 IRQ_TYPE_NONE>;
144				clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
145				clock-names = "core", "iface";
146				#address-cells = <1>;
147				#size-cells = <0>;
148				status = "disabled";
149			};
150		};
151
152		gsbi12: gsbi@19c00000 {
153			compatible = "qcom,gsbi-v1.0.0";
154			cell-index = <12>;
155			reg = <0x19c00000 0x100>;
156			clocks = <&gcc GSBI12_H_CLK>;
157			clock-names = "iface";
158			#address-cells = <1>;
159			#size-cells = <1>;
160			ranges;
161
162			syscon-tcsr = <&tcsr>;
163
164			gsbi12_serial: serial@19c40000 {
165				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
166				reg = <0x19c40000 0x1000>,
167				      <0x19c00000 0x1000>;
168				interrupts = <0 195 IRQ_TYPE_NONE>;
169				clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
170				clock-names = "core", "iface";
171				status = "disabled";
172			};
173
174			gsbi12_i2c: i2c@19c80000 {
175				compatible = "qcom,i2c-qup-v1.1.1";
176				reg = <0x19c80000 0x1000>;
177				interrupts = <0 196 IRQ_TYPE_NONE>;
178				clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
179				clock-names = "core", "iface";
180				#address-cells = <1>;
181				#size-cells = <0>;
182				status = "disabled";
183			};
184		};
185
186		external-bus@1a100000 {
187			compatible = "qcom,msm8660-ebi2";
188			#address-cells = <2>;
189			#size-cells = <1>;
190			ranges = <0 0x0 0x1a800000 0x00800000>,
191				 <1 0x0 0x1b000000 0x00800000>,
192				 <2 0x0 0x1b800000 0x00800000>,
193				 <3 0x0 0x1d000000 0x08000000>,
194				 <4 0x0 0x1c800000 0x00800000>,
195				 <5 0x0 0x1c000000 0x00800000>;
196			reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
197			reg-names = "ebi2", "xmem";
198			clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
199			clock-names = "ebi2x", "ebi2";
200			status = "disabled";
201		};
202
203		qcom,ssbi@500000 {
204			compatible = "qcom,ssbi";
205			reg = <0x500000 0x1000>;
206			qcom,controller-type = "pmic-arbiter";
207
208			pm8058: pmic@0 {
209				compatible = "qcom,pm8058";
210				interrupt-parent = <&tlmm>;
211				interrupts = <88 8>;
212				#interrupt-cells = <2>;
213				interrupt-controller;
214				#address-cells = <1>;
215				#size-cells = <0>;
216
217				pm8058_gpio: gpio@150 {
218					compatible = "qcom,pm8058-gpio",
219						     "qcom,ssbi-gpio";
220					reg = <0x150>;
221					interrupt-parent = <&pm8058>;
222					interrupts = <192 IRQ_TYPE_NONE>,
223						     <193 IRQ_TYPE_NONE>,
224						     <194 IRQ_TYPE_NONE>,
225						     <195 IRQ_TYPE_NONE>,
226						     <196 IRQ_TYPE_NONE>,
227						     <197 IRQ_TYPE_NONE>,
228						     <198 IRQ_TYPE_NONE>,
229						     <199 IRQ_TYPE_NONE>,
230						     <200 IRQ_TYPE_NONE>,
231						     <201 IRQ_TYPE_NONE>,
232						     <202 IRQ_TYPE_NONE>,
233						     <203 IRQ_TYPE_NONE>,
234						     <204 IRQ_TYPE_NONE>,
235						     <205 IRQ_TYPE_NONE>,
236						     <206 IRQ_TYPE_NONE>,
237						     <207 IRQ_TYPE_NONE>,
238						     <208 IRQ_TYPE_NONE>,
239						     <209 IRQ_TYPE_NONE>,
240						     <210 IRQ_TYPE_NONE>,
241						     <211 IRQ_TYPE_NONE>,
242						     <212 IRQ_TYPE_NONE>,
243						     <213 IRQ_TYPE_NONE>,
244						     <214 IRQ_TYPE_NONE>,
245						     <215 IRQ_TYPE_NONE>,
246						     <216 IRQ_TYPE_NONE>,
247						     <217 IRQ_TYPE_NONE>,
248						     <218 IRQ_TYPE_NONE>,
249						     <219 IRQ_TYPE_NONE>,
250						     <220 IRQ_TYPE_NONE>,
251						     <221 IRQ_TYPE_NONE>,
252						     <222 IRQ_TYPE_NONE>,
253						     <223 IRQ_TYPE_NONE>,
254						     <224 IRQ_TYPE_NONE>,
255						     <225 IRQ_TYPE_NONE>,
256						     <226 IRQ_TYPE_NONE>,
257						     <227 IRQ_TYPE_NONE>,
258						     <228 IRQ_TYPE_NONE>,
259						     <229 IRQ_TYPE_NONE>,
260						     <230 IRQ_TYPE_NONE>,
261						     <231 IRQ_TYPE_NONE>,
262						     <232 IRQ_TYPE_NONE>,
263						     <233 IRQ_TYPE_NONE>,
264						     <234 IRQ_TYPE_NONE>,
265						     <235 IRQ_TYPE_NONE>;
266					gpio-controller;
267					#gpio-cells = <2>;
268
269				};
270
271				pm8058_mpps: mpps@50 {
272					compatible = "qcom,pm8058-mpp",
273						     "qcom,ssbi-mpp";
274					reg = <0x50>;
275					gpio-controller;
276					#gpio-cells = <2>;
277					interrupt-parent = <&pm8058>;
278					interrupts =
279					<128 IRQ_TYPE_NONE>,
280					<129 IRQ_TYPE_NONE>,
281					<130 IRQ_TYPE_NONE>,
282					<131 IRQ_TYPE_NONE>,
283					<132 IRQ_TYPE_NONE>,
284					<133 IRQ_TYPE_NONE>,
285					<134 IRQ_TYPE_NONE>,
286					<135 IRQ_TYPE_NONE>,
287					<136 IRQ_TYPE_NONE>,
288					<137 IRQ_TYPE_NONE>,
289					<138 IRQ_TYPE_NONE>,
290					<139 IRQ_TYPE_NONE>;
291				};
292
293				pwrkey@1c {
294					compatible = "qcom,pm8058-pwrkey";
295					reg = <0x1c>;
296					interrupt-parent = <&pm8058>;
297					interrupts = <50 1>, <51 1>;
298					debounce = <15625>;
299					pull-up;
300				};
301
302				keypad@148 {
303					compatible = "qcom,pm8058-keypad";
304					reg = <0x148>;
305					interrupt-parent = <&pm8058>;
306					interrupts = <74 1>, <75 1>;
307					debounce = <15>;
308					scan-delay = <32>;
309					row-hold = <91500>;
310				};
311
312				xoadc: xoadc@197 {
313					compatible = "qcom,pm8058-adc";
314					reg = <0x197>;
315					interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
316					#address-cells = <2>;
317					#size-cells = <0>;
318					#io-channel-cells = <2>;
319
320					vcoin: adc-channel@00 {
321						reg = <0x00 0x00>;
322					};
323					vbat: adc-channel@01 {
324						reg = <0x00 0x01>;
325					};
326					dcin: adc-channel@02 {
327						reg = <0x00 0x02>;
328					};
329					ichg: adc-channel@03 {
330						reg = <0x00 0x03>;
331					};
332					vph_pwr: adc-channel@04 {
333						reg = <0x00 0x04>;
334					};
335					usb_vbus: adc-channel@0a {
336						reg = <0x00 0x0a>;
337					};
338					die_temp: adc-channel@0b {
339						reg = <0x00 0x0b>;
340					};
341					ref_625mv: adc-channel@0c {
342						reg = <0x00 0x0c>;
343					};
344					ref_1250mv: adc-channel@0d {
345						reg = <0x00 0x0d>;
346					};
347					ref_325mv: adc-channel@0e {
348						reg = <0x00 0x0e>;
349					};
350					ref_muxoff: adc-channel@0f {
351						reg = <0x00 0x0f>;
352					};
353				};
354
355				rtc@1e8 {
356					compatible = "qcom,pm8058-rtc";
357					reg = <0x1e8>;
358					interrupt-parent = <&pm8058>;
359					interrupts = <39 1>;
360					allow-set-time;
361				};
362
363				vibrator@4a {
364					compatible = "qcom,pm8058-vib";
365					reg = <0x4a>;
366				};
367			};
368		};
369
370		l2cc: clock-controller@2082000 {
371			compatible	= "syscon";
372			reg		= <0x02082000 0x1000>;
373		};
374
375		rpm: rpm@104000 {
376			compatible	= "qcom,rpm-msm8660";
377			reg		= <0x00104000 0x1000>;
378			qcom,ipc	= <&l2cc 0x8 2>;
379
380			interrupts	= <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
381					  <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
382					  <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
383			interrupt-names	= "ack", "err", "wakeup";
384			clocks = <&gcc RPM_MSG_RAM_H_CLK>;
385			clock-names = "ram";
386
387			rpmcc: clock-controller {
388				compatible	= "qcom,rpmcc-apq8660", "qcom,rpmcc";
389				#clock-cells = <1>;
390			};
391
392			pm8901-regulators {
393				compatible = "qcom,rpm-pm8901-regulators";
394
395				pm8901_l0: l0 {};
396				pm8901_l1: l1 {};
397				pm8901_l2: l2 {};
398				pm8901_l3: l3 {};
399				pm8901_l4: l4 {};
400				pm8901_l5: l5 {};
401				pm8901_l6: l6 {};
402
403				/* S0 and S1 Handled as SAW regulators by SPM */
404				pm8901_s2: s2 {};
405				pm8901_s3: s3 {};
406				pm8901_s4: s4 {};
407
408				pm8901_lvs0: lvs0 {};
409				pm8901_lvs1: lvs1 {};
410				pm8901_lvs2: lvs2 {};
411				pm8901_lvs3: lvs3 {};
412
413				pm8901_mvs: mvs {};
414			};
415
416			pm8058-regulators {
417				compatible = "qcom,rpm-pm8058-regulators";
418
419				pm8058_l0: l0 {};
420				pm8058_l1: l1 {};
421				pm8058_l2: l2 {};
422				pm8058_l3: l3 {};
423				pm8058_l4: l4 {};
424				pm8058_l5: l5 {};
425				pm8058_l6: l6 {};
426				pm8058_l7: l7 {};
427				pm8058_l8: l8 {};
428				pm8058_l9: l9 {};
429				pm8058_l10: l10 {};
430				pm8058_l11: l11 {};
431				pm8058_l12: l12 {};
432				pm8058_l13: l13 {};
433				pm8058_l14: l14 {};
434				pm8058_l15: l15 {};
435				pm8058_l16: l16 {};
436				pm8058_l17: l17 {};
437				pm8058_l18: l18 {};
438				pm8058_l19: l19 {};
439				pm8058_l20: l20 {};
440				pm8058_l21: l21 {};
441				pm8058_l22: l22 {};
442				pm8058_l23: l23 {};
443				pm8058_l24: l24 {};
444				pm8058_l25: l25 {};
445
446				pm8058_s0: s0 {};
447				pm8058_s1: s1 {};
448				pm8058_s2: s2 {};
449				pm8058_s3: s3 {};
450				pm8058_s4: s4 {};
451
452				pm8058_lvs0: lvs0 {};
453				pm8058_lvs1: lvs1 {};
454
455				pm8058_ncp: ncp {};
456			};
457		};
458
459		amba {
460			compatible = "simple-bus";
461			#address-cells = <1>;
462			#size-cells = <1>;
463			ranges;
464			sdcc1: sdcc@12400000 {
465				status		= "disabled";
466				compatible	= "arm,pl18x", "arm,primecell";
467				arm,primecell-periphid = <0x00051180>;
468				reg		= <0x12400000 0x8000>;
469				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
470				interrupt-names	= "cmd_irq";
471				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
472				clock-names	= "mclk", "apb_pclk";
473				bus-width	= <8>;
474				max-frequency	= <48000000>;
475				non-removable;
476				cap-sd-highspeed;
477				cap-mmc-highspeed;
478			};
479
480			sdcc2: sdcc@12140000 {
481				status		= "disabled";
482				compatible	= "arm,pl18x", "arm,primecell";
483				arm,primecell-periphid = <0x00051180>;
484				reg		= <0x12140000 0x8000>;
485				interrupts	= <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
486				interrupt-names	= "cmd_irq";
487				clocks		= <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
488				clock-names	= "mclk", "apb_pclk";
489				bus-width	= <8>;
490				max-frequency	= <48000000>;
491				cap-sd-highspeed;
492				cap-mmc-highspeed;
493			};
494
495			sdcc3: sdcc@12180000 {
496				compatible	= "arm,pl18x", "arm,primecell";
497				arm,primecell-periphid = <0x00051180>;
498				status		= "disabled";
499				reg		= <0x12180000 0x8000>;
500				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
501				interrupt-names	= "cmd_irq";
502				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
503				clock-names	= "mclk", "apb_pclk";
504				bus-width	= <4>;
505				cap-sd-highspeed;
506				cap-mmc-highspeed;
507				max-frequency	= <48000000>;
508				no-1-8-v;
509			};
510
511			sdcc4: sdcc@121c0000 {
512				compatible	= "arm,pl18x", "arm,primecell";
513				arm,primecell-periphid = <0x00051180>;
514				status		= "disabled";
515				reg		= <0x121c0000 0x8000>;
516				interrupts	= <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
517				interrupt-names	= "cmd_irq";
518				clocks		= <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
519				clock-names	= "mclk", "apb_pclk";
520				bus-width	= <4>;
521				max-frequency	= <48000000>;
522				cap-sd-highspeed;
523				cap-mmc-highspeed;
524			};
525
526			sdcc5: sdcc@12200000 {
527				compatible	= "arm,pl18x", "arm,primecell";
528				arm,primecell-periphid = <0x00051180>;
529				status		= "disabled";
530				reg		= <0x12200000 0x8000>;
531				interrupts	= <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
532				interrupt-names	= "cmd_irq";
533				clocks		= <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
534				clock-names	= "mclk", "apb_pclk";
535				bus-width	= <4>;
536				cap-sd-highspeed;
537				cap-mmc-highspeed;
538				max-frequency	= <48000000>;
539			};
540		};
541
542		tcsr: syscon@1a400000 {
543			compatible = "qcom,tcsr-msm8660", "syscon";
544			reg = <0x1a400000 0x100>;
545		};
546	};
547
548};
549