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1/*
2 * Device Tree Source for the RZ/A1H RSK board
3 *
4 * Copyright (C) 2016 Renesas Electronics
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2.  This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "r7s72100.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
15
16/ {
17	model = "RSKRZA1";
18	compatible = "renesas,rskrza1", "renesas,r7s72100";
19
20	aliases {
21		serial0 = &scif2;
22	};
23
24	chosen {
25		bootargs = "ignore_loglevel";
26		stdout-path = "serial0:115200n8";
27	};
28
29	memory@8000000 {
30		device_type = "memory";
31		reg = <0x08000000 0x02000000>;
32	};
33
34	lbsc {
35		#address-cells = <1>;
36		#size-cells = <1>;
37	};
38
39	leds {
40		status = "okay";
41		compatible = "gpio-leds";
42
43		led0 {
44			gpios = <&port7 1 GPIO_ACTIVE_LOW>;
45		};
46	};
47};
48
49&extal_clk {
50	clock-frequency = <13330000>;
51};
52
53&usb_x1_clk {
54	clock-frequency = <48000000>;
55};
56
57&rtc_x1_clk {
58	clock-frequency = <32768>;
59};
60
61&pinctrl {
62
63	/* Serial Console */
64	scif2_pins: serial2 {
65		pinmux = <RZA1_PINMUX(3, 0, 6)>,	/* TxD2 */
66			 <RZA1_PINMUX(3, 2, 4)>;	/* RxD2 */
67	};
68
69	/* Ethernet */
70	ether_pins: ether {
71		/* Ethernet on Ports 1,2,3,5 */
72		pinmux = <RZA1_PINMUX(1, 14, 4)>,	/* ET_COL   */
73			 <RZA1_PINMUX(5, 9, 2)>,	/* ET_MDC   */
74			 <RZA1_PINMUX(3, 3, 2)>,	/* ET_MDIO  */
75			 <RZA1_PINMUX(3, 4, 2)>,	/* ET_RXCLK */
76			 <RZA1_PINMUX(3, 5, 2)>,	/* ET_RXER  */
77			 <RZA1_PINMUX(3, 6, 2)>,	/* ET_RXDV  */
78			 <RZA1_PINMUX(2, 0, 2)>,	/* ET_TXCLK */
79			 <RZA1_PINMUX(2, 1, 2)>,	/* ET_TXER  */
80			 <RZA1_PINMUX(2, 2, 2)>,	/* ET_TXEN  */
81			 <RZA1_PINMUX(2, 3, 2)>,	/* ET_CRS   */
82			 <RZA1_PINMUX(2, 4, 2)>,	/* ET_TXD0  */
83			 <RZA1_PINMUX(2, 5, 2)>,	/* ET_TXD1  */
84			 <RZA1_PINMUX(2, 6, 2)>,	/* ET_TXD2  */
85			 <RZA1_PINMUX(2, 7, 2)>,	/* ET_TXD3  */
86			 <RZA1_PINMUX(2, 8, 2)>,	/* ET_RXD0  */
87			 <RZA1_PINMUX(2, 9, 2)>,	/* ET_RXD1  */
88			 <RZA1_PINMUX(2, 10, 2)>,	/* ET_RXD2  */
89			 <RZA1_PINMUX(2, 11, 2)>;	/* ET_RXD3  */
90	};
91
92	/* SDHI ch1 on CN1 */
93	sdhi1_pins: sdhi1 {
94		pinmux = <RZA1_PINMUX(3, 8, 7)>,	/* SD_CD_1 */
95			 <RZA1_PINMUX(3, 9, 7)>,	/* SD_WP_1 */
96			 <RZA1_PINMUX(3, 10, 7)>,	/* SD_D1_1 */
97			 <RZA1_PINMUX(3, 11, 7)>,	/* SD_D0_1 */
98			 <RZA1_PINMUX(3, 12, 7)>,	/* SD_CLK_1 */
99			 <RZA1_PINMUX(3, 13, 7)>,	/* SD_CMD_1 */
100			 <RZA1_PINMUX(3, 14, 7)>,	/* SD_D3_1 */
101			 <RZA1_PINMUX(3, 15, 7)>;	/* SD_D2_1 */
102	};
103};
104
105&mtu2 {
106	status = "okay";
107};
108
109&ether {
110	pinctrl-names = "default";
111	pinctrl-0 = <&ether_pins>;
112	status = "okay";
113	renesas,no-ether-link;
114	phy-handle = <&phy0>;
115	phy0: ethernet-phy@0 {
116		reg = <0>;
117	};
118};
119
120&sdhi1 {
121	pinctrl-names = "default";
122	pinctrl-0 = <&sdhi1_pins>;
123	bus-width = <4>;
124	status = "okay";
125};
126
127&ostm0 {
128	status = "okay";
129};
130
131&ostm1 {
132	status = "okay";
133};
134
135&rtc {
136	status = "okay";
137};
138
139&scif2 {
140	pinctrl-names = "default";
141	pinctrl-0 = <&scif2_pins>;
142	status = "okay";
143};
144