1/* 2 * Device Tree Source for the r8a73a4 SoC 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Magnus Damm 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12#include <dt-bindings/clock/r8a73a4-clock.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15 16/ { 17 compatible = "renesas,r8a73a4"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu0: cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a15"; 29 reg = <0>; 30 clock-frequency = <1500000000>; 31 power-domains = <&pd_a2sl>; 32 next-level-cache = <&L2_CA15>; 33 }; 34 35 L2_CA15: cache-controller-0 { 36 compatible = "cache"; 37 clocks = <&cpg_clocks R8A73A4_CLK_Z>; 38 power-domains = <&pd_a3sm>; 39 cache-unified; 40 cache-level = <2>; 41 }; 42 43 L2_CA7: cache-controller-1 { 44 compatible = "cache"; 45 clocks = <&cpg_clocks R8A73A4_CLK_Z2>; 46 power-domains = <&pd_a3km>; 47 cache-unified; 48 cache-level = <2>; 49 }; 50 }; 51 52 ptm { 53 compatible = "arm,coresight-etm3x"; 54 power-domains = <&pd_d4>; 55 }; 56 57 timer { 58 compatible = "arm,armv7-timer"; 59 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 60 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 61 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 62 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 63 }; 64 65 dbsc1: memory-controller@e6790000 { 66 compatible = "renesas,dbsc-r8a73a4"; 67 reg = <0 0xe6790000 0 0x10000>; 68 power-domains = <&pd_a3bc>; 69 }; 70 71 dbsc2: memory-controller@e67a0000 { 72 compatible = "renesas,dbsc-r8a73a4"; 73 reg = <0 0xe67a0000 0 0x10000>; 74 power-domains = <&pd_a3bc>; 75 }; 76 77 dmac: dma-multiplexer { 78 compatible = "renesas,shdma-mux"; 79 #dma-cells = <1>; 80 dma-channels = <20>; 81 dma-requests = <256>; 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 86 dma0: dma-controller@e6700020 { 87 compatible = "renesas,shdma-r8a73a4"; 88 reg = <0 0xe6700020 0 0x89e0>; 89 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 90 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 91 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 92 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 93 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 94 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 95 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 96 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 97 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 98 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 99 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 100 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 101 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 102 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 103 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 104 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 105 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 106 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 107 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 108 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 109 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 110 interrupt-names = "error", 111 "ch0", "ch1", "ch2", "ch3", 112 "ch4", "ch5", "ch6", "ch7", 113 "ch8", "ch9", "ch10", "ch11", 114 "ch12", "ch13", "ch14", "ch15", 115 "ch16", "ch17", "ch18", "ch19"; 116 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>; 117 power-domains = <&pd_a3sp>; 118 }; 119 }; 120 121 i2c5: i2c@e60b0000 { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 125 reg = <0 0xe60b0000 0 0x428>; 126 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 127 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; 128 power-domains = <&pd_a3sp>; 129 130 status = "disabled"; 131 }; 132 133 cmt1: timer@e6130000 { 134 compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; 135 reg = <0 0xe6130000 0 0x1004>; 136 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; 138 clock-names = "fck"; 139 power-domains = <&pd_c5>; 140 141 renesas,channels-mask = <0xff>; 142 143 status = "disabled"; 144 }; 145 146 irqc0: interrupt-controller@e61c0000 { 147 compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; 148 #interrupt-cells = <2>; 149 interrupt-controller; 150 reg = <0 0xe61c0000 0 0x200>; 151 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; 184 power-domains = <&pd_c4>; 185 }; 186 187 irqc1: interrupt-controller@e61c0200 { 188 compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; 189 #interrupt-cells = <2>; 190 interrupt-controller; 191 reg = <0 0xe61c0200 0 0x200>; 192 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; 219 power-domains = <&pd_c4>; 220 }; 221 222 pfc: pin-controller@e6050000 { 223 compatible = "renesas,pfc-r8a73a4"; 224 reg = <0 0xe6050000 0 0x9000>; 225 gpio-controller; 226 #gpio-cells = <2>; 227 gpio-ranges = 228 <&pfc 0 0 31>, <&pfc 32 32 9>, 229 <&pfc 64 64 22>, <&pfc 96 96 31>, 230 <&pfc 128 128 7>, <&pfc 160 160 19>, 231 <&pfc 192 192 31>, <&pfc 224 224 27>, 232 <&pfc 256 256 28>, <&pfc 288 288 21>, 233 <&pfc 320 320 10>; 234 interrupts-extended = 235 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, 236 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, 237 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, 238 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, 239 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, 240 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, 241 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, 242 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, 243 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, 244 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, 245 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, 246 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, 247 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, 248 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, 249 <&irqc1 24 0>, <&irqc1 25 0>; 250 power-domains = <&pd_c5>; 251 }; 252 253 thermal@e61f0000 { 254 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; 255 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, 256 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; 257 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; 259 power-domains = <&pd_c5>; 260 }; 261 262 i2c0: i2c@e6500000 { 263 #address-cells = <1>; 264 #size-cells = <0>; 265 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 266 reg = <0 0xe6500000 0 0x428>; 267 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; 269 power-domains = <&pd_a3sp>; 270 status = "disabled"; 271 }; 272 273 i2c1: i2c@e6510000 { 274 #address-cells = <1>; 275 #size-cells = <0>; 276 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 277 reg = <0 0xe6510000 0 0x428>; 278 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; 280 power-domains = <&pd_a3sp>; 281 status = "disabled"; 282 }; 283 284 i2c2: i2c@e6520000 { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 288 reg = <0 0xe6520000 0 0x428>; 289 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; 291 power-domains = <&pd_a3sp>; 292 status = "disabled"; 293 }; 294 295 i2c3: i2c@e6530000 { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 299 reg = <0 0xe6530000 0 0x428>; 300 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; 302 power-domains = <&pd_a3sp>; 303 status = "disabled"; 304 }; 305 306 i2c4: i2c@e6540000 { 307 #address-cells = <1>; 308 #size-cells = <0>; 309 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 310 reg = <0 0xe6540000 0 0x428>; 311 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; 313 power-domains = <&pd_a3sp>; 314 status = "disabled"; 315 }; 316 317 i2c6: i2c@e6550000 { 318 #address-cells = <1>; 319 #size-cells = <0>; 320 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 321 reg = <0 0xe6550000 0 0x428>; 322 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; 324 power-domains = <&pd_a3sp>; 325 status = "disabled"; 326 }; 327 328 i2c7: i2c@e6560000 { 329 #address-cells = <1>; 330 #size-cells = <0>; 331 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 332 reg = <0 0xe6560000 0 0x428>; 333 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; 335 power-domains = <&pd_a3sp>; 336 status = "disabled"; 337 }; 338 339 i2c8: i2c@e6570000 { 340 #address-cells = <1>; 341 #size-cells = <0>; 342 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 343 reg = <0 0xe6570000 0 0x428>; 344 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; 346 power-domains = <&pd_a3sp>; 347 status = "disabled"; 348 }; 349 350 scifb0: serial@e6c20000 { 351 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 352 reg = <0 0xe6c20000 0 0x100>; 353 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; 355 clock-names = "fck"; 356 power-domains = <&pd_a3sp>; 357 status = "disabled"; 358 }; 359 360 scifb1: serial@e6c30000 { 361 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 362 reg = <0 0xe6c30000 0 0x100>; 363 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; 365 clock-names = "fck"; 366 power-domains = <&pd_a3sp>; 367 status = "disabled"; 368 }; 369 370 scifa0: serial@e6c40000 { 371 compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 372 reg = <0 0xe6c40000 0 0x100>; 373 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; 375 clock-names = "fck"; 376 power-domains = <&pd_a3sp>; 377 status = "disabled"; 378 }; 379 380 scifa1: serial@e6c50000 { 381 compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 382 reg = <0 0xe6c50000 0 0x100>; 383 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; 385 clock-names = "fck"; 386 power-domains = <&pd_a3sp>; 387 status = "disabled"; 388 }; 389 390 scifb2: serial@e6ce0000 { 391 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 392 reg = <0 0xe6ce0000 0 0x100>; 393 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; 395 clock-names = "fck"; 396 power-domains = <&pd_a3sp>; 397 status = "disabled"; 398 }; 399 400 scifb3: serial@e6cf0000 { 401 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 402 reg = <0 0xe6cf0000 0 0x100>; 403 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; 405 clock-names = "fck"; 406 power-domains = <&pd_c4>; 407 status = "disabled"; 408 }; 409 410 sdhi0: sd@ee100000 { 411 compatible = "renesas,sdhi-r8a73a4"; 412 reg = <0 0xee100000 0 0x100>; 413 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; 415 power-domains = <&pd_a3sp>; 416 cap-sd-highspeed; 417 status = "disabled"; 418 }; 419 420 sdhi1: sd@ee120000 { 421 compatible = "renesas,sdhi-r8a73a4"; 422 reg = <0 0xee120000 0 0x100>; 423 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; 425 power-domains = <&pd_a3sp>; 426 cap-sd-highspeed; 427 status = "disabled"; 428 }; 429 430 sdhi2: sd@ee140000 { 431 compatible = "renesas,sdhi-r8a73a4"; 432 reg = <0 0xee140000 0 0x100>; 433 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; 435 power-domains = <&pd_a3sp>; 436 cap-sd-highspeed; 437 status = "disabled"; 438 }; 439 440 mmcif0: mmc@ee200000 { 441 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; 442 reg = <0 0xee200000 0 0x80>; 443 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; 445 power-domains = <&pd_a3sp>; 446 reg-io-width = <4>; 447 status = "disabled"; 448 }; 449 450 mmcif1: mmc@ee220000 { 451 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; 452 reg = <0 0xee220000 0 0x80>; 453 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; 455 power-domains = <&pd_a3sp>; 456 reg-io-width = <4>; 457 status = "disabled"; 458 }; 459 460 gic: interrupt-controller@f1001000 { 461 compatible = "arm,gic-400"; 462 #interrupt-cells = <3>; 463 #address-cells = <0>; 464 interrupt-controller; 465 reg = <0 0xf1001000 0 0x1000>, 466 <0 0xf1002000 0 0x2000>, 467 <0 0xf1004000 0 0x2000>, 468 <0 0xf1006000 0 0x2000>; 469 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 470 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>; 471 clock-names = "clk"; 472 power-domains = <&pd_c4>; 473 }; 474 475 bsc: bus@fec10000 { 476 compatible = "renesas,bsc-r8a73a4", "renesas,bsc", 477 "simple-pm-bus"; 478 #address-cells = <1>; 479 #size-cells = <1>; 480 ranges = <0 0 0 0x20000000>; 481 reg = <0 0xfec10000 0 0x400>; 482 clocks = <&zb_clk>; 483 power-domains = <&pd_c4>; 484 }; 485 486 clocks { 487 #address-cells = <2>; 488 #size-cells = <2>; 489 ranges; 490 491 /* External root clocks */ 492 extalr_clk: extalr { 493 compatible = "fixed-clock"; 494 #clock-cells = <0>; 495 clock-frequency = <32768>; 496 }; 497 extal1_clk: extal1 { 498 compatible = "fixed-clock"; 499 #clock-cells = <0>; 500 clock-frequency = <25000000>; 501 }; 502 extal2_clk: extal2 { 503 compatible = "fixed-clock"; 504 #clock-cells = <0>; 505 clock-frequency = <48000000>; 506 }; 507 fsiack_clk: fsiack { 508 compatible = "fixed-clock"; 509 #clock-cells = <0>; 510 /* This value must be overridden by the board. */ 511 clock-frequency = <0>; 512 }; 513 fsibck_clk: fsibck { 514 compatible = "fixed-clock"; 515 #clock-cells = <0>; 516 /* This value must be overridden by the board. */ 517 clock-frequency = <0>; 518 }; 519 520 /* Special CPG clocks */ 521 cpg_clocks: cpg_clocks@e6150000 { 522 compatible = "renesas,r8a73a4-cpg-clocks"; 523 reg = <0 0xe6150000 0 0x10000>; 524 clocks = <&extal1_clk>, <&extal2_clk>; 525 #clock-cells = <1>; 526 clock-output-names = "main", "pll0", "pll1", "pll2", 527 "pll2s", "pll2h", "z", "z2", 528 "i", "m3", "b", "m1", "m2", 529 "zx", "zs", "hp"; 530 }; 531 532 /* Variable factor clocks (DIV6) */ 533 zb_clk: zb_clk@e6150010 { 534 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 535 reg = <0 0xe6150010 0 4>; 536 clocks = <&pll1_div2_clk>, <0>, 537 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; 538 #clock-cells = <0>; 539 clock-output-names = "zb"; 540 }; 541 sdhi0_clk: sdhi0ck@e6150074 { 542 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 543 reg = <0 0xe6150074 0 4>; 544 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 545 <0>, <&extal2_clk>; 546 #clock-cells = <0>; 547 }; 548 sdhi1_clk: sdhi1ck@e6150078 { 549 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 550 reg = <0 0xe6150078 0 4>; 551 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 552 <0>, <&extal2_clk>; 553 #clock-cells = <0>; 554 }; 555 sdhi2_clk: sdhi2ck@e615007c { 556 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 557 reg = <0 0xe615007c 0 4>; 558 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 559 <0>, <&extal2_clk>; 560 #clock-cells = <0>; 561 }; 562 mmc0_clk: mmc0@e6150240 { 563 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 564 reg = <0 0xe6150240 0 4>; 565 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 566 <0>, <&extal2_clk>; 567 #clock-cells = <0>; 568 }; 569 mmc1_clk: mmc1@e6150244 { 570 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 571 reg = <0 0xe6150244 0 4>; 572 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 573 <0>, <&extal2_clk>; 574 #clock-cells = <0>; 575 }; 576 vclk1_clk: vclk1@e6150008 { 577 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 578 reg = <0 0xe6150008 0 4>; 579 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 580 <0>, <&extal2_clk>, <&main_div2_clk>, 581 <&extalr_clk>, <0>, <0>; 582 #clock-cells = <0>; 583 }; 584 vclk2_clk: vclk2@e615000c { 585 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 586 reg = <0 0xe615000c 0 4>; 587 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 588 <0>, <&extal2_clk>, <&main_div2_clk>, 589 <&extalr_clk>, <0>, <0>; 590 #clock-cells = <0>; 591 }; 592 vclk3_clk: vclk3@e615001c { 593 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 594 reg = <0 0xe615001c 0 4>; 595 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 596 <0>, <&extal2_clk>, <&main_div2_clk>, 597 <&extalr_clk>, <0>, <0>; 598 #clock-cells = <0>; 599 }; 600 vclk4_clk: vclk4@e6150014 { 601 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 602 reg = <0 0xe6150014 0 4>; 603 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 604 <0>, <&extal2_clk>, <&main_div2_clk>, 605 <&extalr_clk>, <0>, <0>; 606 #clock-cells = <0>; 607 }; 608 vclk5_clk: vclk5@e6150034 { 609 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 610 reg = <0 0xe6150034 0 4>; 611 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 612 <0>, <&extal2_clk>, <&main_div2_clk>, 613 <&extalr_clk>, <0>, <0>; 614 #clock-cells = <0>; 615 }; 616 fsia_clk: fsia@e6150018 { 617 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 618 reg = <0 0xe6150018 0 4>; 619 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 620 <&fsiack_clk>, <0>; 621 #clock-cells = <0>; 622 }; 623 fsib_clk: fsib@e6150090 { 624 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 625 reg = <0 0xe6150090 0 4>; 626 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 627 <&fsibck_clk>, <0>; 628 #clock-cells = <0>; 629 }; 630 mp_clk: mp@e6150080 { 631 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 632 reg = <0 0xe6150080 0 4>; 633 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 634 <&extal2_clk>, <&extal2_clk>; 635 #clock-cells = <0>; 636 }; 637 m4_clk: m4@e6150098 { 638 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 639 reg = <0 0xe6150098 0 4>; 640 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; 641 #clock-cells = <0>; 642 }; 643 hsi_clk: hsi@e615026c { 644 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 645 reg = <0 0xe615026c 0 4>; 646 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, 647 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; 648 #clock-cells = <0>; 649 }; 650 spuv_clk: spuv@e6150094 { 651 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 652 reg = <0 0xe6150094 0 4>; 653 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 654 <&extal2_clk>, <&extal2_clk>; 655 #clock-cells = <0>; 656 }; 657 658 /* Fixed factor clocks */ 659 main_div2_clk: main_div2 { 660 compatible = "fixed-factor-clock"; 661 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; 662 #clock-cells = <0>; 663 clock-div = <2>; 664 clock-mult = <1>; 665 }; 666 pll0_div2_clk: pll0_div2 { 667 compatible = "fixed-factor-clock"; 668 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; 669 #clock-cells = <0>; 670 clock-div = <2>; 671 clock-mult = <1>; 672 }; 673 pll1_div2_clk: pll1_div2 { 674 compatible = "fixed-factor-clock"; 675 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; 676 #clock-cells = <0>; 677 clock-div = <2>; 678 clock-mult = <1>; 679 }; 680 extal1_div2_clk: extal1_div2 { 681 compatible = "fixed-factor-clock"; 682 clocks = <&extal1_clk>; 683 #clock-cells = <0>; 684 clock-div = <2>; 685 clock-mult = <1>; 686 }; 687 688 /* Gate clocks */ 689 mstp2_clks: mstp2_clks@e6150138 { 690 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 691 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 692 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 693 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; 694 #clock-cells = <1>; 695 clock-indices = < 696 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 697 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 698 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 699 R8A73A4_CLK_DMAC 700 >; 701 clock-output-names = 702 "scifa0", "scifa1", "scifb0", "scifb1", 703 "scifb2", "scifb3", "dmac"; 704 }; 705 mstp3_clks: mstp3_clks@e615013c { 706 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 707 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 708 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, 709 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, 710 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, 711 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks 712 R8A73A4_CLK_HP>, <&cpg_clocks 713 R8A73A4_CLK_HP>, <&extalr_clk>; 714 #clock-cells = <1>; 715 clock-indices = < 716 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 717 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 718 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 719 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 720 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 721 R8A73A4_CLK_CMT1 722 >; 723 clock-output-names = 724 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", 725 "mmcif0", "iic6", "iic7", "iic0", "iic1", 726 "cmt1"; 727 }; 728 mstp4_clks: mstp4_clks@e6150140 { 729 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 730 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; 731 clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, 732 <&main_div2_clk>, 733 <&cpg_clocks R8A73A4_CLK_HP>, 734 <&cpg_clocks R8A73A4_CLK_HP>; 735 #clock-cells = <1>; 736 clock-indices = < 737 R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS 738 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 739 R8A73A4_CLK_IIC3 740 >; 741 clock-output-names = 742 "irqc", "intc-sys", "iic5", "iic4", "iic3"; 743 }; 744 mstp5_clks: mstp5_clks@e6150144 { 745 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 746 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 747 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; 748 #clock-cells = <1>; 749 clock-indices = < 750 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 751 >; 752 clock-output-names = 753 "thermal", "iic8"; 754 }; 755 }; 756 757 prr: chipid@ff000044 { 758 compatible = "renesas,prr"; 759 reg = <0 0xff000044 0 4>; 760 }; 761 762 sysc: system-controller@e6180000 { 763 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; 764 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; 765 766 pm-domains { 767 pd_c5: c5 { 768 #address-cells = <1>; 769 #size-cells = <0>; 770 #power-domain-cells = <0>; 771 772 pd_c4: c4@0 { 773 reg = <0>; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 #power-domain-cells = <0>; 777 778 pd_a3sg: a3sg@16 { 779 reg = <16>; 780 #power-domain-cells = <0>; 781 }; 782 783 pd_a3ex: a3ex@17 { 784 reg = <17>; 785 #power-domain-cells = <0>; 786 }; 787 788 pd_a3sp: a3sp@18 { 789 reg = <18>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 #power-domain-cells = <0>; 793 794 pd_a2us: a2us@19 { 795 reg = <19>; 796 #power-domain-cells = <0>; 797 }; 798 }; 799 800 pd_a3sm: a3sm@20 { 801 reg = <20>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 #power-domain-cells = <0>; 805 806 pd_a2sl: a2sl@21 { 807 reg = <21>; 808 #power-domain-cells = <0>; 809 }; 810 }; 811 812 pd_a3km: a3km@22 { 813 reg = <22>; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 #power-domain-cells = <0>; 817 818 pd_a2kl: a2kl@23 { 819 reg = <23>; 820 #power-domain-cells = <0>; 821 }; 822 }; 823 }; 824 825 pd_c4ma: c4ma@1 { 826 reg = <1>; 827 #power-domain-cells = <0>; 828 }; 829 830 pd_c4cl: c4cl@2 { 831 reg = <2>; 832 #power-domain-cells = <0>; 833 }; 834 835 pd_d4: d4@3 { 836 reg = <3>; 837 #power-domain-cells = <0>; 838 }; 839 840 pd_a4bc: a4bc@4 { 841 reg = <4>; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 #power-domain-cells = <0>; 845 846 pd_a3bc: a3bc@5 { 847 reg = <5>; 848 #power-domain-cells = <0>; 849 }; 850 }; 851 852 pd_a4l: a4l@6 { 853 reg = <6>; 854 #power-domain-cells = <0>; 855 }; 856 857 pd_a4lc: a4lc@7 { 858 reg = <7>; 859 #power-domain-cells = <0>; 860 }; 861 862 pd_a4mp: a4mp@8 { 863 reg = <8>; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 #power-domain-cells = <0>; 867 868 pd_a3mp: a3mp@9 { 869 reg = <9>; 870 #power-domain-cells = <0>; 871 }; 872 873 pd_a3vc: a3vc@10 { 874 reg = <10>; 875 #power-domain-cells = <0>; 876 }; 877 }; 878 879 pd_a4sf: a4sf@11 { 880 reg = <11>; 881 #power-domain-cells = <0>; 882 }; 883 884 pd_a3r: a3r@12 { 885 reg = <12>; 886 #address-cells = <1>; 887 #size-cells = <0>; 888 #power-domain-cells = <0>; 889 890 pd_a2rv: a2rv@13 { 891 reg = <13>; 892 #power-domain-cells = <0>; 893 }; 894 895 pd_a2is: a2is@14 { 896 reg = <14>; 897 #power-domain-cells = <0>; 898 }; 899 }; 900 }; 901 }; 902 }; 903}; 904