1/* 2 * Device Tree Source for the Marzen board 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Simon Horman 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12/dts-v1/; 13#include "r8a7779.dtsi" 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16 17/ { 18 model = "marzen"; 19 compatible = "renesas,marzen", "renesas,r8a7779"; 20 21 aliases { 22 serial0 = &scif2; 23 serial1 = &scif4; 24 }; 25 26 chosen { 27 bootargs = "ignore_loglevel root=/dev/nfs ip=on"; 28 stdout-path = "serial0:115200n8"; 29 }; 30 31 memory@60000000 { 32 device_type = "memory"; 33 reg = <0x60000000 0x40000000>; 34 }; 35 36 fixedregulator3v3: regulator-3v3 { 37 compatible = "regulator-fixed"; 38 regulator-name = "fixed-3.3V"; 39 regulator-min-microvolt = <3300000>; 40 regulator-max-microvolt = <3300000>; 41 regulator-boot-on; 42 regulator-always-on; 43 }; 44 45 ethernet@18000000 { 46 compatible = "smsc,lan9220", "smsc,lan9115"; 47 reg = <0x18000000 0x100>; 48 pinctrl-0 = <ðernet_pins>; 49 pinctrl-names = "default"; 50 51 phy-mode = "mii"; 52 interrupt-parent = <&irqpin0>; 53 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 54 smsc,irq-push-pull; 55 reg-io-width = <4>; 56 vddvario-supply = <&fixedregulator3v3>; 57 vdd33a-supply = <&fixedregulator3v3>; 58 }; 59 60 leds { 61 compatible = "gpio-leds"; 62 led2 { 63 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 64 }; 65 led3 { 66 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; 67 }; 68 led4 { 69 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; 70 }; 71 }; 72 73 vga-encoder { 74 compatible = "adi,adv7123"; 75 76 ports { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 80 port@0 { 81 reg = <0>; 82 vga_enc_in: endpoint { 83 remote-endpoint = <&du_out_rgb0>; 84 }; 85 }; 86 port@1 { 87 reg = <1>; 88 vga_enc_out: endpoint { 89 remote-endpoint = <&vga_in>; 90 }; 91 }; 92 }; 93 }; 94 95 vga { 96 compatible = "vga-connector"; 97 98 port { 99 vga_in: endpoint { 100 remote-endpoint = <&vga_enc_out>; 101 }; 102 }; 103 }; 104 105 lvds-encoder { 106 compatible = "thine,thc63lvdm83d"; 107 108 ports { 109 #address-cells = <1>; 110 #size-cells = <0>; 111 112 port@0 { 113 reg = <0>; 114 lvds_enc_in: endpoint { 115 remote-endpoint = <&du_out_rgb1>; 116 }; 117 }; 118 port@1 { 119 reg = <1>; 120 lvds_connector: endpoint { 121 }; 122 }; 123 }; 124 }; 125 126 x3_clk: x3-clock { 127 compatible = "fixed-clock"; 128 #clock-cells = <0>; 129 clock-frequency = <65000000>; 130 }; 131}; 132 133&du { 134 pinctrl-0 = <&du_pins>; 135 pinctrl-names = "default"; 136 status = "okay"; 137 138 clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>; 139 clock-names = "du", "dclkin.0"; 140 141 ports { 142 port@0 { 143 endpoint { 144 remote-endpoint = <&vga_enc_in>; 145 }; 146 }; 147 port@1 { 148 endpoint { 149 remote-endpoint = <&lvds_enc_in>; 150 }; 151 }; 152 }; 153}; 154 155&irqpin0 { 156 status = "okay"; 157}; 158 159&extal_clk { 160 clock-frequency = <31250000>; 161}; 162 163&tmu0 { 164 status = "okay"; 165}; 166 167&pfc { 168 pinctrl-0 = <&scif_clk_pins>; 169 pinctrl-names = "default"; 170 171 du_pins: du { 172 du0 { 173 groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", "du0_clk_in"; 174 function = "du0"; 175 }; 176 du1 { 177 groups = "du1_rgb666", "du1_sync_1", "du1_clk_out"; 178 function = "du1"; 179 }; 180 }; 181 182 scif_clk_pins: scif_clk { 183 groups = "scif_clk_b"; 184 function = "scif_clk"; 185 }; 186 187 ethernet_pins: ethernet { 188 intc { 189 groups = "intc_irq1_b"; 190 function = "intc"; 191 }; 192 lbsc { 193 groups = "lbsc_ex_cs0"; 194 function = "lbsc"; 195 }; 196 }; 197 198 scif2_pins: scif2 { 199 groups = "scif2_data_c"; 200 function = "scif2"; 201 }; 202 203 scif4_pins: scif4 { 204 groups = "scif4_data"; 205 function = "scif4"; 206 }; 207 208 sdhi0_pins: sd0 { 209 groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; 210 function = "sdhi0"; 211 }; 212 213 hspi0_pins: hspi0 { 214 groups = "hspi0"; 215 function = "hspi0"; 216 }; 217}; 218 219&sata { 220 status = "okay"; 221}; 222 223&scif2 { 224 pinctrl-0 = <&scif2_pins>; 225 pinctrl-names = "default"; 226 227 status = "okay"; 228}; 229 230&scif4 { 231 pinctrl-0 = <&scif4_pins>; 232 pinctrl-names = "default"; 233 234 status = "okay"; 235}; 236 237&scif_clk { 238 clock-frequency = <14745600>; 239}; 240 241&sdhi0 { 242 pinctrl-0 = <&sdhi0_pins>; 243 pinctrl-names = "default"; 244 245 vmmc-supply = <&fixedregulator3v3>; 246 bus-width = <4>; 247 status = "okay"; 248}; 249 250&hspi0 { 251 pinctrl-0 = <&hspi0_pins>; 252 pinctrl-names = "default"; 253 status = "okay"; 254}; 255