1/* 2 * Device Tree Source for the r8a7792 SoC 3 * 4 * Copyright (C) 2016 Cogent Embedded Inc. 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/clock/r8a7792-clock.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/r8a7792-sysc.h> 15 16/ { 17 compatible = "renesas,r8a7792"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 i2c0 = &i2c0; 23 i2c1 = &i2c1; 24 i2c2 = &i2c2; 25 i2c3 = &i2c3; 26 i2c4 = &i2c4; 27 i2c5 = &i2c5; 28 spi0 = &qspi; 29 spi1 = &msiof0; 30 spi2 = &msiof1; 31 vin0 = &vin0; 32 vin1 = &vin1; 33 vin2 = &vin2; 34 vin3 = &vin3; 35 vin4 = &vin4; 36 vin5 = &vin5; 37 }; 38 39 cpus { 40 #address-cells = <1>; 41 #size-cells = <0>; 42 enable-method = "renesas,apmu"; 43 44 cpu0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a15"; 47 reg = <0>; 48 clock-frequency = <1000000000>; 49 clocks = <&z_clk>; 50 power-domains = <&sysc R8A7792_PD_CA15_CPU0>; 51 next-level-cache = <&L2_CA15>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a15"; 57 reg = <1>; 58 clock-frequency = <1000000000>; 59 power-domains = <&sysc R8A7792_PD_CA15_CPU1>; 60 next-level-cache = <&L2_CA15>; 61 }; 62 63 L2_CA15: cache-controller-0 { 64 compatible = "cache"; 65 cache-unified; 66 cache-level = <2>; 67 power-domains = <&sysc R8A7792_PD_CA15_SCU>; 68 }; 69 }; 70 71 soc { 72 compatible = "simple-bus"; 73 interrupt-parent = <&gic>; 74 75 #address-cells = <2>; 76 #size-cells = <2>; 77 ranges; 78 79 apmu@e6152000 { 80 compatible = "renesas,r8a7792-apmu", "renesas,apmu"; 81 reg = <0 0xe6152000 0 0x188>; 82 cpus = <&cpu0 &cpu1>; 83 }; 84 85 gic: interrupt-controller@f1001000 { 86 compatible = "arm,gic-400"; 87 #interrupt-cells = <3>; 88 interrupt-controller; 89 reg = <0 0xf1001000 0 0x1000>, 90 <0 0xf1002000 0 0x2000>, 91 <0 0xf1004000 0 0x2000>, 92 <0 0xf1006000 0 0x2000>; 93 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 94 IRQ_TYPE_LEVEL_HIGH)>; 95 clocks = <&mstp4_clks R8A7792_CLK_INTC_SYS>; 96 clock-names = "clk"; 97 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 98 }; 99 100 irqc: interrupt-controller@e61c0000 { 101 compatible = "renesas,irqc-r8a7792", "renesas,irqc"; 102 #interrupt-cells = <2>; 103 interrupt-controller; 104 reg = <0 0xe61c0000 0 0x200>; 105 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 109 clocks = <&mstp4_clks R8A7792_CLK_IRQC>; 110 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 111 }; 112 113 timer { 114 compatible = "arm,armv7-timer"; 115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 116 IRQ_TYPE_LEVEL_LOW)>, 117 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 118 IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 120 IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 122 IRQ_TYPE_LEVEL_LOW)>; 123 }; 124 125 rst: reset-controller@e6160000 { 126 compatible = "renesas,r8a7792-rst"; 127 reg = <0 0xe6160000 0 0x0100>; 128 }; 129 130 prr: chipid@ff000044 { 131 compatible = "renesas,prr"; 132 reg = <0 0xff000044 0 4>; 133 }; 134 135 sysc: system-controller@e6180000 { 136 compatible = "renesas,r8a7792-sysc"; 137 reg = <0 0xe6180000 0 0x0200>; 138 #power-domain-cells = <1>; 139 }; 140 141 pfc: pin-controller@e6060000 { 142 compatible = "renesas,pfc-r8a7792"; 143 reg = <0 0xe6060000 0 0x144>; 144 }; 145 146 gpio0: gpio@e6050000 { 147 compatible = "renesas,gpio-r8a7792", 148 "renesas,gpio-rcar"; 149 reg = <0 0xe6050000 0 0x50>; 150 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 151 #gpio-cells = <2>; 152 gpio-controller; 153 gpio-ranges = <&pfc 0 0 29>; 154 #interrupt-cells = <2>; 155 interrupt-controller; 156 clocks = <&mstp9_clks R8A7792_CLK_GPIO0>; 157 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 158 }; 159 160 gpio1: gpio@e6051000 { 161 compatible = "renesas,gpio-r8a7792", 162 "renesas,gpio-rcar"; 163 reg = <0 0xe6051000 0 0x50>; 164 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 165 #gpio-cells = <2>; 166 gpio-controller; 167 gpio-ranges = <&pfc 0 32 23>; 168 #interrupt-cells = <2>; 169 interrupt-controller; 170 clocks = <&mstp9_clks R8A7792_CLK_GPIO1>; 171 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 172 }; 173 174 gpio2: gpio@e6052000 { 175 compatible = "renesas,gpio-r8a7792", 176 "renesas,gpio-rcar"; 177 reg = <0 0xe6052000 0 0x50>; 178 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 179 #gpio-cells = <2>; 180 gpio-controller; 181 gpio-ranges = <&pfc 0 64 32>; 182 #interrupt-cells = <2>; 183 interrupt-controller; 184 clocks = <&mstp9_clks R8A7792_CLK_GPIO2>; 185 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 186 }; 187 188 gpio3: gpio@e6053000 { 189 compatible = "renesas,gpio-r8a7792", 190 "renesas,gpio-rcar"; 191 reg = <0 0xe6053000 0 0x50>; 192 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 193 #gpio-cells = <2>; 194 gpio-controller; 195 gpio-ranges = <&pfc 0 96 28>; 196 #interrupt-cells = <2>; 197 interrupt-controller; 198 clocks = <&mstp9_clks R8A7792_CLK_GPIO3>; 199 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 200 }; 201 202 gpio4: gpio@e6054000 { 203 compatible = "renesas,gpio-r8a7792", 204 "renesas,gpio-rcar"; 205 reg = <0 0xe6054000 0 0x50>; 206 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 207 #gpio-cells = <2>; 208 gpio-controller; 209 gpio-ranges = <&pfc 0 128 17>; 210 #interrupt-cells = <2>; 211 interrupt-controller; 212 clocks = <&mstp9_clks R8A7792_CLK_GPIO4>; 213 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 214 }; 215 216 gpio5: gpio@e6055000 { 217 compatible = "renesas,gpio-r8a7792", 218 "renesas,gpio-rcar"; 219 reg = <0 0xe6055000 0 0x50>; 220 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 221 #gpio-cells = <2>; 222 gpio-controller; 223 gpio-ranges = <&pfc 0 160 17>; 224 #interrupt-cells = <2>; 225 interrupt-controller; 226 clocks = <&mstp9_clks R8A7792_CLK_GPIO5>; 227 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 228 }; 229 230 gpio6: gpio@e6055100 { 231 compatible = "renesas,gpio-r8a7792", 232 "renesas,gpio-rcar"; 233 reg = <0 0xe6055100 0 0x50>; 234 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 235 #gpio-cells = <2>; 236 gpio-controller; 237 gpio-ranges = <&pfc 0 192 17>; 238 #interrupt-cells = <2>; 239 interrupt-controller; 240 clocks = <&mstp9_clks R8A7792_CLK_GPIO6>; 241 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 242 }; 243 244 gpio7: gpio@e6055200 { 245 compatible = "renesas,gpio-r8a7792", 246 "renesas,gpio-rcar"; 247 reg = <0 0xe6055200 0 0x50>; 248 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 249 #gpio-cells = <2>; 250 gpio-controller; 251 gpio-ranges = <&pfc 0 224 17>; 252 #interrupt-cells = <2>; 253 interrupt-controller; 254 clocks = <&mstp9_clks R8A7792_CLK_GPIO7>; 255 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 256 }; 257 258 gpio8: gpio@e6055300 { 259 compatible = "renesas,gpio-r8a7792", 260 "renesas,gpio-rcar"; 261 reg = <0 0xe6055300 0 0x50>; 262 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 263 #gpio-cells = <2>; 264 gpio-controller; 265 gpio-ranges = <&pfc 0 256 17>; 266 #interrupt-cells = <2>; 267 interrupt-controller; 268 clocks = <&mstp9_clks R8A7792_CLK_GPIO8>; 269 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 270 }; 271 272 gpio9: gpio@e6055400 { 273 compatible = "renesas,gpio-r8a7792", 274 "renesas,gpio-rcar"; 275 reg = <0 0xe6055400 0 0x50>; 276 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 277 #gpio-cells = <2>; 278 gpio-controller; 279 gpio-ranges = <&pfc 0 288 17>; 280 #interrupt-cells = <2>; 281 interrupt-controller; 282 clocks = <&mstp9_clks R8A7792_CLK_GPIO9>; 283 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 284 }; 285 286 gpio10: gpio@e6055500 { 287 compatible = "renesas,gpio-r8a7792", 288 "renesas,gpio-rcar"; 289 reg = <0 0xe6055500 0 0x50>; 290 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 291 #gpio-cells = <2>; 292 gpio-controller; 293 gpio-ranges = <&pfc 0 320 32>; 294 #interrupt-cells = <2>; 295 interrupt-controller; 296 clocks = <&mstp9_clks R8A7792_CLK_GPIO10>; 297 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 298 }; 299 300 gpio11: gpio@e6055600 { 301 compatible = "renesas,gpio-r8a7792", 302 "renesas,gpio-rcar"; 303 reg = <0 0xe6055600 0 0x50>; 304 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 305 #gpio-cells = <2>; 306 gpio-controller; 307 gpio-ranges = <&pfc 0 352 30>; 308 #interrupt-cells = <2>; 309 interrupt-controller; 310 clocks = <&mstp9_clks R8A7792_CLK_GPIO11>; 311 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 312 }; 313 314 dmac0: dma-controller@e6700000 { 315 compatible = "renesas,dmac-r8a7792", 316 "renesas,rcar-dmac"; 317 reg = <0 0xe6700000 0 0x20000>; 318 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 319 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 320 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 321 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 322 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 323 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 324 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 325 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 326 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 327 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 328 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 329 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 330 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 331 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 332 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 333 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 334 interrupt-names = "error", 335 "ch0", "ch1", "ch2", "ch3", 336 "ch4", "ch5", "ch6", "ch7", 337 "ch8", "ch9", "ch10", "ch11", 338 "ch12", "ch13", "ch14"; 339 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>; 340 clock-names = "fck"; 341 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 342 #dma-cells = <1>; 343 dma-channels = <15>; 344 }; 345 346 dmac1: dma-controller@e6720000 { 347 compatible = "renesas,dmac-r8a7792", 348 "renesas,rcar-dmac"; 349 reg = <0 0xe6720000 0 0x20000>; 350 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 351 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 352 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 353 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 354 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 355 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 356 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 357 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 358 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 359 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 360 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 361 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 362 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 363 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 364 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 365 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 366 interrupt-names = "error", 367 "ch0", "ch1", "ch2", "ch3", 368 "ch4", "ch5", "ch6", "ch7", 369 "ch8", "ch9", "ch10", "ch11", 370 "ch12", "ch13", "ch14"; 371 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>; 372 clock-names = "fck"; 373 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 374 #dma-cells = <1>; 375 dma-channels = <15>; 376 }; 377 378 scif0: serial@e6e60000 { 379 compatible = "renesas,scif-r8a7792", 380 "renesas,rcar-gen2-scif", "renesas,scif"; 381 reg = <0 0xe6e60000 0 64>; 382 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>, 384 <&scif_clk>; 385 clock-names = "fck", "brg_int", "scif_clk"; 386 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 387 <&dmac1 0x29>, <&dmac1 0x2a>; 388 dma-names = "tx", "rx", "tx", "rx"; 389 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 390 status = "disabled"; 391 }; 392 393 scif1: serial@e6e68000 { 394 compatible = "renesas,scif-r8a7792", 395 "renesas,rcar-gen2-scif", "renesas,scif"; 396 reg = <0 0xe6e68000 0 64>; 397 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>, 399 <&scif_clk>; 400 clock-names = "fck", "brg_int", "scif_clk"; 401 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 402 <&dmac1 0x2d>, <&dmac1 0x2e>; 403 dma-names = "tx", "rx", "tx", "rx"; 404 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 405 status = "disabled"; 406 }; 407 408 scif2: serial@e6e58000 { 409 compatible = "renesas,scif-r8a7792", 410 "renesas,rcar-gen2-scif", "renesas,scif"; 411 reg = <0 0xe6e58000 0 64>; 412 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>, 414 <&scif_clk>; 415 clock-names = "fck", "brg_int", "scif_clk"; 416 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 417 <&dmac1 0x2b>, <&dmac1 0x2c>; 418 dma-names = "tx", "rx", "tx", "rx"; 419 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 420 status = "disabled"; 421 }; 422 423 scif3: serial@e6ea8000 { 424 compatible = "renesas,scif-r8a7792", 425 "renesas,rcar-gen2-scif", "renesas,scif"; 426 reg = <0 0xe6ea8000 0 64>; 427 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>, 429 <&scif_clk>; 430 clock-names = "fck", "brg_int", "scif_clk"; 431 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 432 <&dmac1 0x2f>, <&dmac1 0x30>; 433 dma-names = "tx", "rx", "tx", "rx"; 434 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 435 status = "disabled"; 436 }; 437 438 hscif0: serial@e62c0000 { 439 compatible = "renesas,hscif-r8a7792", 440 "renesas,rcar-gen2-hscif", "renesas,hscif"; 441 reg = <0 0xe62c0000 0 96>; 442 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>, 444 <&scif_clk>; 445 clock-names = "fck", "brg_int", "scif_clk"; 446 dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 447 <&dmac1 0x39>, <&dmac1 0x3a>; 448 dma-names = "tx", "rx", "tx", "rx"; 449 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 450 status = "disabled"; 451 }; 452 453 hscif1: serial@e62c8000 { 454 compatible = "renesas,hscif-r8a7792", 455 "renesas,rcar-gen2-hscif", "renesas,hscif"; 456 reg = <0 0xe62c8000 0 96>; 457 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>, 459 <&scif_clk>; 460 clock-names = "fck", "brg_int", "scif_clk"; 461 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 462 <&dmac1 0x4d>, <&dmac1 0x4e>; 463 dma-names = "tx", "rx", "tx", "rx"; 464 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 465 status = "disabled"; 466 }; 467 468 icram0: sram@e63a0000 { 469 compatible = "mmio-sram"; 470 reg = <0 0xe63a0000 0 0x12000>; 471 }; 472 473 icram1: sram@e63c0000 { 474 compatible = "mmio-sram"; 475 reg = <0 0xe63c0000 0 0x1000>; 476 #address-cells = <1>; 477 #size-cells = <1>; 478 ranges = <0 0 0xe63c0000 0x1000>; 479 480 smp-sram@0 { 481 compatible = "renesas,smp-sram"; 482 reg = <0 0x10>; 483 }; 484 }; 485 486 sdhi0: sd@ee100000 { 487 compatible = "renesas,sdhi-r8a7792"; 488 reg = <0 0xee100000 0 0x328>; 489 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 490 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 491 <&dmac1 0xcd>, <&dmac1 0xce>; 492 dma-names = "tx", "rx", "tx", "rx"; 493 clocks = <&mstp3_clks R8A7792_CLK_SDHI0>; 494 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 495 status = "disabled"; 496 }; 497 498 jpu: jpeg-codec@fe980000 { 499 compatible = "renesas,jpu-r8a7792", 500 "renesas,rcar-gen2-jpu"; 501 reg = <0 0xfe980000 0 0x10300>; 502 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&mstp1_clks R8A7792_CLK_JPU>; 504 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 505 }; 506 507 avb: ethernet@e6800000 { 508 compatible = "renesas,etheravb-r8a7792", 509 "renesas,etheravb-rcar-gen2"; 510 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 511 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>; 513 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 status = "disabled"; 517 }; 518 519 /* I2C doesn't need pinmux */ 520 i2c0: i2c@e6508000 { 521 compatible = "renesas,i2c-r8a7792", 522 "renesas,rcar-gen2-i2c"; 523 reg = <0 0xe6508000 0 0x40>; 524 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&mstp9_clks R8A7792_CLK_I2C0>; 526 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 527 i2c-scl-internal-delay-ns = <6>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 status = "disabled"; 531 }; 532 533 i2c1: i2c@e6518000 { 534 compatible = "renesas,i2c-r8a7792", 535 "renesas,rcar-gen2-i2c"; 536 reg = <0 0xe6518000 0 0x40>; 537 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&mstp9_clks R8A7792_CLK_I2C1>; 539 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 540 i2c-scl-internal-delay-ns = <6>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 status = "disabled"; 544 }; 545 546 i2c2: i2c@e6530000 { 547 compatible = "renesas,i2c-r8a7792", 548 "renesas,rcar-gen2-i2c"; 549 reg = <0 0xe6530000 0 0x40>; 550 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&mstp9_clks R8A7792_CLK_I2C2>; 552 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 553 i2c-scl-internal-delay-ns = <6>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 status = "disabled"; 557 }; 558 559 i2c3: i2c@e6540000 { 560 compatible = "renesas,i2c-r8a7792", 561 "renesas,rcar-gen2-i2c"; 562 reg = <0 0xe6540000 0 0x40>; 563 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&mstp9_clks R8A7792_CLK_I2C3>; 565 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 566 i2c-scl-internal-delay-ns = <6>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 i2c4: i2c@e6520000 { 573 compatible = "renesas,i2c-r8a7792", 574 "renesas,rcar-gen2-i2c"; 575 reg = <0 0xe6520000 0 0x40>; 576 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&mstp9_clks R8A7792_CLK_I2C4>; 578 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 579 i2c-scl-internal-delay-ns = <6>; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 status = "disabled"; 583 }; 584 585 i2c5: i2c@e6528000 { 586 compatible = "renesas,i2c-r8a7792", 587 "renesas,rcar-gen2-i2c"; 588 reg = <0 0xe6528000 0 0x40>; 589 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&mstp9_clks R8A7792_CLK_I2C5>; 591 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 592 i2c-scl-internal-delay-ns = <110>; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 status = "disabled"; 596 }; 597 598 qspi: spi@e6b10000 { 599 compatible = "renesas,qspi-r8a7792", "renesas,qspi"; 600 reg = <0 0xe6b10000 0 0x2c>; 601 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>; 603 dmas = <&dmac0 0x17>, <&dmac0 0x18>, 604 <&dmac1 0x17>, <&dmac1 0x18>; 605 dma-names = "tx", "rx", "tx", "rx"; 606 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 607 num-cs = <1>; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 status = "disabled"; 611 }; 612 613 msiof0: spi@e6e20000 { 614 compatible = "renesas,msiof-r8a7792", 615 "renesas,rcar-gen2-msiof"; 616 reg = <0 0xe6e20000 0 0x0064>; 617 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>; 619 dmas = <&dmac0 0x51>, <&dmac0 0x52>, 620 <&dmac1 0x51>, <&dmac1 0x52>; 621 dma-names = "tx", "rx", "tx", "rx"; 622 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 status = "disabled"; 626 }; 627 628 msiof1: spi@e6e10000 { 629 compatible = "renesas,msiof-r8a7792", 630 "renesas,rcar-gen2-msiof"; 631 reg = <0 0xe6e10000 0 0x0064>; 632 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>; 634 dmas = <&dmac0 0x55>, <&dmac0 0x56>, 635 <&dmac1 0x55>, <&dmac1 0x56>; 636 dma-names = "tx", "rx", "tx", "rx"; 637 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 status = "disabled"; 641 }; 642 643 du: display@feb00000 { 644 compatible = "renesas,du-r8a7792"; 645 reg = <0 0xfeb00000 0 0x40000>; 646 reg-names = "du"; 647 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&mstp7_clks R8A7792_CLK_DU0>, 650 <&mstp7_clks R8A7792_CLK_DU1>; 651 clock-names = "du.0", "du.1"; 652 status = "disabled"; 653 654 ports { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 658 port@0 { 659 reg = <0>; 660 du_out_rgb0: endpoint { 661 }; 662 }; 663 port@1 { 664 reg = <1>; 665 du_out_rgb1: endpoint { 666 }; 667 }; 668 }; 669 }; 670 671 can0: can@e6e80000 { 672 compatible = "renesas,can-r8a7792", 673 "renesas,rcar-gen2-can"; 674 reg = <0 0xe6e80000 0 0x1000>; 675 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&mstp9_clks R8A7792_CLK_CAN0>, 677 <&rcan_clk>, <&can_clk>; 678 clock-names = "clkp1", "clkp2", "can_clk"; 679 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 680 status = "disabled"; 681 }; 682 683 can1: can@e6e88000 { 684 compatible = "renesas,can-r8a7792", 685 "renesas,rcar-gen2-can"; 686 reg = <0 0xe6e88000 0 0x1000>; 687 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&mstp9_clks R8A7792_CLK_CAN1>, 689 <&rcan_clk>, <&can_clk>; 690 clock-names = "clkp1", "clkp2", "can_clk"; 691 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 692 status = "disabled"; 693 }; 694 695 vin0: video@e6ef0000 { 696 compatible = "renesas,vin-r8a7792", 697 "renesas,rcar-gen2-vin"; 698 reg = <0 0xe6ef0000 0 0x1000>; 699 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&mstp8_clks R8A7792_CLK_VIN0>; 701 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 702 status = "disabled"; 703 }; 704 705 vin1: video@e6ef1000 { 706 compatible = "renesas,vin-r8a7792", 707 "renesas,rcar-gen2-vin"; 708 reg = <0 0xe6ef1000 0 0x1000>; 709 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&mstp8_clks R8A7792_CLK_VIN1>; 711 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 712 status = "disabled"; 713 }; 714 715 vin2: video@e6ef2000 { 716 compatible = "renesas,vin-r8a7792", 717 "renesas,rcar-gen2-vin"; 718 reg = <0 0xe6ef2000 0 0x1000>; 719 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&mstp8_clks R8A7792_CLK_VIN2>; 721 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 722 status = "disabled"; 723 }; 724 725 vin3: video@e6ef3000 { 726 compatible = "renesas,vin-r8a7792", 727 "renesas,rcar-gen2-vin"; 728 reg = <0 0xe6ef3000 0 0x1000>; 729 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&mstp8_clks R8A7792_CLK_VIN3>; 731 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 732 status = "disabled"; 733 }; 734 735 vin4: video@e6ef4000 { 736 compatible = "renesas,vin-r8a7792", 737 "renesas,rcar-gen2-vin"; 738 reg = <0 0xe6ef4000 0 0x1000>; 739 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&mstp8_clks R8A7792_CLK_VIN4>; 741 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 742 status = "disabled"; 743 }; 744 745 vin5: video@e6ef5000 { 746 compatible = "renesas,vin-r8a7792", 747 "renesas,rcar-gen2-vin"; 748 reg = <0 0xe6ef5000 0 0x1000>; 749 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&mstp8_clks R8A7792_CLK_VIN5>; 751 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 752 status = "disabled"; 753 }; 754 755 vsp1@fe928000 { 756 compatible = "renesas,vsp1"; 757 reg = <0 0xfe928000 0 0x8000>; 758 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>; 760 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 761 }; 762 763 vsp1@fe930000 { 764 compatible = "renesas,vsp1"; 765 reg = <0 0xfe930000 0 0x8000>; 766 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>; 768 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 769 }; 770 771 vsp1@fe938000 { 772 compatible = "renesas,vsp1"; 773 reg = <0 0xfe938000 0 0x8000>; 774 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>; 776 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 777 }; 778 779 /* Special CPG clocks */ 780 cpg_clocks: cpg_clocks@e6150000 { 781 compatible = "renesas,r8a7792-cpg-clocks", 782 "renesas,rcar-gen2-cpg-clocks"; 783 reg = <0 0xe6150000 0 0x1000>; 784 clocks = <&extal_clk>; 785 #clock-cells = <1>; 786 clock-output-names = "main", "pll0", "pll1", "pll3", 787 "lb", "qspi"; 788 #power-domain-cells = <0>; 789 }; 790 791 /* Fixed factor clocks */ 792 pll1_div2_clk: pll1_div2 { 793 compatible = "fixed-factor-clock"; 794 clocks = <&cpg_clocks R8A7792_CLK_PLL1>; 795 #clock-cells = <0>; 796 clock-div = <2>; 797 clock-mult = <1>; 798 }; 799 z_clk: z { 800 compatible = "fixed-factor-clock"; 801 clocks = <&cpg_clocks R8A7792_CLK_PLL0>; 802 #clock-cells = <0>; 803 clock-div = <1>; 804 clock-mult = <1>; 805 }; 806 zx_clk: zx { 807 compatible = "fixed-factor-clock"; 808 clocks = <&cpg_clocks R8A7792_CLK_PLL1>; 809 #clock-cells = <0>; 810 clock-div = <3>; 811 clock-mult = <1>; 812 }; 813 zs_clk: zs { 814 compatible = "fixed-factor-clock"; 815 clocks = <&cpg_clocks R8A7792_CLK_PLL1>; 816 #clock-cells = <0>; 817 clock-div = <6>; 818 clock-mult = <1>; 819 }; 820 hp_clk: hp { 821 compatible = "fixed-factor-clock"; 822 clocks = <&cpg_clocks R8A7792_CLK_PLL1>; 823 #clock-cells = <0>; 824 clock-div = <12>; 825 clock-mult = <1>; 826 }; 827 p_clk: p { 828 compatible = "fixed-factor-clock"; 829 clocks = <&cpg_clocks R8A7792_CLK_PLL1>; 830 #clock-cells = <0>; 831 clock-div = <24>; 832 clock-mult = <1>; 833 }; 834 cp_clk: cp { 835 compatible = "fixed-factor-clock"; 836 clocks = <&cpg_clocks R8A7792_CLK_PLL1>; 837 #clock-cells = <0>; 838 clock-div = <48>; 839 clock-mult = <1>; 840 }; 841 mp_clk: mp { 842 compatible = "fixed-factor-clock"; 843 clocks = <&pll1_div2_clk>; 844 #clock-cells = <0>; 845 clock-div = <15>; 846 clock-mult = <1>; 847 }; 848 m2_clk: m2 { 849 compatible = "fixed-factor-clock"; 850 clocks = <&cpg_clocks R8A7792_CLK_PLL1>; 851 #clock-cells = <0>; 852 clock-div = <8>; 853 clock-mult = <1>; 854 }; 855 sd_clk: sd { 856 compatible = "fixed-factor-clock"; 857 clocks = <&pll1_div2_clk>; 858 #clock-cells = <0>; 859 clock-div = <8>; 860 clock-mult = <1>; 861 }; 862 rcan_clk: rcan { 863 compatible = "fixed-factor-clock"; 864 clocks = <&pll1_div2_clk>; 865 #clock-cells = <0>; 866 clock-div = <49>; 867 clock-mult = <1>; 868 }; 869 zg_clk: zg { 870 compatible = "fixed-factor-clock"; 871 clocks = <&cpg_clocks R8A7792_CLK_PLL1>; 872 #clock-cells = <0>; 873 clock-div = <5>; 874 clock-mult = <1>; 875 }; 876 877 /* Gate clocks */ 878 mstp0_clks: mstp0_clks@e6150130 { 879 compatible = "renesas,r8a7792-mstp-clocks", 880 "renesas,cpg-mstp-clocks"; 881 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; 882 clocks = <&mp_clk>; 883 #clock-cells = <1>; 884 clock-indices = <R8A7792_CLK_MSIOF0>; 885 clock-output-names = "msiof0"; 886 }; 887 mstp1_clks: mstp1_clks@e6150134 { 888 compatible = "renesas,r8a7792-mstp-clocks", 889 "renesas,cpg-mstp-clocks"; 890 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 891 clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; 892 #clock-cells = <1>; 893 clock-indices = < 894 R8A7792_CLK_JPU 895 R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0 896 R8A7792_CLK_VSP1_SY 897 >; 898 clock-output-names = "jpu", "vsp1du1", "vsp1du0", 899 "vsp1-sy"; 900 }; 901 mstp2_clks: mstp2_clks@e6150138 { 902 compatible = "renesas,r8a7792-mstp-clocks", 903 "renesas,cpg-mstp-clocks"; 904 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 905 clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>; 906 #clock-cells = <1>; 907 clock-indices = < 908 R8A7792_CLK_MSIOF1 909 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0 910 >; 911 clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0"; 912 }; 913 mstp3_clks: mstp3_clks@e615013c { 914 compatible = "renesas,r8a7792-mstp-clocks", 915 "renesas,cpg-mstp-clocks"; 916 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 917 clocks = <&sd_clk>; 918 #clock-cells = <1>; 919 renesas,clock-indices = <R8A7792_CLK_SDHI0>; 920 clock-output-names = "sdhi0"; 921 }; 922 mstp4_clks: mstp4_clks@e6150140 { 923 compatible = "renesas,r8a7792-mstp-clocks", 924 "renesas,cpg-mstp-clocks"; 925 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; 926 clocks = <&cp_clk>, <&zs_clk>; 927 #clock-cells = <1>; 928 clock-indices = < 929 R8A7792_CLK_IRQC R8A7792_CLK_INTC_SYS 930 >; 931 clock-output-names = "irqc", "intc-sys"; 932 }; 933 mstp7_clks: mstp7_clks@e615014c { 934 compatible = "renesas,r8a7792-mstp-clocks", 935 "renesas,cpg-mstp-clocks"; 936 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; 937 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, 938 <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>; 939 #clock-cells = <1>; 940 clock-indices = < 941 R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0 942 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2 943 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0 944 R8A7792_CLK_DU1 R8A7792_CLK_DU0 945 >; 946 clock-output-names = "hscif1", "hscif0", "scif3", 947 "scif2", "scif1", "scif0", 948 "du1", "du0"; 949 }; 950 mstp8_clks: mstp8_clks@e6150990 { 951 compatible = "renesas,r8a7792-mstp-clocks", 952 "renesas,cpg-mstp-clocks"; 953 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 954 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, 955 <&zg_clk>, <&zg_clk>, <&hp_clk>; 956 #clock-cells = <1>; 957 clock-indices = < 958 R8A7792_CLK_VIN5 R8A7792_CLK_VIN4 959 R8A7792_CLK_VIN3 R8A7792_CLK_VIN2 960 R8A7792_CLK_VIN1 R8A7792_CLK_VIN0 961 R8A7792_CLK_ETHERAVB 962 >; 963 clock-output-names = "vin5", "vin4", "vin3", "vin2", 964 "vin1", "vin0", "etheravb"; 965 }; 966 mstp9_clks: mstp9_clks@e6150994 { 967 compatible = "renesas,r8a7792-mstp-clocks", 968 "renesas,cpg-mstp-clocks"; 969 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; 970 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, 971 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, 972 <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>, 973 <&cpg_clocks R8A7792_CLK_QSPI>, 974 <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>, 975 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; 976 #clock-cells = <1>; 977 clock-indices = < 978 R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6 979 R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4 980 R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2 981 R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0 982 R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10 983 R8A7792_CLK_CAN1 R8A7792_CLK_CAN0 984 R8A7792_CLK_QSPI_MOD 985 R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8 986 R8A7792_CLK_I2C5 R8A7792_CLK_I2C4 987 R8A7792_CLK_I2C3 R8A7792_CLK_I2C2 988 R8A7792_CLK_I2C1 R8A7792_CLK_I2C0 989 >; 990 clock-output-names = 991 "gpio7", "gpio6", "gpio5", "gpio4", 992 "gpio3", "gpio2", "gpio1", "gpio0", 993 "gpio11", "gpio10", "can1", "can0", 994 "qspi_mod", "gpio9", "gpio8", 995 "i2c5", "i2c4", "i2c3", "i2c2", 996 "i2c1", "i2c0"; 997 }; 998 }; 999 1000 /* External root clock */ 1001 extal_clk: extal { 1002 compatible = "fixed-clock"; 1003 #clock-cells = <0>; 1004 /* This value must be overridden by the board. */ 1005 clock-frequency = <0>; 1006 }; 1007 1008 /* External SCIF clock */ 1009 scif_clk: scif { 1010 compatible = "fixed-clock"; 1011 #clock-cells = <0>; 1012 /* This value must be overridden by the board. */ 1013 clock-frequency = <0>; 1014 }; 1015 1016 /* External CAN clock */ 1017 can_clk: can { 1018 compatible = "fixed-clock"; 1019 #clock-cells = <0>; 1020 /* This value must be overridden by the board. */ 1021 clock-frequency = <0>; 1022 }; 1023}; 1024