1/* 2 * Device Tree Source for the Alt board 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11/dts-v1/; 12#include "r8a7794.dtsi" 13#include <dt-bindings/gpio/gpio.h> 14 15/ { 16 model = "Alt"; 17 compatible = "renesas,alt", "renesas,r8a7794"; 18 19 aliases { 20 serial0 = &scif2; 21 i2c10 = &gpioi2c4; 22 i2c12 = &i2cexio4; 23 }; 24 25 chosen { 26 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; 27 stdout-path = "serial0:115200n8"; 28 }; 29 30 memory@40000000 { 31 device_type = "memory"; 32 reg = <0 0x40000000 0 0x40000000>; 33 }; 34 35 d3_3v: regulator-d3-3v { 36 compatible = "regulator-fixed"; 37 regulator-name = "D3.3V"; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 regulator-boot-on; 41 regulator-always-on; 42 }; 43 44 vcc_sdhi0: regulator-vcc-sdhi0 { 45 compatible = "regulator-fixed"; 46 47 regulator-name = "SDHI0 Vcc"; 48 regulator-min-microvolt = <3300000>; 49 regulator-max-microvolt = <3300000>; 50 51 gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; 52 enable-active-high; 53 }; 54 55 vccq_sdhi0: regulator-vccq-sdhi0 { 56 compatible = "regulator-gpio"; 57 58 regulator-name = "SDHI0 VccQ"; 59 regulator-min-microvolt = <1800000>; 60 regulator-max-microvolt = <3300000>; 61 62 gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; 63 gpios-states = <1>; 64 states = <3300000 1 65 1800000 0>; 66 }; 67 68 vcc_sdhi1: regulator-vcc-sdhi1 { 69 compatible = "regulator-fixed"; 70 71 regulator-name = "SDHI1 Vcc"; 72 regulator-min-microvolt = <3300000>; 73 regulator-max-microvolt = <3300000>; 74 75 gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; 76 enable-active-high; 77 }; 78 79 vccq_sdhi1: regulator-vccq-sdhi1 { 80 compatible = "regulator-gpio"; 81 82 regulator-name = "SDHI1 VccQ"; 83 regulator-min-microvolt = <1800000>; 84 regulator-max-microvolt = <3300000>; 85 86 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 87 gpios-states = <1>; 88 states = <3300000 1 89 1800000 0>; 90 }; 91 92 lbsc { 93 #address-cells = <1>; 94 #size-cells = <1>; 95 }; 96 97 vga-encoder { 98 compatible = "adi,adv7123"; 99 100 ports { 101 #address-cells = <1>; 102 #size-cells = <0>; 103 104 port@0 { 105 reg = <0>; 106 adv7123_in: endpoint { 107 remote-endpoint = <&du_out_rgb1>; 108 }; 109 }; 110 port@1 { 111 reg = <1>; 112 adv7123_out: endpoint { 113 remote-endpoint = <&vga_in>; 114 }; 115 }; 116 }; 117 }; 118 119 vga { 120 compatible = "vga-connector"; 121 122 port { 123 vga_in: endpoint { 124 remote-endpoint = <&adv7123_out>; 125 }; 126 }; 127 }; 128 129 x2_clk: x2-clock { 130 compatible = "fixed-clock"; 131 #clock-cells = <0>; 132 clock-frequency = <74250000>; 133 }; 134 135 x13_clk: x13-clock { 136 compatible = "fixed-clock"; 137 #clock-cells = <0>; 138 clock-frequency = <148500000>; 139 }; 140 141 gpioi2c4: i2c-10 { 142 #address-cells = <1>; 143 #size-cells = <0>; 144 compatible = "i2c-gpio"; 145 status = "disabled"; 146 gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */ 147 &gpio4 8 GPIO_ACTIVE_HIGH /* scl */ 148 >; 149 i2c-gpio,delay-us = <5>; 150 }; 151 152 /* 153 * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA). 154 * A fallback to GPIO is provided. 155 */ 156 i2cexio4: i2c-14 { 157 compatible = "i2c-demux-pinctrl"; 158 i2c-parent = <&i2c4>, <&gpioi2c4>; 159 i2c-bus-name = "i2c-exio4"; 160 #address-cells = <1>; 161 #size-cells = <0>; 162 }; 163}; 164 165&du { 166 pinctrl-0 = <&du_pins>; 167 pinctrl-names = "default"; 168 status = "okay"; 169 170 clocks = <&mstp7_clks R8A7794_CLK_DU0>, 171 <&mstp7_clks R8A7794_CLK_DU1>, 172 <&x13_clk>, <&x2_clk>; 173 clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; 174 175 ports { 176 port@1 { 177 endpoint { 178 remote-endpoint = <&adv7123_in>; 179 }; 180 }; 181 }; 182}; 183 184&extal_clk { 185 clock-frequency = <20000000>; 186}; 187 188&pfc { 189 pinctrl-0 = <&scif_clk_pins>; 190 pinctrl-names = "default"; 191 192 du_pins: du { 193 groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; 194 function = "du1"; 195 }; 196 197 scif2_pins: scif2 { 198 groups = "scif2_data"; 199 function = "scif2"; 200 }; 201 202 scif_clk_pins: scif_clk { 203 groups = "scif_clk"; 204 function = "scif_clk"; 205 }; 206 207 ether_pins: ether { 208 groups = "eth_link", "eth_mdio", "eth_rmii"; 209 function = "eth"; 210 }; 211 212 phy1_pins: phy1 { 213 groups = "intc_irq8"; 214 function = "intc"; 215 }; 216 217 i2c1_pins: i2c1 { 218 groups = "i2c1"; 219 function = "i2c1"; 220 }; 221 222 i2c4_pins: i2c4 { 223 groups = "i2c4"; 224 function = "i2c4"; 225 }; 226 227 vin0_pins: vin0 { 228 groups = "vin0_data8", "vin0_clk"; 229 function = "vin0"; 230 }; 231 232 mmcif0_pins: mmcif0 { 233 groups = "mmc_data8", "mmc_ctrl"; 234 function = "mmc"; 235 }; 236 237 sdhi0_pins: sd0 { 238 groups = "sdhi0_data4", "sdhi0_ctrl"; 239 function = "sdhi0"; 240 power-source = <3300>; 241 }; 242 243 sdhi0_pins_uhs: sd0_uhs { 244 groups = "sdhi0_data4", "sdhi0_ctrl"; 245 function = "sdhi0"; 246 power-source = <1800>; 247 }; 248 249 sdhi1_pins: sd1 { 250 groups = "sdhi1_data4", "sdhi1_ctrl"; 251 function = "sdhi1"; 252 power-source = <3300>; 253 }; 254 255 sdhi1_pins_uhs: sd1_uhs { 256 groups = "sdhi1_data4", "sdhi1_ctrl"; 257 function = "sdhi1"; 258 power-source = <1800>; 259 }; 260}; 261 262&cmt0 { 263 status = "okay"; 264}; 265 266&pfc { 267 qspi_pins: qspi { 268 groups = "qspi_ctrl", "qspi_data4"; 269 function = "qspi"; 270 }; 271}; 272 273ðer { 274 pinctrl-0 = <ðer_pins &phy1_pins>; 275 pinctrl-names = "default"; 276 277 phy-handle = <&phy1>; 278 renesas,ether-link-active-low; 279 status = "okay"; 280 281 phy1: ethernet-phy@1 { 282 reg = <1>; 283 interrupt-parent = <&irqc0>; 284 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 285 micrel,led-mode = <1>; 286 }; 287}; 288 289&mmcif0 { 290 pinctrl-0 = <&mmcif0_pins>; 291 pinctrl-names = "default"; 292 293 vmmc-supply = <&d3_3v>; 294 vqmmc-supply = <&d3_3v>; 295 bus-width = <8>; 296 non-removable; 297 status = "okay"; 298}; 299 300&sdhi0 { 301 pinctrl-0 = <&sdhi0_pins>; 302 pinctrl-1 = <&sdhi0_pins_uhs>; 303 pinctrl-names = "default", "state_uhs"; 304 305 vmmc-supply = <&vcc_sdhi0>; 306 vqmmc-supply = <&vccq_sdhi0>; 307 cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; 308 wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; 309 sd-uhs-sdr50; 310 sd-uhs-sdr104; 311 status = "okay"; 312}; 313 314&sdhi1 { 315 pinctrl-0 = <&sdhi1_pins>; 316 pinctrl-1 = <&sdhi1_pins_uhs>; 317 pinctrl-names = "default", "state_uhs"; 318 319 vmmc-supply = <&vcc_sdhi1>; 320 vqmmc-supply = <&vccq_sdhi1>; 321 cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; 322 wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; 323 sd-uhs-sdr50; 324 status = "okay"; 325}; 326 327&i2c1 { 328 pinctrl-0 = <&i2c1_pins>; 329 pinctrl-names = "default"; 330 331 status = "okay"; 332 clock-frequency = <400000>; 333 334 composite-in@20 { 335 compatible = "adi,adv7180"; 336 reg = <0x20>; 337 remote = <&vin0>; 338 339 port { 340 adv7180: endpoint { 341 bus-width = <8>; 342 remote-endpoint = <&vin0ep>; 343 }; 344 }; 345 }; 346}; 347 348&i2c4 { 349 pinctrl-0 = <&i2c4_pins>; 350 pinctrl-names = "i2c-exio4"; 351}; 352 353&vin0 { 354 status = "okay"; 355 pinctrl-0 = <&vin0_pins>; 356 pinctrl-names = "default"; 357 358 port { 359 #address-cells = <1>; 360 #size-cells = <0>; 361 362 vin0ep: endpoint { 363 remote-endpoint = <&adv7180>; 364 bus-width = <8>; 365 }; 366 }; 367}; 368 369&scif2 { 370 pinctrl-0 = <&scif2_pins>; 371 pinctrl-names = "default"; 372 373 status = "okay"; 374}; 375 376&scif_clk { 377 clock-frequency = <14745600>; 378}; 379 380&qspi { 381 pinctrl-0 = <&qspi_pins>; 382 pinctrl-names = "default"; 383 384 status = "okay"; 385 386 flash@0 { 387 compatible = "spansion,s25fl512s", "jedec,spi-nor"; 388 reg = <0>; 389 spi-max-frequency = <30000000>; 390 spi-tx-bus-width = <4>; 391 spi-rx-bus-width = <4>; 392 spi-cpol; 393 spi-cpha; 394 m25p,fast-read; 395 396 partitions { 397 compatible = "fixed-partitions"; 398 #address-cells = <1>; 399 #size-cells = <1>; 400 401 partition@0 { 402 label = "loader"; 403 reg = <0x00000000 0x00040000>; 404 read-only; 405 }; 406 partition@40000 { 407 label = "system"; 408 reg = <0x00040000 0x00040000>; 409 read-only; 410 }; 411 partition@80000 { 412 label = "user"; 413 reg = <0x00080000 0x03f80000>; 414 }; 415 }; 416 }; 417}; 418