1/* 2 * Copyright (c) 2013 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * This file is dual-licensed: you can use it either under the terms 6 * of the GPL or the X11 license, at your option. Note that this dual 7 * licensing only applies to this file, and not this project as a 8 * whole. 9 * 10 * a) This file is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This file is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include <dt-bindings/interrupt-controller/irq.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/soc/rockchip,boot-mode.h> 47 48/ { 49 #address-cells = <1>; 50 #size-cells = <1>; 51 52 interrupt-parent = <&gic>; 53 54 aliases { 55 ethernet0 = &emac; 56 i2c0 = &i2c0; 57 i2c1 = &i2c1; 58 i2c2 = &i2c2; 59 i2c3 = &i2c3; 60 i2c4 = &i2c4; 61 mshc0 = &emmc; 62 mshc1 = &mmc0; 63 mshc2 = &mmc1; 64 serial0 = &uart0; 65 serial1 = &uart1; 66 serial2 = &uart2; 67 serial3 = &uart3; 68 spi0 = &spi0; 69 spi1 = &spi1; 70 }; 71 72 amba { 73 compatible = "simple-bus"; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges; 77 78 dmac1_s: dma-controller@20018000 { 79 compatible = "arm,pl330", "arm,primecell"; 80 reg = <0x20018000 0x4000>; 81 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 83 #dma-cells = <1>; 84 arm,pl330-broken-no-flushp; 85 clocks = <&cru ACLK_DMA1>; 86 clock-names = "apb_pclk"; 87 }; 88 89 dmac1_ns: dma-controller@2001c000 { 90 compatible = "arm,pl330", "arm,primecell"; 91 reg = <0x2001c000 0x4000>; 92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 94 #dma-cells = <1>; 95 arm,pl330-broken-no-flushp; 96 clocks = <&cru ACLK_DMA1>; 97 clock-names = "apb_pclk"; 98 status = "disabled"; 99 }; 100 101 dmac2: dma-controller@20078000 { 102 compatible = "arm,pl330", "arm,primecell"; 103 reg = <0x20078000 0x4000>; 104 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 106 #dma-cells = <1>; 107 arm,pl330-broken-no-flushp; 108 clocks = <&cru ACLK_DMA2>; 109 clock-names = "apb_pclk"; 110 }; 111 }; 112 113 xin24m: oscillator { 114 compatible = "fixed-clock"; 115 clock-frequency = <24000000>; 116 #clock-cells = <0>; 117 clock-output-names = "xin24m"; 118 }; 119 120 L2: l2-cache-controller@10138000 { 121 compatible = "arm,pl310-cache"; 122 reg = <0x10138000 0x1000>; 123 cache-unified; 124 cache-level = <2>; 125 }; 126 127 scu@1013c000 { 128 compatible = "arm,cortex-a9-scu"; 129 reg = <0x1013c000 0x100>; 130 }; 131 132 global_timer: global-timer@1013c200 { 133 compatible = "arm,cortex-a9-global-timer"; 134 reg = <0x1013c200 0x20>; 135 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 136 clocks = <&cru CORE_PERI>; 137 }; 138 139 local_timer: local-timer@1013c600 { 140 compatible = "arm,cortex-a9-twd-timer"; 141 reg = <0x1013c600 0x20>; 142 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 143 clocks = <&cru CORE_PERI>; 144 }; 145 146 gic: interrupt-controller@1013d000 { 147 compatible = "arm,cortex-a9-gic"; 148 interrupt-controller; 149 #interrupt-cells = <3>; 150 reg = <0x1013d000 0x1000>, 151 <0x1013c100 0x0100>; 152 }; 153 154 uart0: serial@10124000 { 155 compatible = "snps,dw-apb-uart"; 156 reg = <0x10124000 0x400>; 157 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 158 reg-shift = <2>; 159 reg-io-width = <1>; 160 clock-names = "baudclk", "apb_pclk"; 161 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 162 status = "disabled"; 163 }; 164 165 uart1: serial@10126000 { 166 compatible = "snps,dw-apb-uart"; 167 reg = <0x10126000 0x400>; 168 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 169 reg-shift = <2>; 170 reg-io-width = <1>; 171 clock-names = "baudclk", "apb_pclk"; 172 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 173 status = "disabled"; 174 }; 175 176 usb_otg: usb@10180000 { 177 compatible = "rockchip,rk3066-usb", "snps,dwc2"; 178 reg = <0x10180000 0x40000>; 179 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&cru HCLK_OTG0>; 181 clock-names = "otg"; 182 dr_mode = "otg"; 183 g-np-tx-fifo-size = <16>; 184 g-rx-fifo-size = <275>; 185 g-tx-fifo-size = <256 128 128 64 64 32>; 186 phys = <&usbphy0>; 187 phy-names = "usb2-phy"; 188 status = "disabled"; 189 }; 190 191 usb_host: usb@101c0000 { 192 compatible = "snps,dwc2"; 193 reg = <0x101c0000 0x40000>; 194 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&cru HCLK_OTG1>; 196 clock-names = "otg"; 197 dr_mode = "host"; 198 phys = <&usbphy1>; 199 phy-names = "usb2-phy"; 200 status = "disabled"; 201 }; 202 203 emac: ethernet@10204000 { 204 compatible = "snps,arc-emac"; 205 reg = <0x10204000 0x3c>; 206 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 210 rockchip,grf = <&grf>; 211 212 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; 213 clock-names = "hclk", "macref"; 214 max-speed = <100>; 215 phy-mode = "rmii"; 216 217 status = "disabled"; 218 }; 219 220 mmc0: dwmmc@10214000 { 221 compatible = "rockchip,rk2928-dw-mshc"; 222 reg = <0x10214000 0x1000>; 223 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 225 clock-names = "biu", "ciu"; 226 dmas = <&dmac2 1>; 227 dma-names = "rx-tx"; 228 fifo-depth = <256>; 229 resets = <&cru SRST_SDMMC>; 230 reset-names = "reset"; 231 status = "disabled"; 232 }; 233 234 mmc1: dwmmc@10218000 { 235 compatible = "rockchip,rk2928-dw-mshc"; 236 reg = <0x10218000 0x1000>; 237 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; 239 clock-names = "biu", "ciu"; 240 dmas = <&dmac2 3>; 241 dma-names = "rx-tx"; 242 fifo-depth = <256>; 243 resets = <&cru SRST_SDIO>; 244 reset-names = "reset"; 245 status = "disabled"; 246 }; 247 248 emmc: dwmmc@1021c000 { 249 compatible = "rockchip,rk2928-dw-mshc"; 250 reg = <0x1021c000 0x1000>; 251 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 253 clock-names = "biu", "ciu"; 254 dmas = <&dmac2 4>; 255 dma-names = "rx-tx"; 256 fifo-depth = <256>; 257 resets = <&cru SRST_EMMC>; 258 reset-names = "reset"; 259 status = "disabled"; 260 }; 261 262 pmu: pmu@20004000 { 263 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; 264 reg = <0x20004000 0x100>; 265 266 reboot-mode { 267 compatible = "syscon-reboot-mode"; 268 offset = <0x40>; 269 mode-normal = <BOOT_NORMAL>; 270 mode-recovery = <BOOT_RECOVERY>; 271 mode-bootloader = <BOOT_FASTBOOT>; 272 mode-loader = <BOOT_BL_DOWNLOAD>; 273 }; 274 }; 275 276 grf: grf@20008000 { 277 compatible = "syscon"; 278 reg = <0x20008000 0x200>; 279 }; 280 281 i2c0: i2c@2002d000 { 282 compatible = "rockchip,rk3066-i2c"; 283 reg = <0x2002d000 0x1000>; 284 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 288 rockchip,grf = <&grf>; 289 290 clock-names = "i2c"; 291 clocks = <&cru PCLK_I2C0>; 292 293 status = "disabled"; 294 }; 295 296 i2c1: i2c@2002f000 { 297 compatible = "rockchip,rk3066-i2c"; 298 reg = <0x2002f000 0x1000>; 299 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 303 rockchip,grf = <&grf>; 304 305 clocks = <&cru PCLK_I2C1>; 306 clock-names = "i2c"; 307 308 status = "disabled"; 309 }; 310 311 pwm0: pwm@20030000 { 312 compatible = "rockchip,rk2928-pwm"; 313 reg = <0x20030000 0x10>; 314 #pwm-cells = <2>; 315 clocks = <&cru PCLK_PWM01>; 316 status = "disabled"; 317 }; 318 319 pwm1: pwm@20030010 { 320 compatible = "rockchip,rk2928-pwm"; 321 reg = <0x20030010 0x10>; 322 #pwm-cells = <2>; 323 clocks = <&cru PCLK_PWM01>; 324 status = "disabled"; 325 }; 326 327 wdt: watchdog@2004c000 { 328 compatible = "snps,dw-wdt"; 329 reg = <0x2004c000 0x100>; 330 clocks = <&cru PCLK_WDT>; 331 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 332 status = "disabled"; 333 }; 334 335 pwm2: pwm@20050020 { 336 compatible = "rockchip,rk2928-pwm"; 337 reg = <0x20050020 0x10>; 338 #pwm-cells = <2>; 339 clocks = <&cru PCLK_PWM23>; 340 status = "disabled"; 341 }; 342 343 pwm3: pwm@20050030 { 344 compatible = "rockchip,rk2928-pwm"; 345 reg = <0x20050030 0x10>; 346 #pwm-cells = <2>; 347 clocks = <&cru PCLK_PWM23>; 348 status = "disabled"; 349 }; 350 351 i2c2: i2c@20056000 { 352 compatible = "rockchip,rk3066-i2c"; 353 reg = <0x20056000 0x1000>; 354 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 358 rockchip,grf = <&grf>; 359 360 clocks = <&cru PCLK_I2C2>; 361 clock-names = "i2c"; 362 363 status = "disabled"; 364 }; 365 366 i2c3: i2c@2005a000 { 367 compatible = "rockchip,rk3066-i2c"; 368 reg = <0x2005a000 0x1000>; 369 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 373 rockchip,grf = <&grf>; 374 375 clocks = <&cru PCLK_I2C3>; 376 clock-names = "i2c"; 377 378 status = "disabled"; 379 }; 380 381 i2c4: i2c@2005e000 { 382 compatible = "rockchip,rk3066-i2c"; 383 reg = <0x2005e000 0x1000>; 384 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 388 rockchip,grf = <&grf>; 389 390 clocks = <&cru PCLK_I2C4>; 391 clock-names = "i2c"; 392 393 status = "disabled"; 394 }; 395 396 uart2: serial@20064000 { 397 compatible = "snps,dw-apb-uart"; 398 reg = <0x20064000 0x400>; 399 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 400 reg-shift = <2>; 401 reg-io-width = <1>; 402 clock-names = "baudclk", "apb_pclk"; 403 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 404 status = "disabled"; 405 }; 406 407 uart3: serial@20068000 { 408 compatible = "snps,dw-apb-uart"; 409 reg = <0x20068000 0x400>; 410 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 411 reg-shift = <2>; 412 reg-io-width = <1>; 413 clock-names = "baudclk", "apb_pclk"; 414 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 415 status = "disabled"; 416 }; 417 418 saradc: saradc@2006c000 { 419 compatible = "rockchip,saradc"; 420 reg = <0x2006c000 0x100>; 421 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 422 #io-channel-cells = <1>; 423 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 424 clock-names = "saradc", "apb_pclk"; 425 resets = <&cru SRST_SARADC>; 426 reset-names = "saradc-apb"; 427 status = "disabled"; 428 }; 429 430 spi0: spi@20070000 { 431 compatible = "rockchip,rk3066-spi"; 432 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 433 clock-names = "spiclk", "apb_pclk"; 434 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 435 reg = <0x20070000 0x1000>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 dmas = <&dmac2 10>, <&dmac2 11>; 439 dma-names = "tx", "rx"; 440 status = "disabled"; 441 }; 442 443 spi1: spi@20074000 { 444 compatible = "rockchip,rk3066-spi"; 445 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 446 clock-names = "spiclk", "apb_pclk"; 447 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 448 reg = <0x20074000 0x1000>; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 dmas = <&dmac2 12>, <&dmac2 13>; 452 dma-names = "tx", "rx"; 453 status = "disabled"; 454 }; 455}; 456