1/* 2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC 3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC 4 * 5 * Copyright (C) 2013 Atmel, 6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> 7 * 8 * Licensed under GPLv2 or later. 9 */ 10 11#include "skeleton.dtsi" 12#include <dt-bindings/dma/at91.h> 13#include <dt-bindings/pinctrl/at91.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/clock/at91.h> 17 18/ { 19 model = "Atmel SAMA5D3 family SoC"; 20 compatible = "atmel,sama5d3", "atmel,sama5"; 21 interrupt-parent = <&aic>; 22 23 aliases { 24 serial0 = &dbgu; 25 serial1 = &usart0; 26 serial2 = &usart1; 27 serial3 = &usart2; 28 serial4 = &usart3; 29 serial5 = &uart0; 30 gpio0 = &pioA; 31 gpio1 = &pioB; 32 gpio2 = &pioC; 33 gpio3 = &pioD; 34 gpio4 = &pioE; 35 tcb0 = &tcb0; 36 i2c0 = &i2c0; 37 i2c1 = &i2c1; 38 i2c2 = &i2c2; 39 ssc0 = &ssc0; 40 ssc1 = &ssc1; 41 pwm0 = &pwm0; 42 }; 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a5"; 49 reg = <0x0>; 50 }; 51 }; 52 53 pmu { 54 compatible = "arm,cortex-a5-pmu"; 55 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; 56 }; 57 58 memory { 59 reg = <0x20000000 0x8000000>; 60 }; 61 62 clocks { 63 slow_xtal: slow_xtal { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <0>; 67 }; 68 69 main_xtal: main_xtal { 70 compatible = "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <0>; 73 }; 74 75 adc_op_clk: adc_op_clk{ 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <1000000>; 79 }; 80 }; 81 82 sram: sram@00300000 { 83 compatible = "mmio-sram"; 84 reg = <0x00300000 0x20000>; 85 }; 86 87 ahb { 88 compatible = "simple-bus"; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 ranges; 92 93 apb { 94 compatible = "simple-bus"; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 ranges; 98 99 mmc0: mmc@f0000000 { 100 compatible = "atmel,hsmci"; 101 reg = <0xf0000000 0x600>; 102 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; 103 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; 104 dma-names = "rxtx"; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; 107 status = "disabled"; 108 #address-cells = <1>; 109 #size-cells = <0>; 110 clocks = <&mci0_clk>; 111 clock-names = "mci_clk"; 112 }; 113 114 spi0: spi@f0004000 { 115 #address-cells = <1>; 116 #size-cells = <0>; 117 compatible = "atmel,at91rm9200-spi"; 118 reg = <0xf0004000 0x100>; 119 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; 120 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, 121 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; 122 dma-names = "tx", "rx"; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_spi0>; 125 clocks = <&spi0_clk>; 126 clock-names = "spi_clk"; 127 status = "disabled"; 128 }; 129 130 ssc0: ssc@f0008000 { 131 compatible = "atmel,at91sam9g45-ssc"; 132 reg = <0xf0008000 0x4000>; 133 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; 134 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>, 135 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>; 136 dma-names = "tx", "rx"; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 139 clocks = <&ssc0_clk>; 140 clock-names = "pclk"; 141 status = "disabled"; 142 }; 143 144 tcb0: timer@f0010000 { 145 compatible = "atmel,at91sam9x5-tcb"; 146 reg = <0xf0010000 0x100>; 147 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 148 clocks = <&tcb0_clk>, <&clk32k>; 149 clock-names = "t0_clk", "slow_clk"; 150 }; 151 152 i2c0: i2c@f0014000 { 153 compatible = "atmel,at91sam9x5-i2c"; 154 reg = <0xf0014000 0x4000>; 155 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; 156 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, 157 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; 158 dma-names = "tx", "rx"; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_i2c0>; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 clocks = <&twi0_clk>; 164 status = "disabled"; 165 }; 166 167 i2c1: i2c@f0018000 { 168 compatible = "atmel,at91sam9x5-i2c"; 169 reg = <0xf0018000 0x4000>; 170 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; 171 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, 172 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; 173 dma-names = "tx", "rx"; 174 pinctrl-names = "default"; 175 pinctrl-0 = <&pinctrl_i2c1>; 176 #address-cells = <1>; 177 #size-cells = <0>; 178 clocks = <&twi1_clk>; 179 status = "disabled"; 180 }; 181 182 usart0: serial@f001c000 { 183 compatible = "atmel,at91sam9260-usart"; 184 reg = <0xf001c000 0x100>; 185 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; 186 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, 187 <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 188 dma-names = "tx", "rx"; 189 pinctrl-names = "default"; 190 pinctrl-0 = <&pinctrl_usart0>; 191 clocks = <&usart0_clk>; 192 clock-names = "usart"; 193 status = "disabled"; 194 }; 195 196 usart1: serial@f0020000 { 197 compatible = "atmel,at91sam9260-usart"; 198 reg = <0xf0020000 0x100>; 199 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; 200 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, 201 <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 202 dma-names = "tx", "rx"; 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_usart1>; 205 clocks = <&usart1_clk>; 206 clock-names = "usart"; 207 status = "disabled"; 208 }; 209 210 uart0: serial@f0024000 { 211 compatible = "atmel,at91sam9260-usart"; 212 reg = <0xf0024000 0x100>; 213 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_uart0>; 216 clocks = <&uart0_clk>; 217 clock-names = "usart"; 218 status = "disabled"; 219 }; 220 221 pwm0: pwm@f002c000 { 222 compatible = "atmel,sama5d3-pwm"; 223 reg = <0xf002c000 0x300>; 224 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; 225 #pwm-cells = <3>; 226 clocks = <&pwm_clk>; 227 status = "disabled"; 228 }; 229 230 isi: isi@f0034000 { 231 compatible = "atmel,at91sam9g45-isi"; 232 reg = <0xf0034000 0x4000>; 233 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_isi_data_0_7>; 236 clocks = <&isi_clk>; 237 clock-names = "isi_clk"; 238 status = "disabled"; 239 port { 240 #address-cells = <1>; 241 #size-cells = <0>; 242 }; 243 }; 244 245 sfr: sfr@f0038000 { 246 compatible = "atmel,sama5d3-sfr", "syscon"; 247 reg = <0xf0038000 0x60>; 248 }; 249 250 mmc1: mmc@f8000000 { 251 compatible = "atmel,hsmci"; 252 reg = <0xf8000000 0x600>; 253 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; 254 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; 255 dma-names = "rxtx"; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; 258 status = "disabled"; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 clocks = <&mci1_clk>; 262 clock-names = "mci_clk"; 263 }; 264 265 spi1: spi@f8008000 { 266 #address-cells = <1>; 267 #size-cells = <0>; 268 compatible = "atmel,at91rm9200-spi"; 269 reg = <0xf8008000 0x100>; 270 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; 271 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, 272 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; 273 dma-names = "tx", "rx"; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&pinctrl_spi1>; 276 clocks = <&spi1_clk>; 277 clock-names = "spi_clk"; 278 status = "disabled"; 279 }; 280 281 ssc1: ssc@f800c000 { 282 compatible = "atmel,at91sam9g45-ssc"; 283 reg = <0xf800c000 0x4000>; 284 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; 285 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>, 286 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>; 287 dma-names = "tx", "rx"; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 290 clocks = <&ssc1_clk>; 291 clock-names = "pclk"; 292 status = "disabled"; 293 }; 294 295 adc0: adc@f8018000 { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 compatible = "atmel,at91sam9x5-adc"; 299 reg = <0xf8018000 0x100>; 300 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; 301 pinctrl-names = "default"; 302 pinctrl-0 = < 303 &pinctrl_adc0_adtrg 304 &pinctrl_adc0_ad0 305 &pinctrl_adc0_ad1 306 &pinctrl_adc0_ad2 307 &pinctrl_adc0_ad3 308 &pinctrl_adc0_ad4 309 &pinctrl_adc0_ad5 310 &pinctrl_adc0_ad6 311 &pinctrl_adc0_ad7 312 &pinctrl_adc0_ad8 313 &pinctrl_adc0_ad9 314 &pinctrl_adc0_ad10 315 &pinctrl_adc0_ad11 316 >; 317 clocks = <&adc_clk>, 318 <&adc_op_clk>; 319 clock-names = "adc_clk", "adc_op_clk"; 320 atmel,adc-channels-used = <0xfff>; 321 atmel,adc-startup-time = <40>; 322 atmel,adc-use-external-triggers; 323 atmel,adc-vref = <3000>; 324 atmel,adc-res = <10 12>; 325 atmel,adc-sample-hold-time = <11>; 326 atmel,adc-res-names = "lowres", "highres"; 327 status = "disabled"; 328 329 trigger0 { 330 trigger-name = "external-rising"; 331 trigger-value = <0x1>; 332 trigger-external; 333 }; 334 trigger1 { 335 trigger-name = "external-falling"; 336 trigger-value = <0x2>; 337 trigger-external; 338 }; 339 trigger2 { 340 trigger-name = "external-any"; 341 trigger-value = <0x3>; 342 trigger-external; 343 }; 344 trigger3 { 345 trigger-name = "continuous"; 346 trigger-value = <0x6>; 347 }; 348 }; 349 350 i2c2: i2c@f801c000 { 351 compatible = "atmel,at91sam9x5-i2c"; 352 reg = <0xf801c000 0x4000>; 353 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; 354 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, 355 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; 356 dma-names = "tx", "rx"; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&pinctrl_i2c2>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 clocks = <&twi2_clk>; 362 status = "disabled"; 363 }; 364 365 usart2: serial@f8020000 { 366 compatible = "atmel,at91sam9260-usart"; 367 reg = <0xf8020000 0x100>; 368 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 369 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, 370 <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 371 dma-names = "tx", "rx"; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&pinctrl_usart2>; 374 clocks = <&usart2_clk>; 375 clock-names = "usart"; 376 status = "disabled"; 377 }; 378 379 usart3: serial@f8024000 { 380 compatible = "atmel,at91sam9260-usart"; 381 reg = <0xf8024000 0x100>; 382 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 383 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, 384 <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 385 dma-names = "tx", "rx"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_usart3>; 388 clocks = <&usart3_clk>; 389 clock-names = "usart"; 390 status = "disabled"; 391 }; 392 393 sha@f8034000 { 394 compatible = "atmel,at91sam9g46-sha"; 395 reg = <0xf8034000 0x100>; 396 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; 397 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; 398 dma-names = "tx"; 399 clocks = <&sha_clk>; 400 clock-names = "sha_clk"; 401 }; 402 403 aes@f8038000 { 404 compatible = "atmel,at91sam9g46-aes"; 405 reg = <0xf8038000 0x100>; 406 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; 407 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, 408 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; 409 dma-names = "tx", "rx"; 410 clocks = <&aes_clk>; 411 clock-names = "aes_clk"; 412 }; 413 414 tdes@f803c000 { 415 compatible = "atmel,at91sam9g46-tdes"; 416 reg = <0xf803c000 0x100>; 417 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; 418 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, 419 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; 420 dma-names = "tx", "rx"; 421 clocks = <&tdes_clk>; 422 clock-names = "tdes_clk"; 423 }; 424 425 trng@f8040000 { 426 compatible = "atmel,at91sam9g45-trng"; 427 reg = <0xf8040000 0x100>; 428 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 429 clocks = <&trng_clk>; 430 }; 431 432 hsmc: hsmc@ffffc000 { 433 compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; 434 reg = <0xffffc000 0x1000>; 435 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; 436 clocks = <&hsmc_clk>; 437 #address-cells = <1>; 438 #size-cells = <1>; 439 ranges; 440 441 pmecc: ecc-engine@ffffc070 { 442 compatible = "atmel,at91sam9g45-pmecc"; 443 reg = <0xffffc070 0x490>, 444 <0xffffc500 0x100>; 445 }; 446 }; 447 448 dma0: dma-controller@ffffe600 { 449 compatible = "atmel,at91sam9g45-dma"; 450 reg = <0xffffe600 0x200>; 451 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; 452 #dma-cells = <2>; 453 clocks = <&dma0_clk>; 454 clock-names = "dma_clk"; 455 }; 456 457 dma1: dma-controller@ffffe800 { 458 compatible = "atmel,at91sam9g45-dma"; 459 reg = <0xffffe800 0x200>; 460 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 461 #dma-cells = <2>; 462 clocks = <&dma1_clk>; 463 clock-names = "dma_clk"; 464 }; 465 466 ramc0: ramc@ffffea00 { 467 compatible = "atmel,sama5d3-ddramc"; 468 reg = <0xffffea00 0x200>; 469 clocks = <&ddrck>, <&mpddr_clk>; 470 clock-names = "ddrck", "mpddr"; 471 }; 472 473 dbgu: serial@ffffee00 { 474 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 475 reg = <0xffffee00 0x200>; 476 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; 477 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, 478 <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 479 dma-names = "tx", "rx"; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&pinctrl_dbgu>; 482 clocks = <&dbgu_clk>; 483 clock-names = "usart"; 484 status = "disabled"; 485 }; 486 487 aic: interrupt-controller@fffff000 { 488 #interrupt-cells = <3>; 489 compatible = "atmel,sama5d3-aic"; 490 interrupt-controller; 491 reg = <0xfffff000 0x200>; 492 atmel,external-irqs = <47>; 493 }; 494 495 pinctrl@fffff200 { 496 #address-cells = <1>; 497 #size-cells = <1>; 498 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; 499 ranges = <0xfffff200 0xfffff200 0xa00>; 500 atmel,mux-mask = < 501 /* A B C */ 502 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ 503 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ 504 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ 505 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ 506 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ 507 >; 508 509 /* shared pinctrl settings */ 510 adc0 { 511 pinctrl_adc0_adtrg: adc0_adtrg { 512 atmel,pins = 513 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */ 514 }; 515 pinctrl_adc0_ad0: adc0_ad0 { 516 atmel,pins = 517 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */ 518 }; 519 pinctrl_adc0_ad1: adc0_ad1 { 520 atmel,pins = 521 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */ 522 }; 523 pinctrl_adc0_ad2: adc0_ad2 { 524 atmel,pins = 525 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */ 526 }; 527 pinctrl_adc0_ad3: adc0_ad3 { 528 atmel,pins = 529 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */ 530 }; 531 pinctrl_adc0_ad4: adc0_ad4 { 532 atmel,pins = 533 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */ 534 }; 535 pinctrl_adc0_ad5: adc0_ad5 { 536 atmel,pins = 537 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */ 538 }; 539 pinctrl_adc0_ad6: adc0_ad6 { 540 atmel,pins = 541 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */ 542 }; 543 pinctrl_adc0_ad7: adc0_ad7 { 544 atmel,pins = 545 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */ 546 }; 547 pinctrl_adc0_ad8: adc0_ad8 { 548 atmel,pins = 549 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */ 550 }; 551 pinctrl_adc0_ad9: adc0_ad9 { 552 atmel,pins = 553 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */ 554 }; 555 pinctrl_adc0_ad10: adc0_ad10 { 556 atmel,pins = 557 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */ 558 }; 559 pinctrl_adc0_ad11: adc0_ad11 { 560 atmel,pins = 561 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */ 562 }; 563 }; 564 565 dbgu { 566 pinctrl_dbgu: dbgu-0 { 567 atmel,pins = 568 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 569 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 570 }; 571 }; 572 573 ebi { 574 pinctrl_ebi_addr: ebi-addr-0 { 575 atmel,pins = 576 <AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE 577 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE 578 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE 579 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE 580 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE 581 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE 582 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE 583 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE 584 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE 585 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE 586 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE 587 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE 588 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE 589 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE 590 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE 591 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE 592 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE 593 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE 594 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE 595 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE 596 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE 597 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE 598 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; 599 }; 600 601 pinctrl_ebi_nand_addr: ebi-addr-1 { 602 atmel,pins = 603 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE 604 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; 605 }; 606 607 pinctrl_ebi_cs0: ebi-cs0-0 { 608 atmel,pins = 609 <AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; 610 }; 611 612 pinctrl_ebi_cs1: ebi-cs1-0 { 613 atmel,pins = 614 <AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; 615 }; 616 617 pinctrl_ebi_cs2: ebi-cs2-0 { 618 atmel,pins = 619 <AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; 620 }; 621 622 pinctrl_ebi_nwait: ebi-nwait-0 { 623 atmel,pins = 624 <AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 625 }; 626 627 pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 { 628 atmel,pins = 629 <AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 630 }; 631 }; 632 633 i2c0 { 634 pinctrl_i2c0: i2c0-0 { 635 atmel,pins = 636 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ 637 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ 638 }; 639 }; 640 641 i2c1 { 642 pinctrl_i2c1: i2c1-0 { 643 atmel,pins = 644 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ 645 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ 646 }; 647 }; 648 649 i2c2 { 650 pinctrl_i2c2: i2c2-0 { 651 atmel,pins = 652 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */ 653 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ 654 }; 655 }; 656 657 isi { 658 pinctrl_isi_data_0_7: isi-0-data-0-7 { 659 atmel,pins = 660 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ 661 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ 662 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ 663 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ 664 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ 665 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ 666 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ 667 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ 668 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ 669 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ 670 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ 671 }; 672 673 pinctrl_isi_data_8_9: isi-0-data-8-9 { 674 atmel,pins = 675 <AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ 676 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ 677 }; 678 679 pinctrl_isi_data_10_11: isi-0-data-10-11 { 680 atmel,pins = 681 <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC27 periph C ISI_PD10, conflicts with SPI1_NPCS2, TWCK1 */ 682 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */ 683 }; 684 }; 685 686 mmc0 { 687 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { 688 atmel,pins = 689 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */ 690 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */ 691 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */ 692 }; 693 pinctrl_mmc0_dat1_3: mmc0_dat1_3 { 694 atmel,pins = 695 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */ 696 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */ 697 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */ 698 }; 699 pinctrl_mmc0_dat4_7: mmc0_dat4_7 { 700 atmel,pins = 701 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ 702 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ 703 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ 704 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ 705 }; 706 }; 707 708 mmc1 { 709 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { 710 atmel,pins = 711 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */ 712 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ 713 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ 714 }; 715 pinctrl_mmc1_dat1_3: mmc1_dat1_3 { 716 atmel,pins = 717 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ 718 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ 719 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ 720 }; 721 }; 722 723 nand0 { 724 pinctrl_nand0_ale_cle: nand0_ale_cle-0 { 725 atmel,pins = 726 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */ 727 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */ 728 }; 729 }; 730 731 pwm0 { 732 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { 733 atmel,pins = 734 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */ 735 }; 736 pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { 737 atmel,pins = 738 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */ 739 }; 740 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { 741 atmel,pins = 742 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */ 743 }; 744 pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { 745 atmel,pins = 746 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */ 747 }; 748 749 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { 750 atmel,pins = 751 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */ 752 }; 753 pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { 754 atmel,pins = 755 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */ 756 }; 757 pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { 758 atmel,pins = 759 <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */ 760 }; 761 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { 762 atmel,pins = 763 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */ 764 }; 765 pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { 766 atmel,pins = 767 <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */ 768 }; 769 pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { 770 atmel,pins = 771 <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */ 772 }; 773 774 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { 775 atmel,pins = 776 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */ 777 }; 778 pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { 779 atmel,pins = 780 <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */ 781 }; 782 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { 783 atmel,pins = 784 <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */ 785 }; 786 pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { 787 atmel,pins = 788 <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */ 789 }; 790 791 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { 792 atmel,pins = 793 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */ 794 }; 795 pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { 796 atmel,pins = 797 <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */ 798 }; 799 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { 800 atmel,pins = 801 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */ 802 }; 803 pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { 804 atmel,pins = 805 <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */ 806 }; 807 }; 808 809 spi0 { 810 pinctrl_spi0: spi0-0 { 811 atmel,pins = 812 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */ 813 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */ 814 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */ 815 }; 816 }; 817 818 spi1 { 819 pinctrl_spi1: spi1-0 { 820 atmel,pins = 821 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */ 822 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */ 823 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */ 824 }; 825 }; 826 827 ssc0 { 828 pinctrl_ssc0_tx: ssc0_tx { 829 atmel,pins = 830 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */ 831 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */ 832 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */ 833 }; 834 835 pinctrl_ssc0_rx: ssc0_rx { 836 atmel,pins = 837 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */ 838 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */ 839 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */ 840 }; 841 }; 842 843 ssc1 { 844 pinctrl_ssc1_tx: ssc1_tx { 845 atmel,pins = 846 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */ 847 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */ 848 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */ 849 }; 850 851 pinctrl_ssc1_rx: ssc1_rx { 852 atmel,pins = 853 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */ 854 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */ 855 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */ 856 }; 857 }; 858 859 uart0 { 860 pinctrl_uart0: uart0-0 { 861 atmel,pins = 862 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* conflicts with PWMFI2, ISI_D8 */ 863 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with ISI_PCK */ 864 }; 865 }; 866 867 uart1 { 868 pinctrl_uart1: uart1-0 { 869 atmel,pins = 870 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* conflicts with TWD0, ISI_VSYNC */ 871 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* conflicts with TWCK0, ISI_HSYNC */ 872 }; 873 }; 874 875 usart0 { 876 pinctrl_usart0: usart0-0 { 877 atmel,pins = 878 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */ 879 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */ 880 }; 881 882 pinctrl_usart0_rts_cts: usart0_rts_cts-0 { 883 atmel,pins = 884 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ 885 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ 886 }; 887 }; 888 889 usart1 { 890 pinctrl_usart1: usart1-0 { 891 atmel,pins = 892 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */ 893 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */ 894 }; 895 896 pinctrl_usart1_rts_cts: usart1_rts_cts-0 { 897 atmel,pins = 898 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */ 899 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */ 900 }; 901 }; 902 903 usart2 { 904 pinctrl_usart2: usart2-0 { 905 atmel,pins = 906 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */ 907 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */ 908 }; 909 910 pinctrl_usart2_rts_cts: usart2_rts_cts-0 { 911 atmel,pins = 912 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */ 913 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */ 914 }; 915 }; 916 917 usart3 { 918 pinctrl_usart3: usart3-0 { 919 atmel,pins = 920 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */ 921 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */ 922 }; 923 924 pinctrl_usart3_rts_cts: usart3_rts_cts-0 { 925 atmel,pins = 926 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */ 927 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */ 928 }; 929 }; 930 931 932 pioA: gpio@fffff200 { 933 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 934 reg = <0xfffff200 0x100>; 935 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; 936 #gpio-cells = <2>; 937 gpio-controller; 938 interrupt-controller; 939 #interrupt-cells = <2>; 940 clocks = <&pioA_clk>; 941 }; 942 943 pioB: gpio@fffff400 { 944 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 945 reg = <0xfffff400 0x100>; 946 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; 947 #gpio-cells = <2>; 948 gpio-controller; 949 interrupt-controller; 950 #interrupt-cells = <2>; 951 clocks = <&pioB_clk>; 952 }; 953 954 pioC: gpio@fffff600 { 955 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 956 reg = <0xfffff600 0x100>; 957 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; 958 #gpio-cells = <2>; 959 gpio-controller; 960 interrupt-controller; 961 #interrupt-cells = <2>; 962 clocks = <&pioC_clk>; 963 }; 964 965 pioD: gpio@fffff800 { 966 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 967 reg = <0xfffff800 0x100>; 968 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; 969 #gpio-cells = <2>; 970 gpio-controller; 971 interrupt-controller; 972 #interrupt-cells = <2>; 973 clocks = <&pioD_clk>; 974 }; 975 976 pioE: gpio@fffffa00 { 977 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 978 reg = <0xfffffa00 0x100>; 979 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; 980 #gpio-cells = <2>; 981 gpio-controller; 982 interrupt-controller; 983 #interrupt-cells = <2>; 984 clocks = <&pioE_clk>; 985 }; 986 }; 987 988 pmc: pmc@fffffc00 { 989 compatible = "atmel,sama5d3-pmc", "syscon"; 990 reg = <0xfffffc00 0x120>; 991 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 992 interrupt-controller; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 #interrupt-cells = <1>; 996 997 main_rc_osc: main_rc_osc { 998 compatible = "atmel,at91sam9x5-clk-main-rc-osc"; 999 #clock-cells = <0>; 1000 interrupt-parent = <&pmc>; 1001 interrupts = <AT91_PMC_MOSCRCS>; 1002 clock-frequency = <12000000>; 1003 clock-accuracy = <50000000>; 1004 }; 1005 1006 main_osc: main_osc { 1007 compatible = "atmel,at91rm9200-clk-main-osc"; 1008 #clock-cells = <0>; 1009 interrupt-parent = <&pmc>; 1010 interrupts = <AT91_PMC_MOSCS>; 1011 clocks = <&main_xtal>; 1012 }; 1013 1014 main: mainck { 1015 compatible = "atmel,at91sam9x5-clk-main"; 1016 #clock-cells = <0>; 1017 interrupt-parent = <&pmc>; 1018 interrupts = <AT91_PMC_MOSCSELS>; 1019 clocks = <&main_rc_osc &main_osc>; 1020 }; 1021 1022 plla: pllack { 1023 compatible = "atmel,sama5d3-clk-pll"; 1024 #clock-cells = <0>; 1025 interrupt-parent = <&pmc>; 1026 interrupts = <AT91_PMC_LOCKA>; 1027 clocks = <&main>; 1028 reg = <0>; 1029 atmel,clk-input-range = <8000000 50000000>; 1030 #atmel,pll-clk-output-range-cells = <4>; 1031 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; 1032 }; 1033 1034 plladiv: plladivck { 1035 compatible = "atmel,at91sam9x5-clk-plldiv"; 1036 #clock-cells = <0>; 1037 clocks = <&plla>; 1038 }; 1039 1040 utmi: utmick { 1041 compatible = "atmel,at91sam9x5-clk-utmi"; 1042 #clock-cells = <0>; 1043 interrupt-parent = <&pmc>; 1044 interrupts = <AT91_PMC_LOCKU>; 1045 clocks = <&main>; 1046 }; 1047 1048 mck: masterck { 1049 compatible = "atmel,at91sam9x5-clk-master"; 1050 #clock-cells = <0>; 1051 interrupt-parent = <&pmc>; 1052 interrupts = <AT91_PMC_MCKRDY>; 1053 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; 1054 atmel,clk-output-range = <0 166000000>; 1055 atmel,clk-divisors = <1 2 4 3>; 1056 }; 1057 1058 usb: usbck { 1059 compatible = "atmel,at91sam9x5-clk-usb"; 1060 #clock-cells = <0>; 1061 clocks = <&plladiv>, <&utmi>; 1062 }; 1063 1064 prog: progck { 1065 compatible = "atmel,at91sam9x5-clk-programmable"; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 interrupt-parent = <&pmc>; 1069 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; 1070 1071 prog0: prog0 { 1072 #clock-cells = <0>; 1073 reg = <0>; 1074 interrupts = <AT91_PMC_PCKRDY(0)>; 1075 }; 1076 1077 prog1: prog1 { 1078 #clock-cells = <0>; 1079 reg = <1>; 1080 interrupts = <AT91_PMC_PCKRDY(1)>; 1081 }; 1082 1083 prog2: prog2 { 1084 #clock-cells = <0>; 1085 reg = <2>; 1086 interrupts = <AT91_PMC_PCKRDY(2)>; 1087 }; 1088 }; 1089 1090 smd: smdclk { 1091 compatible = "atmel,at91sam9x5-clk-smd"; 1092 #clock-cells = <0>; 1093 clocks = <&plladiv>, <&utmi>; 1094 }; 1095 1096 systemck { 1097 compatible = "atmel,at91rm9200-clk-system"; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 1101 ddrck: ddrck { 1102 #clock-cells = <0>; 1103 reg = <2>; 1104 clocks = <&mck>; 1105 }; 1106 1107 smdck: smdck { 1108 #clock-cells = <0>; 1109 reg = <4>; 1110 clocks = <&smd>; 1111 }; 1112 1113 uhpck: uhpck { 1114 #clock-cells = <0>; 1115 reg = <6>; 1116 clocks = <&usb>; 1117 }; 1118 1119 udpck: udpck { 1120 #clock-cells = <0>; 1121 reg = <7>; 1122 clocks = <&usb>; 1123 }; 1124 1125 pck0: pck0 { 1126 #clock-cells = <0>; 1127 reg = <8>; 1128 clocks = <&prog0>; 1129 }; 1130 1131 pck1: pck1 { 1132 #clock-cells = <0>; 1133 reg = <9>; 1134 clocks = <&prog1>; 1135 }; 1136 1137 pck2: pck2 { 1138 #clock-cells = <0>; 1139 reg = <10>; 1140 clocks = <&prog2>; 1141 }; 1142 }; 1143 1144 periphck { 1145 compatible = "atmel,at91sam9x5-clk-peripheral"; 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 clocks = <&mck>; 1149 1150 dbgu_clk: dbgu_clk { 1151 #clock-cells = <0>; 1152 reg = <2>; 1153 }; 1154 1155 hsmc_clk: hsmc_clk { 1156 #clock-cells = <0>; 1157 reg = <5>; 1158 }; 1159 1160 pioA_clk: pioA_clk { 1161 #clock-cells = <0>; 1162 reg = <6>; 1163 }; 1164 1165 pioB_clk: pioB_clk { 1166 #clock-cells = <0>; 1167 reg = <7>; 1168 }; 1169 1170 pioC_clk: pioC_clk { 1171 #clock-cells = <0>; 1172 reg = <8>; 1173 }; 1174 1175 pioD_clk: pioD_clk { 1176 #clock-cells = <0>; 1177 reg = <9>; 1178 }; 1179 1180 pioE_clk: pioE_clk { 1181 #clock-cells = <0>; 1182 reg = <10>; 1183 }; 1184 1185 usart0_clk: usart0_clk { 1186 #clock-cells = <0>; 1187 reg = <12>; 1188 atmel,clk-output-range = <0 83000000>; 1189 }; 1190 1191 usart1_clk: usart1_clk { 1192 #clock-cells = <0>; 1193 reg = <13>; 1194 atmel,clk-output-range = <0 83000000>; 1195 }; 1196 1197 usart2_clk: usart2_clk { 1198 #clock-cells = <0>; 1199 reg = <14>; 1200 atmel,clk-output-range = <0 83000000>; 1201 }; 1202 1203 usart3_clk: usart3_clk { 1204 #clock-cells = <0>; 1205 reg = <15>; 1206 atmel,clk-output-range = <0 83000000>; 1207 }; 1208 1209 uart0_clk: uart0_clk { 1210 #clock-cells = <0>; 1211 reg = <16>; 1212 atmel,clk-output-range = <0 83000000>; 1213 }; 1214 1215 twi0_clk: twi0_clk { 1216 reg = <18>; 1217 #clock-cells = <0>; 1218 atmel,clk-output-range = <0 41500000>; 1219 }; 1220 1221 twi1_clk: twi1_clk { 1222 #clock-cells = <0>; 1223 reg = <19>; 1224 atmel,clk-output-range = <0 41500000>; 1225 }; 1226 1227 twi2_clk: twi2_clk { 1228 #clock-cells = <0>; 1229 reg = <20>; 1230 atmel,clk-output-range = <0 41500000>; 1231 }; 1232 1233 mci0_clk: mci0_clk { 1234 #clock-cells = <0>; 1235 reg = <21>; 1236 }; 1237 1238 mci1_clk: mci1_clk { 1239 #clock-cells = <0>; 1240 reg = <22>; 1241 }; 1242 1243 spi0_clk: spi0_clk { 1244 #clock-cells = <0>; 1245 reg = <24>; 1246 atmel,clk-output-range = <0 166000000>; 1247 }; 1248 1249 spi1_clk: spi1_clk { 1250 #clock-cells = <0>; 1251 reg = <25>; 1252 atmel,clk-output-range = <0 166000000>; 1253 }; 1254 1255 tcb0_clk: tcb0_clk { 1256 #clock-cells = <0>; 1257 reg = <26>; 1258 atmel,clk-output-range = <0 166000000>; 1259 }; 1260 1261 pwm_clk: pwm_clk { 1262 #clock-cells = <0>; 1263 reg = <28>; 1264 }; 1265 1266 adc_clk: adc_clk { 1267 #clock-cells = <0>; 1268 reg = <29>; 1269 atmel,clk-output-range = <0 83000000>; 1270 }; 1271 1272 dma0_clk: dma0_clk { 1273 #clock-cells = <0>; 1274 reg = <30>; 1275 }; 1276 1277 dma1_clk: dma1_clk { 1278 #clock-cells = <0>; 1279 reg = <31>; 1280 }; 1281 1282 uhphs_clk: uhphs_clk { 1283 #clock-cells = <0>; 1284 reg = <32>; 1285 }; 1286 1287 udphs_clk: udphs_clk { 1288 #clock-cells = <0>; 1289 reg = <33>; 1290 }; 1291 1292 isi_clk: isi_clk { 1293 #clock-cells = <0>; 1294 reg = <37>; 1295 }; 1296 1297 ssc0_clk: ssc0_clk { 1298 #clock-cells = <0>; 1299 reg = <38>; 1300 atmel,clk-output-range = <0 83000000>; 1301 }; 1302 1303 ssc1_clk: ssc1_clk { 1304 #clock-cells = <0>; 1305 reg = <39>; 1306 atmel,clk-output-range = <0 83000000>; 1307 }; 1308 1309 sha_clk: sha_clk { 1310 #clock-cells = <0>; 1311 reg = <42>; 1312 }; 1313 1314 aes_clk: aes_clk { 1315 #clock-cells = <0>; 1316 reg = <43>; 1317 }; 1318 1319 tdes_clk: tdes_clk { 1320 #clock-cells = <0>; 1321 reg = <44>; 1322 }; 1323 1324 trng_clk: trng_clk { 1325 #clock-cells = <0>; 1326 reg = <45>; 1327 }; 1328 1329 fuse_clk: fuse_clk { 1330 #clock-cells = <0>; 1331 reg = <48>; 1332 }; 1333 1334 mpddr_clk: mpddr_clk { 1335 #clock-cells = <0>; 1336 reg = <49>; 1337 }; 1338 }; 1339 }; 1340 1341 rstc@fffffe00 { 1342 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; 1343 reg = <0xfffffe00 0x10>; 1344 clocks = <&clk32k>; 1345 }; 1346 1347 shutdown-controller@fffffe10 { 1348 compatible = "atmel,at91sam9x5-shdwc"; 1349 reg = <0xfffffe10 0x10>; 1350 clocks = <&clk32k>; 1351 }; 1352 1353 pit: timer@fffffe30 { 1354 compatible = "atmel,at91sam9260-pit"; 1355 reg = <0xfffffe30 0xf>; 1356 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 1357 clocks = <&mck>; 1358 }; 1359 1360 watchdog@fffffe40 { 1361 compatible = "atmel,at91sam9260-wdt"; 1362 reg = <0xfffffe40 0x10>; 1363 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 1364 clocks = <&clk32k>; 1365 atmel,watchdog-type = "hardware"; 1366 atmel,reset-type = "all"; 1367 atmel,dbg-halt; 1368 status = "disabled"; 1369 }; 1370 1371 sckc@fffffe50 { 1372 compatible = "atmel,at91sam9x5-sckc"; 1373 reg = <0xfffffe50 0x4>; 1374 1375 slow_rc_osc: slow_rc_osc { 1376 compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; 1377 #clock-cells = <0>; 1378 clock-frequency = <32768>; 1379 clock-accuracy = <50000000>; 1380 atmel,startup-time-usec = <75>; 1381 }; 1382 1383 slow_osc: slow_osc { 1384 compatible = "atmel,at91sam9x5-clk-slow-osc"; 1385 #clock-cells = <0>; 1386 clocks = <&slow_xtal>; 1387 atmel,startup-time-usec = <1200000>; 1388 }; 1389 1390 clk32k: slowck { 1391 compatible = "atmel,at91sam9x5-clk-slow"; 1392 #clock-cells = <0>; 1393 clocks = <&slow_rc_osc &slow_osc>; 1394 }; 1395 }; 1396 1397 rtc@fffffeb0 { 1398 compatible = "atmel,at91rm9200-rtc"; 1399 reg = <0xfffffeb0 0x30>; 1400 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1401 clocks = <&clk32k>; 1402 }; 1403 }; 1404 1405 nfc_sram: sram@200000 { 1406 compatible = "mmio-sram"; 1407 no-memory-wc; 1408 reg = <0x200000 0x2400>; 1409 }; 1410 1411 usb0: gadget@00500000 { 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 compatible = "atmel,sama5d3-udc"; 1415 reg = <0x00500000 0x100000 1416 0xf8030000 0x4000>; 1417 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; 1418 clocks = <&udphs_clk>, <&utmi>; 1419 clock-names = "pclk", "hclk"; 1420 status = "disabled"; 1421 1422 ep@0 { 1423 reg = <0>; 1424 atmel,fifo-size = <64>; 1425 atmel,nb-banks = <1>; 1426 }; 1427 1428 ep@1 { 1429 reg = <1>; 1430 atmel,fifo-size = <1024>; 1431 atmel,nb-banks = <3>; 1432 atmel,can-dma; 1433 atmel,can-isoc; 1434 }; 1435 1436 ep@2 { 1437 reg = <2>; 1438 atmel,fifo-size = <1024>; 1439 atmel,nb-banks = <3>; 1440 atmel,can-dma; 1441 atmel,can-isoc; 1442 }; 1443 1444 ep@3 { 1445 reg = <3>; 1446 atmel,fifo-size = <1024>; 1447 atmel,nb-banks = <2>; 1448 atmel,can-dma; 1449 }; 1450 1451 ep@4 { 1452 reg = <4>; 1453 atmel,fifo-size = <1024>; 1454 atmel,nb-banks = <2>; 1455 atmel,can-dma; 1456 }; 1457 1458 ep@5 { 1459 reg = <5>; 1460 atmel,fifo-size = <1024>; 1461 atmel,nb-banks = <2>; 1462 atmel,can-dma; 1463 }; 1464 1465 ep@6 { 1466 reg = <6>; 1467 atmel,fifo-size = <1024>; 1468 atmel,nb-banks = <2>; 1469 atmel,can-dma; 1470 }; 1471 1472 ep@7 { 1473 reg = <7>; 1474 atmel,fifo-size = <1024>; 1475 atmel,nb-banks = <2>; 1476 atmel,can-dma; 1477 }; 1478 1479 ep@8 { 1480 reg = <8>; 1481 atmel,fifo-size = <1024>; 1482 atmel,nb-banks = <2>; 1483 }; 1484 1485 ep@9 { 1486 reg = <9>; 1487 atmel,fifo-size = <1024>; 1488 atmel,nb-banks = <2>; 1489 }; 1490 1491 ep@10 { 1492 reg = <10>; 1493 atmel,fifo-size = <1024>; 1494 atmel,nb-banks = <2>; 1495 }; 1496 1497 ep@11 { 1498 reg = <11>; 1499 atmel,fifo-size = <1024>; 1500 atmel,nb-banks = <2>; 1501 }; 1502 1503 ep@12 { 1504 reg = <12>; 1505 atmel,fifo-size = <1024>; 1506 atmel,nb-banks = <2>; 1507 }; 1508 1509 ep@13 { 1510 reg = <13>; 1511 atmel,fifo-size = <1024>; 1512 atmel,nb-banks = <2>; 1513 }; 1514 1515 ep@14 { 1516 reg = <14>; 1517 atmel,fifo-size = <1024>; 1518 atmel,nb-banks = <2>; 1519 }; 1520 1521 ep@15 { 1522 reg = <15>; 1523 atmel,fifo-size = <1024>; 1524 atmel,nb-banks = <2>; 1525 }; 1526 }; 1527 1528 usb1: ohci@00600000 { 1529 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 1530 reg = <0x00600000 0x100000>; 1531 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1532 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; 1533 clock-names = "ohci_clk", "hclk", "uhpck"; 1534 status = "disabled"; 1535 }; 1536 1537 usb2: ehci@00700000 { 1538 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1539 reg = <0x00700000 0x100000>; 1540 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1541 clocks = <&utmi>, <&uhphs_clk>; 1542 clock-names = "usb_clk", "ehci_clk"; 1543 status = "disabled"; 1544 }; 1545 1546 ebi: ebi@10000000 { 1547 compatible = "atmel,sama5d3-ebi"; 1548 #address-cells = <2>; 1549 #size-cells = <1>; 1550 atmel,smc = <&hsmc>; 1551 reg = <0x10000000 0x10000000 1552 0x40000000 0x30000000>; 1553 ranges = <0x0 0x0 0x10000000 0x10000000 1554 0x1 0x0 0x40000000 0x10000000 1555 0x2 0x0 0x50000000 0x10000000 1556 0x3 0x0 0x60000000 0x10000000>; 1557 clocks = <&mck>; 1558 status = "disabled"; 1559 1560 nand_controller: nand-controller { 1561 compatible = "atmel,sama5d3-nand-controller"; 1562 atmel,nfc-sram = <&nfc_sram>; 1563 atmel,nfc-io = <&nfc_io>; 1564 ecc-engine = <&pmecc>; 1565 #address-cells = <2>; 1566 #size-cells = <1>; 1567 ranges; 1568 status = "disabled"; 1569 }; 1570 }; 1571 1572 nfc_io: nfc-io@70000000 { 1573 compatible = "atmel,sama5d3-nfc-io", "syscon"; 1574 reg = <0x70000000 0x8000000>; 1575 }; 1576 }; 1577}; 1578