1/* 2 * Copyright (C) 2014 STMicroelectronics Limited. 3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * publishhed by the Free Software Foundation. 8 */ 9#include "stih407-pinctrl.dtsi" 10#include <dt-bindings/mfd/st-lpc.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/reset/stih407-resets.h> 13#include <dt-bindings/interrupt-controller/irq-st.h> 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 reserved-memory { 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges; 22 23 gp0_reserved: rproc@45000000 { 24 compatible = "shared-dma-pool"; 25 reg = <0x45000000 0x00400000>; 26 no-map; 27 }; 28 29 delta_reserved: rproc@44000000 { 30 compatible = "shared-dma-pool"; 31 reg = <0x44000000 0x01000000>; 32 no-map; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a9"; 42 reg = <0>; 43 44 /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 45 cpu-release-addr = <0x94100A4>; 46 47 /* kHz uV */ 48 operating-points = <1500000 0 49 1200000 0 50 800000 0 51 500000 0>; 52 53 clocks = <&clk_m_a9>; 54 clock-names = "cpu"; 55 clock-latency = <100000>; 56 cpu0-supply = <&pwm_regulator>; 57 st,syscfg = <&syscfg_core 0x8e0>; 58 }; 59 cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a9"; 62 reg = <1>; 63 64 /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 65 cpu-release-addr = <0x94100A4>; 66 67 /* kHz uV */ 68 operating-points = <1500000 0 69 1200000 0 70 800000 0 71 500000 0>; 72 }; 73 }; 74 75 intc: interrupt-controller@08761000 { 76 compatible = "arm,cortex-a9-gic"; 77 #interrupt-cells = <3>; 78 interrupt-controller; 79 reg = <0x08761000 0x1000>, <0x08760100 0x100>; 80 }; 81 82 scu@08760000 { 83 compatible = "arm,cortex-a9-scu"; 84 reg = <0x08760000 0x1000>; 85 }; 86 87 timer@08760200 { 88 interrupt-parent = <&intc>; 89 compatible = "arm,cortex-a9-global-timer"; 90 reg = <0x08760200 0x100>; 91 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 92 clocks = <&arm_periph_clk>; 93 }; 94 95 l2: cache-controller { 96 compatible = "arm,pl310-cache"; 97 reg = <0x08762000 0x1000>; 98 arm,data-latency = <3 3 3>; 99 arm,tag-latency = <2 2 2>; 100 cache-unified; 101 cache-level = <2>; 102 }; 103 104 arm-pmu { 105 interrupt-parent = <&intc>; 106 compatible = "arm,cortex-a9-pmu"; 107 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 108 }; 109 110 pwm_regulator: pwm-regulator { 111 compatible = "pwm-regulator"; 112 pwms = <&pwm1 3 8448>; 113 regulator-name = "CPU_1V0_AVS"; 114 regulator-min-microvolt = <784000>; 115 regulator-max-microvolt = <1299000>; 116 regulator-always-on; 117 max-duty-cycle = <255>; 118 status = "okay"; 119 }; 120 121 soc { 122 #address-cells = <1>; 123 #size-cells = <1>; 124 interrupt-parent = <&intc>; 125 ranges; 126 compatible = "simple-bus"; 127 128 restart { 129 compatible = "st,stih407-restart"; 130 st,syscfg = <&syscfg_sbc_reg>; 131 status = "okay"; 132 }; 133 134 powerdown: powerdown-controller { 135 compatible = "st,stih407-powerdown"; 136 #reset-cells = <1>; 137 }; 138 139 softreset: softreset-controller { 140 compatible = "st,stih407-softreset"; 141 #reset-cells = <1>; 142 }; 143 144 picophyreset: picophyreset-controller { 145 compatible = "st,stih407-picophyreset"; 146 #reset-cells = <1>; 147 }; 148 149 syscfg_sbc: sbc-syscfg@9620000 { 150 compatible = "st,stih407-sbc-syscfg", "syscon"; 151 reg = <0x9620000 0x1000>; 152 }; 153 154 syscfg_front: front-syscfg@9280000 { 155 compatible = "st,stih407-front-syscfg", "syscon"; 156 reg = <0x9280000 0x1000>; 157 }; 158 159 syscfg_rear: rear-syscfg@9290000 { 160 compatible = "st,stih407-rear-syscfg", "syscon"; 161 reg = <0x9290000 0x1000>; 162 }; 163 164 syscfg_flash: flash-syscfg@92a0000 { 165 compatible = "st,stih407-flash-syscfg", "syscon"; 166 reg = <0x92a0000 0x1000>; 167 }; 168 169 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { 170 compatible = "st,stih407-sbc-reg-syscfg", "syscon"; 171 reg = <0x9600000 0x1000>; 172 }; 173 174 syscfg_core: core-syscfg@92b0000 { 175 compatible = "st,stih407-core-syscfg", "syscon"; 176 reg = <0x92b0000 0x1000>; 177 }; 178 179 syscfg_lpm: lpm-syscfg@94b5100 { 180 compatible = "st,stih407-lpm-syscfg", "syscon"; 181 reg = <0x94b5100 0x1000>; 182 }; 183 184 irq-syscfg { 185 compatible = "st,stih407-irq-syscfg"; 186 st,syscfg = <&syscfg_core>; 187 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, 188 <ST_IRQ_SYSCFG_PMU_1>; 189 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, 190 <ST_IRQ_SYSCFG_DISABLED>; 191 }; 192 193 /* Display */ 194 vtg_main: sti-vtg-main@8d02800 { 195 compatible = "st,vtg"; 196 reg = <0x8d02800 0x200>; 197 interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>; 198 }; 199 200 vtg_aux: sti-vtg-aux@8d00200 { 201 compatible = "st,vtg"; 202 reg = <0x8d00200 0x100>; 203 interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>; 204 }; 205 206 serial@9830000 { 207 compatible = "st,asc"; 208 reg = <0x9830000 0x2c>; 209 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>; 210 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 211 /* Pinctrl moved out to a per-board configuration */ 212 213 status = "disabled"; 214 }; 215 216 serial@9831000 { 217 compatible = "st,asc"; 218 reg = <0x9831000 0x2c>; 219 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>; 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pinctrl_serial1>; 222 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 223 224 status = "disabled"; 225 }; 226 227 serial@9832000 { 228 compatible = "st,asc"; 229 reg = <0x9832000 0x2c>; 230 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_serial2>; 233 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 234 235 status = "disabled"; 236 }; 237 238 /* SBC_ASC0 - UART10 */ 239 sbc_serial0: serial@9530000 { 240 compatible = "st,asc"; 241 reg = <0x9530000 0x2c>; 242 interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_sbc_serial0>; 245 clocks = <&clk_sysin>; 246 247 status = "disabled"; 248 }; 249 250 serial@9531000 { 251 compatible = "st,asc"; 252 reg = <0x9531000 0x2c>; 253 interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_sbc_serial1>; 256 clocks = <&clk_sysin>; 257 258 status = "disabled"; 259 }; 260 261 i2c@9840000 { 262 compatible = "st,comms-ssc4-i2c"; 263 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 264 reg = <0x9840000 0x110>; 265 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 266 clock-names = "ssc"; 267 clock-frequency = <400000>; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_i2c0_default>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 273 status = "disabled"; 274 }; 275 276 i2c@9841000 { 277 compatible = "st,comms-ssc4-i2c"; 278 reg = <0x9841000 0x110>; 279 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 281 clock-names = "ssc"; 282 clock-frequency = <400000>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&pinctrl_i2c1_default>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 288 status = "disabled"; 289 }; 290 291 i2c@9842000 { 292 compatible = "st,comms-ssc4-i2c"; 293 reg = <0x9842000 0x110>; 294 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 296 clock-names = "ssc"; 297 clock-frequency = <400000>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&pinctrl_i2c2_default>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 303 status = "disabled"; 304 }; 305 306 i2c@9843000 { 307 compatible = "st,comms-ssc4-i2c"; 308 reg = <0x9843000 0x110>; 309 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 311 clock-names = "ssc"; 312 clock-frequency = <400000>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&pinctrl_i2c3_default>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 318 status = "disabled"; 319 }; 320 321 i2c@9844000 { 322 compatible = "st,comms-ssc4-i2c"; 323 reg = <0x9844000 0x110>; 324 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 326 clock-names = "ssc"; 327 clock-frequency = <400000>; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&pinctrl_i2c4_default>; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 333 status = "disabled"; 334 }; 335 336 i2c@9845000 { 337 compatible = "st,comms-ssc4-i2c"; 338 reg = <0x9845000 0x110>; 339 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 341 clock-names = "ssc"; 342 clock-frequency = <400000>; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pinctrl_i2c5_default>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 348 status = "disabled"; 349 }; 350 351 352 /* SSCs on SBC */ 353 i2c@9540000 { 354 compatible = "st,comms-ssc4-i2c"; 355 reg = <0x9540000 0x110>; 356 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&clk_sysin>; 358 clock-names = "ssc"; 359 clock-frequency = <400000>; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&pinctrl_i2c10_default>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 365 status = "disabled"; 366 }; 367 368 i2c@9541000 { 369 compatible = "st,comms-ssc4-i2c"; 370 reg = <0x9541000 0x110>; 371 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&clk_sysin>; 373 clock-names = "ssc"; 374 clock-frequency = <400000>; 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pinctrl_i2c11_default>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 380 status = "disabled"; 381 }; 382 383 usb2_picophy0: phy1 { 384 compatible = "st,stih407-usb2-phy"; 385 #phy-cells = <0>; 386 st,syscfg = <&syscfg_core 0x100 0xf4>; 387 resets = <&softreset STIH407_PICOPHY_SOFTRESET>, 388 <&picophyreset STIH407_PICOPHY2_RESET>; 389 reset-names = "global", "port"; 390 }; 391 392 miphy28lp_phy: miphy28lp@9b22000 { 393 compatible = "st,miphy28lp-phy"; 394 st,syscfg = <&syscfg_core>; 395 #address-cells = <1>; 396 #size-cells = <1>; 397 ranges; 398 399 phy_port0: port@9b22000 { 400 reg = <0x9b22000 0xff>, 401 <0x9b09000 0xff>, 402 <0x9b04000 0xff>; 403 reg-names = "sata-up", 404 "pcie-up", 405 "pipew"; 406 407 st,syscfg = <0x114 0x818 0xe0 0xec>; 408 #phy-cells = <1>; 409 410 reset-names = "miphy-sw-rst"; 411 resets = <&softreset STIH407_MIPHY0_SOFTRESET>; 412 }; 413 414 phy_port1: port@9b2a000 { 415 reg = <0x9b2a000 0xff>, 416 <0x9b19000 0xff>, 417 <0x9b14000 0xff>; 418 reg-names = "sata-up", 419 "pcie-up", 420 "pipew"; 421 422 st,syscfg = <0x118 0x81c 0xe4 0xf0>; 423 424 #phy-cells = <1>; 425 426 reset-names = "miphy-sw-rst"; 427 resets = <&softreset STIH407_MIPHY1_SOFTRESET>; 428 }; 429 430 phy_port2: port@8f95000 { 431 reg = <0x8f95000 0xff>, 432 <0x8f90000 0xff>; 433 reg-names = "pipew", 434 "usb3-up"; 435 436 st,syscfg = <0x11c 0x820>; 437 438 #phy-cells = <1>; 439 440 reset-names = "miphy-sw-rst"; 441 resets = <&softreset STIH407_MIPHY2_SOFTRESET>; 442 }; 443 }; 444 445 spi@9840000 { 446 compatible = "st,comms-ssc4-spi"; 447 reg = <0x9840000 0x110>; 448 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 450 clock-names = "ssc"; 451 pinctrl-0 = <&pinctrl_spi0_default>; 452 pinctrl-names = "default"; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 456 status = "disabled"; 457 }; 458 459 spi@9841000 { 460 compatible = "st,comms-ssc4-spi"; 461 reg = <0x9841000 0x110>; 462 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 464 clock-names = "ssc"; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&pinctrl_spi1_default>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 470 status = "disabled"; 471 }; 472 473 spi@9842000 { 474 compatible = "st,comms-ssc4-spi"; 475 reg = <0x9842000 0x110>; 476 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 478 clock-names = "ssc"; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pinctrl_spi2_default>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 484 status = "disabled"; 485 }; 486 487 spi@9843000 { 488 compatible = "st,comms-ssc4-spi"; 489 reg = <0x9843000 0x110>; 490 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 492 clock-names = "ssc"; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pinctrl_spi3_default>; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 498 status = "disabled"; 499 }; 500 501 spi@9844000 { 502 compatible = "st,comms-ssc4-spi"; 503 reg = <0x9844000 0x110>; 504 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 506 clock-names = "ssc"; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&pinctrl_spi4_default>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 512 status = "disabled"; 513 }; 514 515 /* SBC SSC */ 516 spi@9540000 { 517 compatible = "st,comms-ssc4-spi"; 518 reg = <0x9540000 0x110>; 519 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&clk_sysin>; 521 clock-names = "ssc"; 522 pinctrl-names = "default"; 523 pinctrl-0 = <&pinctrl_spi10_default>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 527 status = "disabled"; 528 }; 529 530 spi@9541000 { 531 compatible = "st,comms-ssc4-spi"; 532 reg = <0x9541000 0x110>; 533 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&clk_sysin>; 535 clock-names = "ssc"; 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pinctrl_spi11_default>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 541 status = "disabled"; 542 }; 543 544 spi@9542000 { 545 compatible = "st,comms-ssc4-spi"; 546 reg = <0x9542000 0x110>; 547 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&clk_sysin>; 549 clock-names = "ssc"; 550 pinctrl-names = "default"; 551 pinctrl-0 = <&pinctrl_spi12_default>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 555 status = "disabled"; 556 }; 557 558 mmc0: sdhci@09060000 { 559 compatible = "st,sdhci-stih407", "st,sdhci"; 560 status = "disabled"; 561 reg = <0x09060000 0x7ff>, <0x9061008 0x20>; 562 reg-names = "mmc", "top-mmc-delay"; 563 interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>; 564 interrupt-names = "mmcirq"; 565 pinctrl-names = "default"; 566 pinctrl-0 = <&pinctrl_mmc0>; 567 clock-names = "mmc", "icn"; 568 clocks = <&clk_s_c0_flexgen CLK_MMC_0>, 569 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; 570 bus-width = <8>; 571 }; 572 573 mmc1: sdhci@09080000 { 574 compatible = "st,sdhci-stih407", "st,sdhci"; 575 status = "disabled"; 576 reg = <0x09080000 0x7ff>; 577 reg-names = "mmc"; 578 interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>; 579 interrupt-names = "mmcirq"; 580 pinctrl-names = "default"; 581 pinctrl-0 = <&pinctrl_sd1>; 582 clock-names = "mmc", "icn"; 583 clocks = <&clk_s_c0_flexgen CLK_MMC_1>, 584 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; 585 resets = <&softreset STIH407_MMC1_SOFTRESET>; 586 bus-width = <4>; 587 }; 588 589 /* Watchdog and Real-Time Clock */ 590 lpc@8787000 { 591 compatible = "st,stih407-lpc"; 592 reg = <0x8787000 0x1000>; 593 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>; 594 clocks = <&clk_s_d3_flexgen CLK_LPC_0>; 595 timeout-sec = <120>; 596 st,syscfg = <&syscfg_core>; 597 st,lpc-mode = <ST_LPC_MODE_WDT>; 598 }; 599 600 lpc@8788000 { 601 compatible = "st,stih407-lpc"; 602 reg = <0x8788000 0x1000>; 603 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>; 604 clocks = <&clk_s_d3_flexgen CLK_LPC_1>; 605 st,lpc-mode = <ST_LPC_MODE_CLKSRC>; 606 }; 607 608 sata0: sata@9b20000 { 609 compatible = "st,ahci"; 610 reg = <0x9b20000 0x1000>; 611 612 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; 613 interrupt-names = "hostc"; 614 615 phys = <&phy_port0 PHY_TYPE_SATA>; 616 phy-names = "ahci_phy"; 617 618 resets = <&powerdown STIH407_SATA0_POWERDOWN>, 619 <&softreset STIH407_SATA0_SOFTRESET>, 620 <&softreset STIH407_SATA0_PWR_SOFTRESET>; 621 reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; 622 623 clock-names = "ahci_clk"; 624 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; 625 626 ports-implemented = <0x1>; 627 628 status = "disabled"; 629 }; 630 631 sata1: sata@9b28000 { 632 compatible = "st,ahci"; 633 reg = <0x9b28000 0x1000>; 634 635 interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>; 636 interrupt-names = "hostc"; 637 638 phys = <&phy_port1 PHY_TYPE_SATA>; 639 phy-names = "ahci_phy"; 640 641 resets = <&powerdown STIH407_SATA1_POWERDOWN>, 642 <&softreset STIH407_SATA1_SOFTRESET>, 643 <&softreset STIH407_SATA1_PWR_SOFTRESET>; 644 reset-names = "pwr-dwn", 645 "sw-rst", 646 "pwr-rst"; 647 648 clock-names = "ahci_clk"; 649 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; 650 651 ports-implemented = <0x1>; 652 653 status = "disabled"; 654 }; 655 656 657 st_dwc3: dwc3@8f94000 { 658 compatible = "st,stih407-dwc3"; 659 reg = <0x08f94000 0x1000>, <0x110 0x4>; 660 reg-names = "reg-glue", "syscfg-reg"; 661 st,syscfg = <&syscfg_core>; 662 resets = <&powerdown STIH407_USB3_POWERDOWN>, 663 <&softreset STIH407_MIPHY2_SOFTRESET>; 664 reset-names = "powerdown", "softreset"; 665 #address-cells = <1>; 666 #size-cells = <1>; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&pinctrl_usb3>; 669 ranges; 670 671 status = "disabled"; 672 673 dwc3: dwc3@9900000 { 674 compatible = "snps,dwc3"; 675 reg = <0x09900000 0x100000>; 676 interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>; 677 dr_mode = "host"; 678 phy-names = "usb2-phy", "usb3-phy"; 679 phys = <&usb2_picophy0>, 680 <&phy_port2 PHY_TYPE_USB3>; 681 snps,dis_u3_susphy_quirk; 682 }; 683 }; 684 685 /* COMMS PWM Module */ 686 pwm0: pwm@9810000 { 687 compatible = "st,sti-pwm"; 688 #pwm-cells = <2>; 689 reg = <0x9810000 0x68>; 690 interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&pinctrl_pwm0_chan0_default>; 693 clock-names = "pwm"; 694 clocks = <&clk_sysin>; 695 st,pwm-num-chan = <1>; 696 697 status = "disabled"; 698 }; 699 700 /* SBC PWM Module */ 701 pwm1: pwm@9510000 { 702 compatible = "st,sti-pwm"; 703 #pwm-cells = <2>; 704 reg = <0x9510000 0x68>; 705 interrupts = <GIC_SPI 131 IRQ_TYPE_NONE>; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&pinctrl_pwm1_chan0_default 708 &pinctrl_pwm1_chan1_default 709 &pinctrl_pwm1_chan2_default 710 &pinctrl_pwm1_chan3_default>; 711 clock-names = "pwm"; 712 clocks = <&clk_sysin>; 713 st,pwm-num-chan = <4>; 714 715 status = "disabled"; 716 }; 717 718 rng10: rng@08a89000 { 719 compatible = "st,rng"; 720 reg = <0x08a89000 0x1000>; 721 clocks = <&clk_sysin>; 722 status = "okay"; 723 }; 724 725 rng11: rng@08a8a000 { 726 compatible = "st,rng"; 727 reg = <0x08a8a000 0x1000>; 728 clocks = <&clk_sysin>; 729 status = "okay"; 730 }; 731 732 ethernet0: dwmac@9630000 { 733 device_type = "network"; 734 status = "disabled"; 735 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; 736 reg = <0x9630000 0x8000>, <0x80 0x4>; 737 reg-names = "stmmaceth", "sti-ethconf"; 738 739 st,syscon = <&syscfg_sbc_reg 0x80>; 740 st,gmac_en; 741 resets = <&softreset STIH407_ETH1_SOFTRESET>; 742 reset-names = "stmmaceth"; 743 744 interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>, 745 <GIC_SPI 99 IRQ_TYPE_NONE>; 746 interrupt-names = "macirq", "eth_wake_irq"; 747 748 /* DMA Bus Mode */ 749 snps,pbl = <8>; 750 751 pinctrl-names = "default"; 752 pinctrl-0 = <&pinctrl_rgmii1>; 753 754 clock-names = "stmmaceth", "sti-ethclk"; 755 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, 756 <&clk_s_c0_flexgen CLK_ETH_PHY>; 757 }; 758 759 rng10: rng@08a89000 { 760 compatible = "st,rng"; 761 reg = <0x08a89000 0x1000>; 762 clocks = <&clk_sysin>; 763 status = "okay"; 764 }; 765 766 rng11: rng@08a8a000 { 767 compatible = "st,rng"; 768 reg = <0x08a8a000 0x1000>; 769 clocks = <&clk_sysin>; 770 status = "okay"; 771 }; 772 773 mailbox0: mailbox@8f00000 { 774 compatible = "st,stih407-mailbox"; 775 reg = <0x8f00000 0x1000>; 776 interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>; 777 #mbox-cells = <2>; 778 mbox-name = "a9"; 779 status = "okay"; 780 }; 781 782 mailbox1: mailbox@8f01000 { 783 compatible = "st,stih407-mailbox"; 784 reg = <0x8f01000 0x1000>; 785 #mbox-cells = <2>; 786 mbox-name = "st231_gp_1"; 787 status = "okay"; 788 }; 789 790 mailbox2: mailbox@8f02000 { 791 compatible = "st,stih407-mailbox"; 792 reg = <0x8f02000 0x1000>; 793 #mbox-cells = <2>; 794 mbox-name = "st231_gp_0"; 795 status = "okay"; 796 }; 797 798 mailbox3: mailbox@8f03000 { 799 compatible = "st,stih407-mailbox"; 800 reg = <0x8f03000 0x1000>; 801 #mbox-cells = <2>; 802 mbox-name = "st231_audio_video"; 803 status = "okay"; 804 }; 805 806 st231_gp0: st231-gp0@0 { 807 compatible = "st,st231-rproc"; 808 memory-region = <&gp0_reserved>; 809 resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; 810 reset-names = "sw_reset"; 811 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; 812 clock-frequency = <600000000>; 813 st,syscfg = <&syscfg_core 0x22c>; 814 #mbox-cells = <1>; 815 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; 816 mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; 817 }; 818 819 st231_delta: st231-delta@0 { 820 compatible = "st,st231-rproc"; 821 memory-region = <&delta_reserved>; 822 resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; 823 reset-names = "sw_reset"; 824 clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; 825 clock-frequency = <600000000>; 826 st,syscfg = <&syscfg_core 0x224>; 827 #mbox-cells = <1>; 828 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; 829 mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; 830 }; 831 832 /* fdma audio */ 833 fdma0: dma-controller@8e20000 { 834 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; 835 reg = <0x8e20000 0x8000>, 836 <0x8e30000 0x3000>, 837 <0x8e37000 0x1000>, 838 <0x8e38000 0x8000>; 839 reg-names = "slimcore", "dmem", "peripherals", "imem"; 840 clocks = <&clk_s_c0_flexgen CLK_FDMA>, 841 <&clk_s_c0_flexgen CLK_EXT2F_A9>, 842 <&clk_s_c0_flexgen CLK_EXT2F_A9>, 843 <&clk_s_c0_flexgen CLK_EXT2F_A9>; 844 interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>; 845 dma-channels = <16>; 846 #dma-cells = <3>; 847 }; 848 849 /* fdma app */ 850 fdma1: dma-controller@8e40000 { 851 compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc"; 852 reg = <0x8e40000 0x8000>, 853 <0x8e50000 0x3000>, 854 <0x8e57000 0x1000>, 855 <0x8e58000 0x8000>; 856 reg-names = "slimcore", "dmem", "peripherals", "imem"; 857 clocks = <&clk_s_c0_flexgen CLK_FDMA>, 858 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, 859 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, 860 <&clk_s_c0_flexgen CLK_EXT2F_A9>; 861 862 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; 863 dma-channels = <16>; 864 #dma-cells = <3>; 865 866 status = "disabled"; 867 }; 868 869 /* fdma free running */ 870 fdma2: dma-controller@8e60000 { 871 compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc"; 872 reg = <0x8e60000 0x8000>, 873 <0x8e70000 0x3000>, 874 <0x8e77000 0x1000>, 875 <0x8e78000 0x8000>; 876 reg-names = "slimcore", "dmem", "peripherals", "imem"; 877 interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>; 878 dma-channels = <16>; 879 #dma-cells = <3>; 880 clocks = <&clk_s_c0_flexgen CLK_FDMA>, 881 <&clk_s_c0_flexgen CLK_EXT2F_A9>, 882 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, 883 <&clk_s_c0_flexgen CLK_EXT2F_A9>; 884 885 status = "disabled"; 886 }; 887 888 sti_sasg_codec: sti-sasg-codec { 889 compatible = "st,stih407-sas-codec"; 890 #sound-dai-cells = <1>; 891 status = "disabled"; 892 st,syscfg = <&syscfg_core>; 893 }; 894 895 sti_uni_player0: sti-uni-player@8d80000 { 896 compatible = "st,stih407-uni-player-hdmi"; 897 #sound-dai-cells = <0>; 898 st,syscfg = <&syscfg_core>; 899 clocks = <&clk_s_d0_flexgen CLK_PCM_0>; 900 assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; 901 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; 902 assigned-clock-rates = <50000000>; 903 reg = <0x8d80000 0x158>; 904 interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>; 905 dmas = <&fdma0 2 0 1>; 906 dma-names = "tx"; 907 908 status = "disabled"; 909 }; 910 911 sti_uni_player1: sti-uni-player@8d81000 { 912 compatible = "st,stih407-uni-player-pcm-out"; 913 #sound-dai-cells = <0>; 914 st,syscfg = <&syscfg_core>; 915 clocks = <&clk_s_d0_flexgen CLK_PCM_1>; 916 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>; 917 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; 918 assigned-clock-rates = <50000000>; 919 reg = <0x8d81000 0x158>; 920 interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>; 921 dmas = <&fdma0 3 0 1>; 922 dma-names = "tx"; 923 924 status = "disabled"; 925 }; 926 927 sti_uni_player2: sti-uni-player@8d82000 { 928 compatible = "st,stih407-uni-player-dac"; 929 #sound-dai-cells = <0>; 930 st,syscfg = <&syscfg_core>; 931 clocks = <&clk_s_d0_flexgen CLK_PCM_2>; 932 assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>; 933 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; 934 assigned-clock-rates = <50000000>; 935 reg = <0x8d82000 0x158>; 936 interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>; 937 dmas = <&fdma0 4 0 1>; 938 dma-names = "tx"; 939 940 status = "disabled"; 941 }; 942 943 sti_uni_player3: sti-uni-player@8d85000 { 944 compatible = "st,stih407-uni-player-spdif"; 945 #sound-dai-cells = <0>; 946 st,syscfg = <&syscfg_core>; 947 clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; 948 assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>; 949 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; 950 assigned-clock-rates = <50000000>; 951 reg = <0x8d85000 0x158>; 952 interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>; 953 dmas = <&fdma0 7 0 1>; 954 dma-names = "tx"; 955 956 status = "disabled"; 957 }; 958 959 sti_uni_reader0: sti-uni-reader@8d83000 { 960 compatible = "st,stih407-uni-reader-pcm_in"; 961 #sound-dai-cells = <0>; 962 st,syscfg = <&syscfg_core>; 963 reg = <0x8d83000 0x158>; 964 interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>; 965 dmas = <&fdma0 5 0 1>; 966 dma-names = "rx"; 967 968 status = "disabled"; 969 }; 970 971 sti_uni_reader1: sti-uni-reader@8d84000 { 972 compatible = "st,stih407-uni-reader-hdmi"; 973 #sound-dai-cells = <0>; 974 st,syscfg = <&syscfg_core>; 975 reg = <0x8d84000 0x158>; 976 interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>; 977 dmas = <&fdma0 6 0 1>; 978 dma-names = "rx"; 979 980 status = "disabled"; 981 }; 982 983 delta0 { 984 compatible = "st,st-delta"; 985 clock-names = "delta", 986 "delta-st231", 987 "delta-flash-promip"; 988 clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, 989 <&clk_s_c0_flexgen CLK_ST231_DMU>, 990 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; 991 }; 992 }; 993}; 994