1/* 2 * Copyright 2015 Vishnu Patekar 3 * 4 * Vishnu Patekar <vishnupatekar0510@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46 47#include <dt-bindings/clock/sun8i-a83t-ccu.h> 48#include <dt-bindings/clock/sun8i-r-ccu.h> 49#include <dt-bindings/reset/sun8i-a83t-ccu.h> 50#include <dt-bindings/reset/sun8i-r-ccu.h> 51 52/ { 53 interrupt-parent = <&gic>; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 57 aliases { 58 }; 59 60 chosen { 61 }; 62 63 cpus { 64 #address-cells = <1>; 65 #size-cells = <0>; 66 67 cpu@0 { 68 compatible = "arm,cortex-a7"; 69 device_type = "cpu"; 70 reg = <0>; 71 }; 72 73 cpu@1 { 74 compatible = "arm,cortex-a7"; 75 device_type = "cpu"; 76 reg = <1>; 77 }; 78 79 cpu@2 { 80 compatible = "arm,cortex-a7"; 81 device_type = "cpu"; 82 reg = <2>; 83 }; 84 85 cpu@3 { 86 compatible = "arm,cortex-a7"; 87 device_type = "cpu"; 88 reg = <3>; 89 }; 90 91 cpu@100 { 92 compatible = "arm,cortex-a7"; 93 device_type = "cpu"; 94 reg = <0x100>; 95 }; 96 97 cpu@101 { 98 compatible = "arm,cortex-a7"; 99 device_type = "cpu"; 100 reg = <0x101>; 101 }; 102 103 cpu@102 { 104 compatible = "arm,cortex-a7"; 105 device_type = "cpu"; 106 reg = <0x102>; 107 }; 108 109 cpu@103 { 110 compatible = "arm,cortex-a7"; 111 device_type = "cpu"; 112 reg = <0x103>; 113 }; 114 }; 115 116 timer { 117 compatible = "arm,armv7-timer"; 118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 120 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 122 }; 123 124 clocks { 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges; 128 129 /* TODO: PRCM block has a mux for this. */ 130 osc24M: osc24M_clk { 131 #clock-cells = <0>; 132 compatible = "fixed-clock"; 133 clock-frequency = <24000000>; 134 clock-accuracy = <50000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 /* 139 * This is called "internal OSC" in some places. 140 * It is an internal RC-based oscillator. 141 * TODO: Its controls are in the PRCM block. 142 */ 143 osc16M: osc16M_clk { 144 #clock-cells = <0>; 145 compatible = "fixed-clock"; 146 clock-frequency = <16000000>; 147 clock-output-names = "osc16M"; 148 }; 149 150 osc16Md512: osc16Md512_clk { 151 #clock-cells = <0>; 152 compatible = "fixed-factor-clock"; 153 clock-div = <512>; 154 clock-mult = <1>; 155 clocks = <&osc16M>; 156 clock-output-names = "osc16M-d512"; 157 }; 158 }; 159 160 memory { 161 reg = <0x40000000 0x80000000>; 162 device_type = "memory"; 163 }; 164 165 soc { 166 compatible = "simple-bus"; 167 #address-cells = <1>; 168 #size-cells = <1>; 169 ranges; 170 171 syscon: syscon@1c00000 { 172 compatible = "allwinner,sun8i-a83t-system-controller", 173 "syscon"; 174 reg = <0x01c00000 0x1000>; 175 }; 176 177 dma: dma-controller@1c02000 { 178 compatible = "allwinner,sun8i-a83t-dma"; 179 reg = <0x01c02000 0x1000>; 180 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 181 clocks = <&ccu CLK_BUS_DMA>; 182 resets = <&ccu RST_BUS_DMA>; 183 #dma-cells = <1>; 184 }; 185 186 mmc0: mmc@1c0f000 { 187 compatible = "allwinner,sun8i-a83t-mmc", 188 "allwinner,sun7i-a20-mmc"; 189 reg = <0x01c0f000 0x1000>; 190 clocks = <&ccu CLK_BUS_MMC0>, 191 <&ccu CLK_MMC0>, 192 <&ccu CLK_MMC0_OUTPUT>, 193 <&ccu CLK_MMC0_SAMPLE>; 194 clock-names = "ahb", 195 "mmc", 196 "output", 197 "sample"; 198 resets = <&ccu RST_BUS_MMC0>; 199 reset-names = "ahb"; 200 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 201 status = "disabled"; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 }; 205 206 mmc1: mmc@1c10000 { 207 compatible = "allwinner,sun8i-a83t-mmc", 208 "allwinner,sun7i-a20-mmc"; 209 reg = <0x01c10000 0x1000>; 210 clocks = <&ccu CLK_BUS_MMC1>, 211 <&ccu CLK_MMC1>, 212 <&ccu CLK_MMC1_OUTPUT>, 213 <&ccu CLK_MMC1_SAMPLE>; 214 clock-names = "ahb", 215 "mmc", 216 "output", 217 "sample"; 218 resets = <&ccu RST_BUS_MMC1>; 219 reset-names = "ahb"; 220 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 221 status = "disabled"; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 }; 225 226 mmc2: mmc@1c11000 { 227 compatible = "allwinner,sun8i-a83t-emmc"; 228 reg = <0x01c11000 0x1000>; 229 clocks = <&ccu CLK_BUS_MMC2>, 230 <&ccu CLK_MMC2>, 231 <&ccu CLK_MMC2_OUTPUT>, 232 <&ccu CLK_MMC2_SAMPLE>; 233 clock-names = "ahb", 234 "mmc", 235 "output", 236 "sample"; 237 resets = <&ccu RST_BUS_MMC2>; 238 reset-names = "ahb"; 239 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 240 status = "disabled"; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 }; 244 245 usb_otg: usb@01c19000 { 246 compatible = "allwinner,sun8i-a83t-musb", 247 "allwinner,sun8i-a33-musb"; 248 reg = <0x01c19000 0x0400>; 249 clocks = <&ccu CLK_BUS_OTG>; 250 resets = <&ccu RST_BUS_OTG>; 251 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 252 interrupt-names = "mc"; 253 phys = <&usbphy 0>; 254 phy-names = "usb"; 255 extcon = <&usbphy 0>; 256 status = "disabled"; 257 }; 258 259 usbphy: phy@1c19400 { 260 compatible = "allwinner,sun8i-a83t-usb-phy"; 261 reg = <0x01c19400 0x10>, 262 <0x01c1a800 0x14>, 263 <0x01c1b800 0x14>; 264 reg-names = "phy_ctrl", 265 "pmu1", 266 "pmu2"; 267 clocks = <&ccu CLK_USB_PHY0>, 268 <&ccu CLK_USB_PHY1>, 269 <&ccu CLK_USB_HSIC>, 270 <&ccu CLK_USB_HSIC_12M>; 271 clock-names = "usb0_phy", 272 "usb1_phy", 273 "usb2_phy", 274 "usb2_hsic_12M"; 275 resets = <&ccu RST_USB_PHY0>, 276 <&ccu RST_USB_PHY1>, 277 <&ccu RST_USB_HSIC>; 278 reset-names = "usb0_reset", 279 "usb1_reset", 280 "usb2_reset"; 281 status = "disabled"; 282 #phy-cells = <1>; 283 }; 284 285 ehci0: usb@1c1a000 { 286 compatible = "allwinner,sun8i-a83t-ehci", 287 "generic-ehci"; 288 reg = <0x01c1a000 0x100>; 289 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&ccu CLK_BUS_EHCI0>; 291 resets = <&ccu RST_BUS_EHCI0>; 292 phys = <&usbphy 1>; 293 phy-names = "usb"; 294 status = "disabled"; 295 }; 296 297 ohci0: usb@1c1a400 { 298 compatible = "allwinner,sun8i-a83t-ohci", 299 "generic-ohci"; 300 reg = <0x01c1a400 0x100>; 301 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; 303 resets = <&ccu RST_BUS_OHCI0>; 304 phys = <&usbphy 1>; 305 phy-names = "usb"; 306 status = "disabled"; 307 }; 308 309 ehci1: usb@1c1b000 { 310 compatible = "allwinner,sun8i-a83t-ehci", 311 "generic-ehci"; 312 reg = <0x01c1b000 0x100>; 313 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&ccu CLK_BUS_EHCI1>; 315 resets = <&ccu RST_BUS_EHCI1>; 316 phys = <&usbphy 2>; 317 phy-names = "usb"; 318 status = "disabled"; 319 }; 320 321 ccu: clock@1c20000 { 322 compatible = "allwinner,sun8i-a83t-ccu"; 323 reg = <0x01c20000 0x400>; 324 clocks = <&osc24M>, <&osc16Md512>; 325 clock-names = "hosc", "losc"; 326 #clock-cells = <1>; 327 #reset-cells = <1>; 328 }; 329 330 pio: pinctrl@1c20800 { 331 compatible = "allwinner,sun8i-a83t-pinctrl"; 332 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 335 reg = <0x01c20800 0x400>; 336 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>; 337 clock-names = "apb", "hosc", "losc"; 338 gpio-controller; 339 interrupt-controller; 340 #interrupt-cells = <3>; 341 #gpio-cells = <3>; 342 343 mmc0_pins: mmc0-pins { 344 pins = "PF0", "PF1", "PF2", 345 "PF3", "PF4", "PF5"; 346 function = "mmc0"; 347 drive-strength = <30>; 348 bias-pull-up; 349 }; 350 351 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { 352 pins = "PC5", "PC6", "PC8", "PC9", 353 "PC10", "PC11", "PC12", "PC13", 354 "PC14", "PC15", "PC16"; 355 function = "mmc2"; 356 drive-strength = <30>; 357 bias-pull-up; 358 }; 359 360 spdif_tx_pin: spdif-tx-pin { 361 pins = "PE18"; 362 function = "spdif"; 363 }; 364 365 uart0_pb_pins: uart0-pb-pins { 366 pins = "PB9", "PB10"; 367 function = "uart0"; 368 }; 369 370 uart0_pf_pins: uart0-pf-pins { 371 pins = "PF2", "PF4"; 372 function = "uart0"; 373 }; 374 }; 375 376 timer@1c20c00 { 377 compatible = "allwinner,sun4i-a10-timer"; 378 reg = <0x01c20c00 0xa0>; 379 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&osc24M>; 382 }; 383 384 watchdog@1c20ca0 { 385 compatible = "allwinner,sun6i-a31-wdt"; 386 reg = <0x01c20ca0 0x20>; 387 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&osc24M>; 389 }; 390 391 spdif: spdif@1c21000 { 392 #sound-dai-cells = <0>; 393 compatible = "allwinner,sun8i-a83t-spdif", 394 "allwinner,sun8i-h3-spdif"; 395 reg = <0x01c21000 0x400>; 396 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 398 resets = <&ccu RST_BUS_SPDIF>; 399 clock-names = "apb", "spdif"; 400 dmas = <&dma 2>; 401 dma-names = "tx"; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&spdif_tx_pin>; 404 status = "disabled"; 405 }; 406 407 uart0: serial@01c28000 { 408 compatible = "snps,dw-apb-uart"; 409 reg = <0x01c28000 0x400>; 410 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 411 reg-shift = <2>; 412 reg-io-width = <4>; 413 clocks = <&ccu CLK_BUS_UART0>; 414 resets = <&ccu RST_BUS_UART0>; 415 status = "disabled"; 416 }; 417 418 gic: interrupt-controller@1c81000 { 419 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 420 reg = <0x01c81000 0x1000>, 421 <0x01c82000 0x2000>, 422 <0x01c84000 0x2000>, 423 <0x01c86000 0x2000>; 424 interrupt-controller; 425 #interrupt-cells = <3>; 426 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 427 }; 428 429 r_intc: interrupt-controller@1f00c00 { 430 compatible = "allwinner,sun8i-a83t-r-intc", 431 "allwinner,sun6i-a31-r-intc"; 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 reg = <0x01f00c00 0x400>; 435 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 436 }; 437 438 r_ccu: clock@1f01400 { 439 compatible = "allwinner,sun8i-a83t-r-ccu"; 440 reg = <0x01f01400 0x400>; 441 clocks = <&osc24M>, <&osc16Md512>, <&osc16M>, 442 <&ccu 6>; 443 clock-names = "hosc", "losc", "iosc", "pll-periph"; 444 #clock-cells = <1>; 445 #reset-cells = <1>; 446 }; 447 448 r_pio: pinctrl@1f02c00 { 449 compatible = "allwinner,sun8i-a83t-r-pinctrl"; 450 reg = <0x01f02c00 0x400>; 451 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, 453 <&osc16Md512>; 454 clock-names = "apb", "hosc", "losc"; 455 gpio-controller; 456 #gpio-cells = <3>; 457 interrupt-controller; 458 #interrupt-cells = <3>; 459 460 r_rsb_pins: r-rsb-pins { 461 pins = "PL0", "PL1"; 462 function = "s_rsb"; 463 drive-strength = <20>; 464 bias-pull-up; 465 }; 466 }; 467 468 r_rsb: rsb@1f03400 { 469 compatible = "allwinner,sun8i-a83t-rsb", 470 "allwinner,sun8i-a23-rsb"; 471 reg = <0x01f03400 0x400>; 472 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&r_ccu CLK_APB0_RSB>; 474 clock-frequency = <3000000>; 475 resets = <&r_ccu RST_APB0_RSB>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&r_rsb_pins>; 478 status = "disabled"; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 }; 482 }; 483}; 484