1/* 2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/sun8i-h3-ccu.h> 44#include <dt-bindings/clock/sun8i-r-ccu.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/reset/sun8i-h3-ccu.h> 47#include <dt-bindings/reset/sun8i-r-ccu.h> 48 49/ { 50 interrupt-parent = <&gic>; 51 #address-cells = <1>; 52 #size-cells = <1>; 53 54 clocks { 55 #address-cells = <1>; 56 #size-cells = <1>; 57 ranges; 58 59 osc24M: osc24M_clk { 60 #clock-cells = <0>; 61 compatible = "fixed-clock"; 62 clock-frequency = <24000000>; 63 clock-output-names = "osc24M"; 64 }; 65 66 osc32k: osc32k_clk { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <32768>; 70 clock-output-names = "osc32k"; 71 }; 72 73 iosc: internal-osc-clk { 74 #clock-cells = <0>; 75 compatible = "fixed-clock"; 76 clock-frequency = <16000000>; 77 clock-accuracy = <300000000>; 78 clock-output-names = "iosc"; 79 }; 80 }; 81 82 soc { 83 compatible = "simple-bus"; 84 #address-cells = <1>; 85 #size-cells = <1>; 86 ranges; 87 88 syscon: syscon@1c00000 { 89 compatible = "allwinner,sun8i-h3-system-controller", 90 "syscon"; 91 reg = <0x01c00000 0x1000>; 92 }; 93 94 dma: dma-controller@01c02000 { 95 compatible = "allwinner,sun8i-h3-dma"; 96 reg = <0x01c02000 0x1000>; 97 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&ccu CLK_BUS_DMA>; 99 resets = <&ccu RST_BUS_DMA>; 100 #dma-cells = <1>; 101 }; 102 103 mmc0: mmc@01c0f000 { 104 /* compatible and clocks are in per SoC .dtsi file */ 105 reg = <0x01c0f000 0x1000>; 106 resets = <&ccu RST_BUS_MMC0>; 107 reset-names = "ahb"; 108 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 109 status = "disabled"; 110 #address-cells = <1>; 111 #size-cells = <0>; 112 }; 113 114 mmc1: mmc@01c10000 { 115 /* compatible and clocks are in per SoC .dtsi file */ 116 reg = <0x01c10000 0x1000>; 117 resets = <&ccu RST_BUS_MMC1>; 118 reset-names = "ahb"; 119 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 120 status = "disabled"; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 }; 124 125 mmc2: mmc@01c11000 { 126 /* compatible and clocks are in per SoC .dtsi file */ 127 reg = <0x01c11000 0x1000>; 128 resets = <&ccu RST_BUS_MMC2>; 129 reset-names = "ahb"; 130 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 131 status = "disabled"; 132 #address-cells = <1>; 133 #size-cells = <0>; 134 }; 135 136 usb_otg: usb@01c19000 { 137 compatible = "allwinner,sun8i-h3-musb"; 138 reg = <0x01c19000 0x400>; 139 clocks = <&ccu CLK_BUS_OTG>; 140 resets = <&ccu RST_BUS_OTG>; 141 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 142 interrupt-names = "mc"; 143 phys = <&usbphy 0>; 144 phy-names = "usb"; 145 extcon = <&usbphy 0>; 146 status = "disabled"; 147 }; 148 149 usbphy: phy@01c19400 { 150 compatible = "allwinner,sun8i-h3-usb-phy"; 151 reg = <0x01c19400 0x2c>, 152 <0x01c1a800 0x4>, 153 <0x01c1b800 0x4>, 154 <0x01c1c800 0x4>, 155 <0x01c1d800 0x4>; 156 reg-names = "phy_ctrl", 157 "pmu0", 158 "pmu1", 159 "pmu2", 160 "pmu3"; 161 clocks = <&ccu CLK_USB_PHY0>, 162 <&ccu CLK_USB_PHY1>, 163 <&ccu CLK_USB_PHY2>, 164 <&ccu CLK_USB_PHY3>; 165 clock-names = "usb0_phy", 166 "usb1_phy", 167 "usb2_phy", 168 "usb3_phy"; 169 resets = <&ccu RST_USB_PHY0>, 170 <&ccu RST_USB_PHY1>, 171 <&ccu RST_USB_PHY2>, 172 <&ccu RST_USB_PHY3>; 173 reset-names = "usb0_reset", 174 "usb1_reset", 175 "usb2_reset", 176 "usb3_reset"; 177 status = "disabled"; 178 #phy-cells = <1>; 179 }; 180 181 ehci0: usb@01c1a000 { 182 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 183 reg = <0x01c1a000 0x100>; 184 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; 186 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; 187 status = "disabled"; 188 }; 189 190 ohci0: usb@01c1a400 { 191 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 192 reg = <0x01c1a400 0x100>; 193 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, 195 <&ccu CLK_USB_OHCI0>; 196 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; 197 status = "disabled"; 198 }; 199 200 ehci1: usb@01c1b000 { 201 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 202 reg = <0x01c1b000 0x100>; 203 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; 205 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; 206 phys = <&usbphy 1>; 207 phy-names = "usb"; 208 status = "disabled"; 209 }; 210 211 ohci1: usb@01c1b400 { 212 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 213 reg = <0x01c1b400 0x100>; 214 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, 216 <&ccu CLK_USB_OHCI1>; 217 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; 218 phys = <&usbphy 1>; 219 phy-names = "usb"; 220 status = "disabled"; 221 }; 222 223 ehci2: usb@01c1c000 { 224 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 225 reg = <0x01c1c000 0x100>; 226 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; 228 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; 229 phys = <&usbphy 2>; 230 phy-names = "usb"; 231 status = "disabled"; 232 }; 233 234 ohci2: usb@01c1c400 { 235 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 236 reg = <0x01c1c400 0x100>; 237 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, 239 <&ccu CLK_USB_OHCI2>; 240 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; 241 phys = <&usbphy 2>; 242 phy-names = "usb"; 243 status = "disabled"; 244 }; 245 246 ehci3: usb@01c1d000 { 247 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 248 reg = <0x01c1d000 0x100>; 249 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; 251 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; 252 phys = <&usbphy 3>; 253 phy-names = "usb"; 254 status = "disabled"; 255 }; 256 257 ohci3: usb@01c1d400 { 258 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 259 reg = <0x01c1d400 0x100>; 260 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, 262 <&ccu CLK_USB_OHCI3>; 263 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; 264 phys = <&usbphy 3>; 265 phy-names = "usb"; 266 status = "disabled"; 267 }; 268 269 ccu: clock@01c20000 { 270 /* compatible is in per SoC .dtsi file */ 271 reg = <0x01c20000 0x400>; 272 clocks = <&osc24M>, <&osc32k>; 273 clock-names = "hosc", "losc"; 274 #clock-cells = <1>; 275 #reset-cells = <1>; 276 }; 277 278 pio: pinctrl@01c20800 { 279 /* compatible is in per SoC .dtsi file */ 280 reg = <0x01c20800 0x400>; 281 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; 284 clock-names = "apb", "hosc", "losc"; 285 gpio-controller; 286 #gpio-cells = <3>; 287 interrupt-controller; 288 #interrupt-cells = <3>; 289 290 emac_rgmii_pins: emac0 { 291 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 292 "PD5", "PD7", "PD8", "PD9", "PD10", 293 "PD12", "PD13", "PD15", "PD16", "PD17"; 294 function = "emac"; 295 drive-strength = <40>; 296 }; 297 298 i2c0_pins: i2c0 { 299 pins = "PA11", "PA12"; 300 function = "i2c0"; 301 }; 302 303 i2c1_pins: i2c1 { 304 pins = "PA18", "PA19"; 305 function = "i2c1"; 306 }; 307 308 i2c2_pins: i2c2 { 309 pins = "PE12", "PE13"; 310 function = "i2c2"; 311 }; 312 313 mmc0_pins_a: mmc0@0 { 314 pins = "PF0", "PF1", "PF2", "PF3", 315 "PF4", "PF5"; 316 function = "mmc0"; 317 drive-strength = <30>; 318 bias-pull-up; 319 }; 320 321 mmc0_cd_pin: mmc0_cd_pin@0 { 322 pins = "PF6"; 323 function = "gpio_in"; 324 bias-pull-up; 325 }; 326 327 mmc1_pins_a: mmc1@0 { 328 pins = "PG0", "PG1", "PG2", "PG3", 329 "PG4", "PG5"; 330 function = "mmc1"; 331 drive-strength = <30>; 332 bias-pull-up; 333 }; 334 335 mmc2_8bit_pins: mmc2_8bit { 336 pins = "PC5", "PC6", "PC8", 337 "PC9", "PC10", "PC11", 338 "PC12", "PC13", "PC14", 339 "PC15", "PC16"; 340 function = "mmc2"; 341 drive-strength = <30>; 342 bias-pull-up; 343 }; 344 345 spdif_tx_pins_a: spdif@0 { 346 pins = "PA17"; 347 function = "spdif"; 348 }; 349 350 spi0_pins: spi0 { 351 pins = "PC0", "PC1", "PC2", "PC3"; 352 function = "spi0"; 353 }; 354 355 spi1_pins: spi1 { 356 pins = "PA15", "PA16", "PA14", "PA13"; 357 function = "spi1"; 358 }; 359 360 uart0_pins_a: uart0@0 { 361 pins = "PA4", "PA5"; 362 function = "uart0"; 363 }; 364 365 uart1_pins: uart1 { 366 pins = "PG6", "PG7"; 367 function = "uart1"; 368 }; 369 370 uart1_rts_cts_pins: uart1_rts_cts { 371 pins = "PG8", "PG9"; 372 function = "uart1"; 373 }; 374 375 uart2_pins: uart2 { 376 pins = "PA0", "PA1"; 377 function = "uart2"; 378 }; 379 380 uart3_pins: uart3 { 381 pins = "PA13", "PA14"; 382 function = "uart3"; 383 }; 384 }; 385 386 timer@01c20c00 { 387 compatible = "allwinner,sun4i-a10-timer"; 388 reg = <0x01c20c00 0xa0>; 389 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&osc24M>; 392 }; 393 394 spi0: spi@01c68000 { 395 compatible = "allwinner,sun8i-h3-spi"; 396 reg = <0x01c68000 0x1000>; 397 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 399 clock-names = "ahb", "mod"; 400 dmas = <&dma 23>, <&dma 23>; 401 dma-names = "rx", "tx"; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&spi0_pins>; 404 resets = <&ccu RST_BUS_SPI0>; 405 status = "disabled"; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 }; 409 410 spi1: spi@01c69000 { 411 compatible = "allwinner,sun8i-h3-spi"; 412 reg = <0x01c69000 0x1000>; 413 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 415 clock-names = "ahb", "mod"; 416 dmas = <&dma 24>, <&dma 24>; 417 dma-names = "rx", "tx"; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&spi1_pins>; 420 resets = <&ccu RST_BUS_SPI1>; 421 status = "disabled"; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 }; 425 426 wdt0: watchdog@01c20ca0 { 427 compatible = "allwinner,sun6i-a31-wdt"; 428 reg = <0x01c20ca0 0x20>; 429 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 430 }; 431 432 spdif: spdif@01c21000 { 433 #sound-dai-cells = <0>; 434 compatible = "allwinner,sun8i-h3-spdif"; 435 reg = <0x01c21000 0x400>; 436 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 438 resets = <&ccu RST_BUS_SPDIF>; 439 clock-names = "apb", "spdif"; 440 dmas = <&dma 2>; 441 dma-names = "tx"; 442 status = "disabled"; 443 }; 444 445 pwm: pwm@01c21400 { 446 compatible = "allwinner,sun8i-h3-pwm"; 447 reg = <0x01c21400 0x8>; 448 clocks = <&osc24M>; 449 #pwm-cells = <3>; 450 status = "disabled"; 451 }; 452 453 codec: codec@01c22c00 { 454 #sound-dai-cells = <0>; 455 compatible = "allwinner,sun8i-h3-codec"; 456 reg = <0x01c22c00 0x400>; 457 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 459 clock-names = "apb", "codec"; 460 resets = <&ccu RST_BUS_CODEC>; 461 dmas = <&dma 15>, <&dma 15>; 462 dma-names = "rx", "tx"; 463 allwinner,codec-analog-controls = <&codec_analog>; 464 status = "disabled"; 465 }; 466 467 uart0: serial@01c28000 { 468 compatible = "snps,dw-apb-uart"; 469 reg = <0x01c28000 0x400>; 470 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 471 reg-shift = <2>; 472 reg-io-width = <4>; 473 clocks = <&ccu CLK_BUS_UART0>; 474 resets = <&ccu RST_BUS_UART0>; 475 dmas = <&dma 6>, <&dma 6>; 476 dma-names = "rx", "tx"; 477 status = "disabled"; 478 }; 479 480 uart1: serial@01c28400 { 481 compatible = "snps,dw-apb-uart"; 482 reg = <0x01c28400 0x400>; 483 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 484 reg-shift = <2>; 485 reg-io-width = <4>; 486 clocks = <&ccu CLK_BUS_UART1>; 487 resets = <&ccu RST_BUS_UART1>; 488 dmas = <&dma 7>, <&dma 7>; 489 dma-names = "rx", "tx"; 490 status = "disabled"; 491 }; 492 493 uart2: serial@01c28800 { 494 compatible = "snps,dw-apb-uart"; 495 reg = <0x01c28800 0x400>; 496 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 497 reg-shift = <2>; 498 reg-io-width = <4>; 499 clocks = <&ccu CLK_BUS_UART2>; 500 resets = <&ccu RST_BUS_UART2>; 501 dmas = <&dma 8>, <&dma 8>; 502 dma-names = "rx", "tx"; 503 status = "disabled"; 504 }; 505 506 uart3: serial@01c28c00 { 507 compatible = "snps,dw-apb-uart"; 508 reg = <0x01c28c00 0x400>; 509 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 510 reg-shift = <2>; 511 reg-io-width = <4>; 512 clocks = <&ccu CLK_BUS_UART3>; 513 resets = <&ccu RST_BUS_UART3>; 514 dmas = <&dma 9>, <&dma 9>; 515 dma-names = "rx", "tx"; 516 status = "disabled"; 517 }; 518 519 i2c0: i2c@01c2ac00 { 520 compatible = "allwinner,sun6i-a31-i2c"; 521 reg = <0x01c2ac00 0x400>; 522 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&ccu CLK_BUS_I2C0>; 524 resets = <&ccu RST_BUS_I2C0>; 525 pinctrl-names = "default"; 526 pinctrl-0 = <&i2c0_pins>; 527 status = "disabled"; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 }; 531 532 i2c1: i2c@01c2b000 { 533 compatible = "allwinner,sun6i-a31-i2c"; 534 reg = <0x01c2b000 0x400>; 535 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&ccu CLK_BUS_I2C1>; 537 resets = <&ccu RST_BUS_I2C1>; 538 pinctrl-names = "default"; 539 pinctrl-0 = <&i2c1_pins>; 540 status = "disabled"; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 }; 544 545 i2c2: i2c@01c2b400 { 546 compatible = "allwinner,sun6i-a31-i2c"; 547 reg = <0x01c2b000 0x400>; 548 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&ccu CLK_BUS_I2C2>; 550 resets = <&ccu RST_BUS_I2C2>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&i2c2_pins>; 553 status = "disabled"; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 }; 557 558 gic: interrupt-controller@01c81000 { 559 compatible = "arm,gic-400"; 560 reg = <0x01c81000 0x1000>, 561 <0x01c82000 0x2000>, 562 <0x01c84000 0x2000>, 563 <0x01c86000 0x2000>; 564 interrupt-controller; 565 #interrupt-cells = <3>; 566 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 567 }; 568 569 rtc: rtc@01f00000 { 570 compatible = "allwinner,sun6i-a31-rtc"; 571 reg = <0x01f00000 0x54>; 572 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 574 }; 575 576 r_ccu: clock@1f01400 { 577 compatible = "allwinner,sun8i-h3-r-ccu"; 578 reg = <0x01f01400 0x100>; 579 clocks = <&osc24M>, <&osc32k>, <&iosc>, 580 <&ccu 9>; 581 clock-names = "hosc", "losc", "iosc", "pll-periph"; 582 #clock-cells = <1>; 583 #reset-cells = <1>; 584 }; 585 586 codec_analog: codec-analog@01f015c0 { 587 compatible = "allwinner,sun8i-h3-codec-analog"; 588 reg = <0x01f015c0 0x4>; 589 }; 590 591 ir: ir@01f02000 { 592 compatible = "allwinner,sun5i-a13-ir"; 593 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 594 clock-names = "apb", "ir"; 595 resets = <&r_ccu RST_APB0_IR>; 596 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 597 reg = <0x01f02000 0x400>; 598 status = "disabled"; 599 }; 600 601 r_pio: pinctrl@01f02c00 { 602 compatible = "allwinner,sun8i-h3-r-pinctrl"; 603 reg = <0x01f02c00 0x400>; 604 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 606 clock-names = "apb", "hosc", "losc"; 607 gpio-controller; 608 #gpio-cells = <3>; 609 interrupt-controller; 610 #interrupt-cells = <3>; 611 612 ir_pins_a: ir@0 { 613 pins = "PL11"; 614 function = "s_cir_rx"; 615 }; 616 }; 617 }; 618}; 619