1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/input/input.h> 3#include "tegra30.dtsi" 4 5/* 6 * Toradex Colibri T30 Module Device Tree 7 * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E; IT: V1.1A 8 */ 9/ { 10 model = "Toradex Colibri T30"; 11 compatible = "toradex,colibri_t30", "nvidia,tegra30"; 12 13 memory { 14 reg = <0x80000000 0x40000000>; 15 }; 16 17 host1x@50000000 { 18 hdmi@54280000 { 19 vdd-supply = <&avdd_hdmi_3v3_reg>; 20 pll-supply = <&avdd_hdmi_pll_1v8_reg>; 21 22 nvidia,hpd-gpio = 23 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 24 nvidia,ddc-i2c-bus = <&hdmiddc>; 25 }; 26 }; 27 28 pinmux@70000868 { 29 pinctrl-names = "default"; 30 pinctrl-0 = <&state_default>; 31 32 state_default: pinmux { 33 /* Analogue Audio (On-module) */ 34 clk1_out_pw4 { 35 nvidia,pins = "clk1_out_pw4"; 36 nvidia,function = "extperiph1"; 37 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 38 nvidia,tristate = <TEGRA_PIN_DISABLE>; 39 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 40 }; 41 dap3_fs_pp0 { 42 nvidia,pins = "dap3_fs_pp0", 43 "dap3_sclk_pp3", 44 "dap3_din_pp1", 45 "dap3_dout_pp2"; 46 nvidia,function = "i2s2"; 47 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 48 nvidia,tristate = <TEGRA_PIN_DISABLE>; 49 }; 50 51 /* Colibri BL_ON */ 52 pv2 { 53 nvidia,pins = "pv2"; 54 nvidia,function = "rsvd4"; 55 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 56 nvidia,tristate = <TEGRA_PIN_DISABLE>; 57 }; 58 59 /* Colibri Backlight PWM<A> */ 60 sdmmc3_dat3_pb4 { 61 nvidia,pins = "sdmmc3_dat3_pb4"; 62 nvidia,function = "pwm0"; 63 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 64 nvidia,tristate = <TEGRA_PIN_DISABLE>; 65 }; 66 67 /* Colibri CAN_INT */ 68 kb_row8_ps0 { 69 nvidia,pins = "kb_row8_ps0"; 70 nvidia,function = "kbc"; 71 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 72 nvidia,tristate = <TEGRA_PIN_DISABLE>; 73 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 74 }; 75 76 /* 77 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE 78 * todays display need DE, disable LCD_M1 79 */ 80 lcd_m1_pw1 { 81 nvidia,pins = "lcd_m1_pw1"; 82 nvidia,function = "rsvd3"; 83 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 84 nvidia,tristate = <TEGRA_PIN_DISABLE>; 85 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 86 }; 87 88 /* Colibri MMC */ 89 kb_row10_ps2 { 90 nvidia,pins = "kb_row10_ps2"; 91 nvidia,function = "sdmmc2"; 92 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 93 nvidia,tristate = <TEGRA_PIN_DISABLE>; 94 }; 95 kb_row11_ps3 { 96 nvidia,pins = "kb_row11_ps3", 97 "kb_row12_ps4", 98 "kb_row13_ps5", 99 "kb_row14_ps6", 100 "kb_row15_ps7"; 101 nvidia,function = "sdmmc2"; 102 nvidia,pull = <TEGRA_PIN_PULL_UP>; 103 nvidia,tristate = <TEGRA_PIN_DISABLE>; 104 }; 105 106 /* Colibri SSP */ 107 ulpi_clk_py0 { 108 nvidia,pins = "ulpi_clk_py0", 109 "ulpi_dir_py1", 110 "ulpi_nxt_py2", 111 "ulpi_stp_py3"; 112 nvidia,function = "spi1"; 113 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 114 nvidia,tristate = <TEGRA_PIN_DISABLE>; 115 }; 116 sdmmc3_dat6_pd3 { 117 nvidia,pins = "sdmmc3_dat6_pd3", 118 "sdmmc3_dat7_pd4"; 119 nvidia,function = "spdif"; 120 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 121 nvidia,tristate = <TEGRA_PIN_ENABLE>; 122 }; 123 124 /* Colibri UART_A */ 125 ulpi_data0 { 126 nvidia,pins = "ulpi_data0_po1", 127 "ulpi_data1_po2", 128 "ulpi_data2_po3", 129 "ulpi_data3_po4", 130 "ulpi_data4_po5", 131 "ulpi_data5_po6", 132 "ulpi_data6_po7", 133 "ulpi_data7_po0"; 134 nvidia,function = "uarta"; 135 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 136 nvidia,tristate = <TEGRA_PIN_DISABLE>; 137 }; 138 139 /* Colibri UART_B */ 140 gmi_a16_pj7 { 141 nvidia,pins = "gmi_a16_pj7", 142 "gmi_a17_pb0", 143 "gmi_a18_pb1", 144 "gmi_a19_pk7"; 145 nvidia,function = "uartd"; 146 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 147 nvidia,tristate = <TEGRA_PIN_DISABLE>; 148 }; 149 150 /* Colibri UART_C */ 151 uart2_rxd { 152 nvidia,pins = "uart2_rxd_pc3", 153 "uart2_txd_pc2"; 154 nvidia,function = "uartb"; 155 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 156 nvidia,tristate = <TEGRA_PIN_DISABLE>; 157 }; 158 159 /* eMMC */ 160 sdmmc4_clk_pcc4 { 161 nvidia,pins = "sdmmc4_clk_pcc4", 162 "sdmmc4_rst_n_pcc3"; 163 nvidia,function = "sdmmc4"; 164 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 165 nvidia,tristate = <TEGRA_PIN_DISABLE>; 166 }; 167 sdmmc4_dat0_paa0 { 168 nvidia,pins = "sdmmc4_dat0_paa0", 169 "sdmmc4_dat1_paa1", 170 "sdmmc4_dat2_paa2", 171 "sdmmc4_dat3_paa3", 172 "sdmmc4_dat4_paa4", 173 "sdmmc4_dat5_paa5", 174 "sdmmc4_dat6_paa6", 175 "sdmmc4_dat7_paa7"; 176 nvidia,function = "sdmmc4"; 177 nvidia,pull = <TEGRA_PIN_PULL_UP>; 178 nvidia,tristate = <TEGRA_PIN_DISABLE>; 179 }; 180 181 /* Power I2C (On-module) */ 182 pwr_i2c_scl_pz6 { 183 nvidia,pins = "pwr_i2c_scl_pz6", 184 "pwr_i2c_sda_pz7"; 185 nvidia,function = "i2cpwr"; 186 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 187 nvidia,tristate = <TEGRA_PIN_DISABLE>; 188 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 189 nvidia,lock = <TEGRA_PIN_DISABLE>; 190 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 191 }; 192 193 /* 194 * THERMD_ALERT#, unlatched I2C address pin of LM95245 195 * temperature sensor therefore requires disabling for 196 * now 197 */ 198 lcd_dc1_pd2 { 199 nvidia,pins = "lcd_dc1_pd2"; 200 nvidia,function = "rsvd3"; 201 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 202 nvidia,tristate = <TEGRA_PIN_DISABLE>; 203 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 204 }; 205 206 /* TOUCH_PEN_INT# */ 207 pv0 { 208 nvidia,pins = "pv0"; 209 nvidia,function = "rsvd1"; 210 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 211 nvidia,tristate = <TEGRA_PIN_DISABLE>; 212 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 213 }; 214 }; 215 }; 216 217 hdmiddc: i2c@7000c700 { 218 clock-frequency = <100000>; 219 }; 220 221 /* 222 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 223 * touch screen controller 224 */ 225 i2c@7000d000 { 226 status = "okay"; 227 clock-frequency = <100000>; 228 229 /* SGTL5000 audio codec */ 230 sgtl5000: codec@a { 231 compatible = "fsl,sgtl5000"; 232 reg = <0x0a>; 233 VDDA-supply = <&sys_3v3_reg>; 234 VDDIO-supply = <&sys_3v3_reg>; 235 clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; 236 }; 237 238 pmic: tps65911@2d { 239 compatible = "ti,tps65911"; 240 reg = <0x2d>; 241 242 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 243 #interrupt-cells = <2>; 244 interrupt-controller; 245 246 ti,system-power-controller; 247 248 #gpio-cells = <2>; 249 gpio-controller; 250 251 vcc1-supply = <&sys_3v3_reg>; 252 vcc2-supply = <&sys_3v3_reg>; 253 vcc3-supply = <&vio_reg>; 254 vcc4-supply = <&sys_3v3_reg>; 255 vcc5-supply = <&sys_3v3_reg>; 256 vcc6-supply = <&vio_reg>; 257 vcc7-supply = <&charge_pump_5v0_reg>; 258 vccio-supply = <&sys_3v3_reg>; 259 260 regulators { 261 /* SW1: +V1.35_VDDIO_DDR */ 262 vdd1_reg: vdd1 { 263 regulator-name = "vddio_ddr_1v35"; 264 regulator-min-microvolt = <1350000>; 265 regulator-max-microvolt = <1350000>; 266 regulator-always-on; 267 }; 268 269 /* SW2: unused */ 270 271 /* SW CTRL: +V1.0_VDD_CPU */ 272 vddctrl_reg: vddctrl { 273 regulator-name = "vdd_cpu,vdd_sys"; 274 regulator-min-microvolt = <1150000>; 275 regulator-max-microvolt = <1150000>; 276 regulator-always-on; 277 }; 278 279 /* SWIO: +V1.8 */ 280 vio_reg: vio { 281 regulator-name = "vdd_1v8_gen"; 282 regulator-min-microvolt = <1800000>; 283 regulator-max-microvolt = <1800000>; 284 regulator-always-on; 285 }; 286 287 /* LDO1: unused */ 288 289 /* 290 * EN_+V3.3 switching via FET: 291 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN 292 * see also 3v3 fixed supply 293 */ 294 ldo2_reg: ldo2 { 295 regulator-name = "en_3v3"; 296 regulator-min-microvolt = <3300000>; 297 regulator-max-microvolt = <3300000>; 298 regulator-always-on; 299 }; 300 301 /* LDO3: unused */ 302 303 /* +V1.2_VDD_RTC */ 304 ldo4_reg: ldo4 { 305 regulator-name = "vdd_rtc"; 306 regulator-min-microvolt = <1200000>; 307 regulator-max-microvolt = <1200000>; 308 regulator-always-on; 309 }; 310 311 /* 312 * +V2.8_AVDD_VDAC: 313 * only required for analog RGB 314 */ 315 ldo5_reg: ldo5 { 316 regulator-name = "avdd_vdac"; 317 regulator-min-microvolt = <2800000>; 318 regulator-max-microvolt = <2800000>; 319 regulator-always-on; 320 }; 321 322 /* 323 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V 324 * but LDO6 can't set voltage in 50mV 325 * granularity 326 */ 327 ldo6_reg: ldo6 { 328 regulator-name = "avdd_plle"; 329 regulator-min-microvolt = <1100000>; 330 regulator-max-microvolt = <1100000>; 331 }; 332 333 /* +V1.2_AVDD_PLL */ 334 ldo7_reg: ldo7 { 335 regulator-name = "avdd_pll"; 336 regulator-min-microvolt = <1200000>; 337 regulator-max-microvolt = <1200000>; 338 regulator-always-on; 339 }; 340 341 /* +V1.0_VDD_DDR_HS */ 342 ldo8_reg: ldo8 { 343 regulator-name = "vdd_ddr_hs"; 344 regulator-min-microvolt = <1000000>; 345 regulator-max-microvolt = <1000000>; 346 regulator-always-on; 347 }; 348 }; 349 }; 350 351 /* STMPE811 touch screen controller */ 352 stmpe811@41 { 353 compatible = "st,stmpe811"; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 reg = <0x41>; 357 interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; 358 interrupt-parent = <&gpio>; 359 interrupt-controller; 360 id = <0>; 361 blocks = <0x5>; 362 irq-trigger = <0x1>; 363 364 stmpe_touchscreen { 365 compatible = "st,stmpe-ts"; 366 reg = <0>; 367 /* 3.25 MHz ADC clock speed */ 368 st,adc-freq = <1>; 369 /* 8 sample average control */ 370 st,ave-ctrl = <3>; 371 /* 7 length fractional part in z */ 372 st,fraction-z = <7>; 373 /* 374 * 50 mA typical 80 mA max touchscreen drivers 375 * current limit value 376 */ 377 st,i-drive = <1>; 378 /* 12-bit ADC */ 379 st,mod-12b = <1>; 380 /* internal ADC reference */ 381 st,ref-sel = <0>; 382 /* ADC converstion time: 80 clocks */ 383 st,sample-time = <4>; 384 /* 1 ms panel driver settling time */ 385 st,settling = <3>; 386 /* 5 ms touch detect interrupt delay */ 387 st,touch-det-delay = <5>; 388 }; 389 }; 390 391 /* 392 * LM95245 temperature sensor 393 * Note: OVERT_N directly connected to PMIC PWRDN 394 */ 395 temp-sensor@4c { 396 compatible = "national,lm95245"; 397 reg = <0x4c>; 398 }; 399 400 /* SW: +V1.2_VDD_CORE */ 401 tps62362@60 { 402 compatible = "ti,tps62362"; 403 reg = <0x60>; 404 405 regulator-name = "tps62362-vout"; 406 regulator-min-microvolt = <900000>; 407 regulator-max-microvolt = <1400000>; 408 regulator-boot-on; 409 regulator-always-on; 410 ti,vsel0-state-low; 411 /* VSEL1: EN_CORE_DVFS_N low for DVFS */ 412 ti,vsel1-state-low; 413 }; 414 }; 415 416 pmc@7000e400 { 417 nvidia,invert-interrupt; 418 nvidia,suspend-mode = <1>; 419 nvidia,cpu-pwr-good-time = <5000>; 420 nvidia,cpu-pwr-off-time = <5000>; 421 nvidia,core-pwr-good-time = <3845 3845>; 422 nvidia,core-pwr-off-time = <0>; 423 nvidia,core-power-req-active-high; 424 nvidia,sys-clock-req-active-high; 425 }; 426 427 ahub@70080000 { 428 i2s@70080500 { 429 status = "okay"; 430 }; 431 }; 432 433 /* eMMC */ 434 sdhci@78000600 { 435 status = "okay"; 436 bus-width = <8>; 437 non-removable; 438 }; 439 440 /* EHCI instance 1: USB2_DP/N -> AX88772B */ 441 usb@7d004000 { 442 status = "okay"; 443 }; 444 445 usb-phy@7d004000 { 446 status = "okay"; 447 nvidia,is-wired = <1>; 448 }; 449 450 clocks { 451 compatible = "simple-bus"; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 455 clk32k_in: clk@0 { 456 compatible = "fixed-clock"; 457 reg = <0>; 458 #clock-cells = <0>; 459 clock-frequency = <32768>; 460 }; 461 }; 462 463 regulators { 464 compatible = "simple-bus"; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 468 avdd_hdmi_pll_1v8_reg: regulator@100 { 469 compatible = "regulator-fixed"; 470 reg = <100>; 471 regulator-name = "+V1.8_AVDD_HDMI_PLL"; 472 regulator-min-microvolt = <1800000>; 473 regulator-max-microvolt = <1800000>; 474 enable-active-high; 475 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; 476 vin-supply = <&vio_reg>; 477 }; 478 479 sys_3v3_reg: regulator@101 { 480 compatible = "regulator-fixed"; 481 reg = <101>; 482 regulator-name = "3v3"; 483 regulator-min-microvolt = <3300000>; 484 regulator-max-microvolt = <3300000>; 485 regulator-always-on; 486 }; 487 488 avdd_hdmi_3v3_reg: regulator@102 { 489 compatible = "regulator-fixed"; 490 reg = <102>; 491 regulator-name = "+V3.3_AVDD_HDMI"; 492 regulator-min-microvolt = <3300000>; 493 regulator-max-microvolt = <3300000>; 494 enable-active-high; 495 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; 496 vin-supply = <&sys_3v3_reg>; 497 }; 498 499 charge_pump_5v0_reg: regulator@103 { 500 compatible = "regulator-fixed"; 501 reg = <103>; 502 regulator-name = "5v0"; 503 regulator-min-microvolt = <5000000>; 504 regulator-max-microvolt = <5000000>; 505 regulator-always-on; 506 }; 507 }; 508 509 sound { 510 compatible = "toradex,tegra-audio-sgtl5000-colibri_t30", 511 "nvidia,tegra-audio-sgtl5000"; 512 nvidia,model = "Toradex Colibri T30"; 513 nvidia,audio-routing = 514 "Headphone Jack", "HP_OUT", 515 "LINE_IN", "Line In Jack", 516 "MIC_IN", "Mic Jack"; 517 nvidia,i2s-controller = <&tegra_i2s2>; 518 nvidia,audio-codec = <&sgtl5000>; 519 clocks = <&tegra_car TEGRA30_CLK_PLL_A>, 520 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 521 <&tegra_car TEGRA30_CLK_EXTERN1>; 522 clock-names = "pll_a", "pll_a_out0", "mclk"; 523 }; 524}; 525