1/* 2 * Device Tree Source for UniPhier PXs2 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10/ { 11 compatible = "socionext,uniphier-pxs2"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a9"; 22 reg = <0>; 23 clocks = <&sys_clk 32>; 24 enable-method = "psci"; 25 next-level-cache = <&l2>; 26 operating-points-v2 = <&cpu_opp>; 27 }; 28 29 cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a9"; 32 reg = <1>; 33 clocks = <&sys_clk 32>; 34 enable-method = "psci"; 35 next-level-cache = <&l2>; 36 operating-points-v2 = <&cpu_opp>; 37 }; 38 39 cpu@2 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a9"; 42 reg = <2>; 43 clocks = <&sys_clk 32>; 44 enable-method = "psci"; 45 next-level-cache = <&l2>; 46 operating-points-v2 = <&cpu_opp>; 47 }; 48 49 cpu@3 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a9"; 52 reg = <3>; 53 clocks = <&sys_clk 32>; 54 enable-method = "psci"; 55 next-level-cache = <&l2>; 56 operating-points-v2 = <&cpu_opp>; 57 }; 58 }; 59 60 cpu_opp: opp_table { 61 compatible = "operating-points-v2"; 62 opp-shared; 63 64 opp-100000000 { 65 opp-hz = /bits/ 64 <100000000>; 66 clock-latency-ns = <300>; 67 }; 68 opp-150000000 { 69 opp-hz = /bits/ 64 <150000000>; 70 clock-latency-ns = <300>; 71 }; 72 opp-200000000 { 73 opp-hz = /bits/ 64 <200000000>; 74 clock-latency-ns = <300>; 75 }; 76 opp-300000000 { 77 opp-hz = /bits/ 64 <300000000>; 78 clock-latency-ns = <300>; 79 }; 80 opp-400000000 { 81 opp-hz = /bits/ 64 <400000000>; 82 clock-latency-ns = <300>; 83 }; 84 opp-600000000 { 85 opp-hz = /bits/ 64 <600000000>; 86 clock-latency-ns = <300>; 87 }; 88 opp-800000000 { 89 opp-hz = /bits/ 64 <800000000>; 90 clock-latency-ns = <300>; 91 }; 92 opp-1200000000 { 93 opp-hz = /bits/ 64 <1200000000>; 94 clock-latency-ns = <300>; 95 }; 96 }; 97 98 psci { 99 compatible = "arm,psci-0.2"; 100 method = "smc"; 101 }; 102 103 clocks { 104 refclk: ref { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <25000000>; 108 }; 109 110 arm_timer_clk: arm_timer_clk { 111 #clock-cells = <0>; 112 compatible = "fixed-clock"; 113 clock-frequency = <50000000>; 114 }; 115 }; 116 117 soc { 118 compatible = "simple-bus"; 119 #address-cells = <1>; 120 #size-cells = <1>; 121 ranges; 122 interrupt-parent = <&intc>; 123 124 l2: l2-cache@500c0000 { 125 compatible = "socionext,uniphier-system-cache"; 126 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, 127 <0x506c0000 0x400>; 128 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; 129 cache-unified; 130 cache-size = <(1280 * 1024)>; 131 cache-sets = <512>; 132 cache-line-size = <128>; 133 cache-level = <2>; 134 }; 135 136 serial0: serial@54006800 { 137 compatible = "socionext,uniphier-uart"; 138 status = "disabled"; 139 reg = <0x54006800 0x40>; 140 interrupts = <0 33 4>; 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pinctrl_uart0>; 143 clocks = <&peri_clk 0>; 144 }; 145 146 serial1: serial@54006900 { 147 compatible = "socionext,uniphier-uart"; 148 status = "disabled"; 149 reg = <0x54006900 0x40>; 150 interrupts = <0 35 4>; 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_uart1>; 153 clocks = <&peri_clk 1>; 154 }; 155 156 serial2: serial@54006a00 { 157 compatible = "socionext,uniphier-uart"; 158 status = "disabled"; 159 reg = <0x54006a00 0x40>; 160 interrupts = <0 37 4>; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_uart2>; 163 clocks = <&peri_clk 2>; 164 }; 165 166 serial3: serial@54006b00 { 167 compatible = "socionext,uniphier-uart"; 168 status = "disabled"; 169 reg = <0x54006b00 0x40>; 170 interrupts = <0 177 4>; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pinctrl_uart3>; 173 clocks = <&peri_clk 3>; 174 }; 175 176 i2c0: i2c@58780000 { 177 compatible = "socionext,uniphier-fi2c"; 178 status = "disabled"; 179 reg = <0x58780000 0x80>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 interrupts = <0 41 4>; 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pinctrl_i2c0>; 185 clocks = <&peri_clk 4>; 186 clock-frequency = <100000>; 187 }; 188 189 i2c1: i2c@58781000 { 190 compatible = "socionext,uniphier-fi2c"; 191 status = "disabled"; 192 reg = <0x58781000 0x80>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 interrupts = <0 42 4>; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&pinctrl_i2c1>; 198 clocks = <&peri_clk 5>; 199 clock-frequency = <100000>; 200 }; 201 202 i2c2: i2c@58782000 { 203 compatible = "socionext,uniphier-fi2c"; 204 status = "disabled"; 205 reg = <0x58782000 0x80>; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 interrupts = <0 43 4>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_i2c2>; 211 clocks = <&peri_clk 6>; 212 clock-frequency = <100000>; 213 }; 214 215 i2c3: i2c@58783000 { 216 compatible = "socionext,uniphier-fi2c"; 217 status = "disabled"; 218 reg = <0x58783000 0x80>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 interrupts = <0 44 4>; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&pinctrl_i2c3>; 224 clocks = <&peri_clk 7>; 225 clock-frequency = <100000>; 226 }; 227 228 /* chip-internal connection for DMD */ 229 i2c4: i2c@58784000 { 230 compatible = "socionext,uniphier-fi2c"; 231 reg = <0x58784000 0x80>; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 interrupts = <0 45 4>; 235 clocks = <&peri_clk 8>; 236 clock-frequency = <400000>; 237 }; 238 239 /* chip-internal connection for STM */ 240 i2c5: i2c@58785000 { 241 compatible = "socionext,uniphier-fi2c"; 242 reg = <0x58785000 0x80>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 interrupts = <0 25 4>; 246 clocks = <&peri_clk 9>; 247 clock-frequency = <400000>; 248 }; 249 250 /* chip-internal connection for HDMI */ 251 i2c6: i2c@58786000 { 252 compatible = "socionext,uniphier-fi2c"; 253 reg = <0x58786000 0x80>; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 interrupts = <0 26 4>; 257 clocks = <&peri_clk 10>; 258 clock-frequency = <400000>; 259 }; 260 261 system_bus: system-bus@58c00000 { 262 compatible = "socionext,uniphier-system-bus"; 263 status = "disabled"; 264 reg = <0x58c00000 0x400>; 265 #address-cells = <2>; 266 #size-cells = <1>; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&pinctrl_system_bus>; 269 }; 270 271 smpctrl@59801000 { 272 compatible = "socionext,uniphier-smpctrl"; 273 reg = <0x59801000 0x400>; 274 }; 275 276 sdctrl@59810000 { 277 compatible = "socionext,uniphier-pxs2-sdctrl", 278 "simple-mfd", "syscon"; 279 reg = <0x59810000 0x400>; 280 281 sd_clk: clock { 282 compatible = "socionext,uniphier-pxs2-sd-clock"; 283 #clock-cells = <1>; 284 }; 285 286 sd_rst: reset { 287 compatible = "socionext,uniphier-pxs2-sd-reset"; 288 #reset-cells = <1>; 289 }; 290 }; 291 292 perictrl@59820000 { 293 compatible = "socionext,uniphier-pxs2-perictrl", 294 "simple-mfd", "syscon"; 295 reg = <0x59820000 0x200>; 296 297 peri_clk: clock { 298 compatible = "socionext,uniphier-pxs2-peri-clock"; 299 #clock-cells = <1>; 300 }; 301 302 peri_rst: reset { 303 compatible = "socionext,uniphier-pxs2-peri-reset"; 304 #reset-cells = <1>; 305 }; 306 }; 307 308 soc-glue@5f800000 { 309 compatible = "socionext,uniphier-pxs2-soc-glue", 310 "simple-mfd", "syscon"; 311 reg = <0x5f800000 0x2000>; 312 313 pinctrl: pinctrl { 314 compatible = "socionext,uniphier-pxs2-pinctrl"; 315 }; 316 }; 317 318 aidet: aidet@5fc20000 { 319 compatible = "socionext,uniphier-pxs2-aidet"; 320 reg = <0x5fc20000 0x200>; 321 interrupt-controller; 322 #interrupt-cells = <2>; 323 }; 324 325 timer@60000200 { 326 compatible = "arm,cortex-a9-global-timer"; 327 reg = <0x60000200 0x20>; 328 interrupts = <1 11 0xf04>; 329 clocks = <&arm_timer_clk>; 330 }; 331 332 timer@60000600 { 333 compatible = "arm,cortex-a9-twd-timer"; 334 reg = <0x60000600 0x20>; 335 interrupts = <1 13 0xf04>; 336 clocks = <&arm_timer_clk>; 337 }; 338 339 intc: interrupt-controller@60001000 { 340 compatible = "arm,cortex-a9-gic"; 341 reg = <0x60001000 0x1000>, 342 <0x60000100 0x100>; 343 #interrupt-cells = <3>; 344 interrupt-controller; 345 }; 346 347 sysctrl@61840000 { 348 compatible = "socionext,uniphier-pxs2-sysctrl", 349 "simple-mfd", "syscon"; 350 reg = <0x61840000 0x10000>; 351 352 sys_clk: clock { 353 compatible = "socionext,uniphier-pxs2-clock"; 354 #clock-cells = <1>; 355 }; 356 357 sys_rst: reset { 358 compatible = "socionext,uniphier-pxs2-reset"; 359 #reset-cells = <1>; 360 }; 361 }; 362 363 nand: nand@68000000 { 364 compatible = "socionext,uniphier-denali-nand-v5b"; 365 status = "disabled"; 366 reg-names = "nand_data", "denali_reg"; 367 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 368 interrupts = <0 65 4>; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&pinctrl_nand2cs>; 371 clocks = <&sys_clk 2>; 372 }; 373 }; 374}; 375 376#include "uniphier-pinctrl.dtsi" 377