1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ARM Ltd. Versatile Express 4 * 5 * CoreTile Express A15x2 (version with Test Chip 1) 6 * Cortex-A15 MPCore (V2P-CA15) 7 * 8 * HBI-0237A 9 */ 10 11/dts-v1/; 12 13/ { 14 model = "V2P-CA15"; 15 arm,hbi = <0x237>; 16 arm,vexpress,site = <0xf>; 17 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 aliases { 25 serial0 = &v2m_serial0; 26 serial1 = &v2m_serial1; 27 serial2 = &v2m_serial2; 28 serial3 = &v2m_serial3; 29 i2c0 = &v2m_i2c_dvi; 30 i2c1 = &v2m_i2c_pcie; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a15"; 40 reg = <0>; 41 }; 42 43 cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a15"; 46 reg = <1>; 47 }; 48 }; 49 50 memory@80000000 { 51 device_type = "memory"; 52 reg = <0 0x80000000 0 0x40000000>; 53 }; 54 55 hdlcd@2b000000 { 56 compatible = "arm,hdlcd"; 57 reg = <0 0x2b000000 0 0x1000>; 58 interrupts = <0 85 4>; 59 clocks = <&hdlcd_clk>; 60 clock-names = "pxlclk"; 61 }; 62 63 memory-controller@2b0a0000 { 64 compatible = "arm,pl341", "arm,primecell"; 65 reg = <0 0x2b0a0000 0 0x1000>; 66 clocks = <&sys_pll>; 67 clock-names = "apb_pclk"; 68 }; 69 70 wdt@2b060000 { 71 compatible = "arm,sp805", "arm,primecell"; 72 status = "disabled"; 73 reg = <0 0x2b060000 0 0x1000>; 74 interrupts = <0 98 4>; 75 clocks = <&sys_pll>; 76 clock-names = "apb_pclk"; 77 }; 78 79 gic: interrupt-controller@2c001000 { 80 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 81 #interrupt-cells = <3>; 82 #address-cells = <0>; 83 interrupt-controller; 84 reg = <0 0x2c001000 0 0x1000>, 85 <0 0x2c002000 0 0x2000>, 86 <0 0x2c004000 0 0x2000>, 87 <0 0x2c006000 0 0x2000>; 88 interrupts = <1 9 0xf04>; 89 }; 90 91 memory-controller@7ffd0000 { 92 compatible = "arm,pl354", "arm,primecell"; 93 reg = <0 0x7ffd0000 0 0x1000>; 94 interrupts = <0 86 4>, 95 <0 87 4>; 96 clocks = <&sys_pll>; 97 clock-names = "apb_pclk"; 98 }; 99 100 dma@7ffb0000 { 101 compatible = "arm,pl330", "arm,primecell"; 102 reg = <0 0x7ffb0000 0 0x1000>; 103 interrupts = <0 92 4>, 104 <0 88 4>, 105 <0 89 4>, 106 <0 90 4>, 107 <0 91 4>; 108 clocks = <&sys_pll>; 109 clock-names = "apb_pclk"; 110 }; 111 112 timer { 113 compatible = "arm,armv7-timer"; 114 interrupts = <1 13 0xf08>, 115 <1 14 0xf08>, 116 <1 11 0xf08>, 117 <1 10 0xf08>; 118 }; 119 120 pmu { 121 compatible = "arm,cortex-a15-pmu"; 122 interrupts = <0 68 4>, 123 <0 69 4>; 124 }; 125 126 dcc { 127 compatible = "arm,vexpress,config-bus"; 128 arm,vexpress,config-bridge = <&v2m_sysreg>; 129 130 oscclk0 { 131 /* CPU PLL reference clock */ 132 compatible = "arm,vexpress-osc"; 133 arm,vexpress-sysreg,func = <1 0>; 134 freq-range = <50000000 60000000>; 135 #clock-cells = <0>; 136 clock-output-names = "oscclk0"; 137 }; 138 139 oscclk4 { 140 /* Multiplexed AXI master clock */ 141 compatible = "arm,vexpress-osc"; 142 arm,vexpress-sysreg,func = <1 4>; 143 freq-range = <20000000 40000000>; 144 #clock-cells = <0>; 145 clock-output-names = "oscclk4"; 146 }; 147 148 hdlcd_clk: oscclk5 { 149 /* HDLCD PLL reference clock */ 150 compatible = "arm,vexpress-osc"; 151 arm,vexpress-sysreg,func = <1 5>; 152 freq-range = <23750000 165000000>; 153 #clock-cells = <0>; 154 clock-output-names = "oscclk5"; 155 }; 156 157 smbclk: oscclk6 { 158 /* SMB clock */ 159 compatible = "arm,vexpress-osc"; 160 arm,vexpress-sysreg,func = <1 6>; 161 freq-range = <20000000 50000000>; 162 #clock-cells = <0>; 163 clock-output-names = "oscclk6"; 164 }; 165 166 sys_pll: oscclk7 { 167 /* SYS PLL reference clock */ 168 compatible = "arm,vexpress-osc"; 169 arm,vexpress-sysreg,func = <1 7>; 170 freq-range = <20000000 60000000>; 171 #clock-cells = <0>; 172 clock-output-names = "oscclk7"; 173 }; 174 175 oscclk8 { 176 /* DDR2 PLL reference clock */ 177 compatible = "arm,vexpress-osc"; 178 arm,vexpress-sysreg,func = <1 8>; 179 freq-range = <40000000 40000000>; 180 #clock-cells = <0>; 181 clock-output-names = "oscclk8"; 182 }; 183 184 volt-cores { 185 /* CPU core voltage */ 186 compatible = "arm,vexpress-volt"; 187 arm,vexpress-sysreg,func = <2 0>; 188 regulator-name = "Cores"; 189 regulator-min-microvolt = <800000>; 190 regulator-max-microvolt = <1050000>; 191 regulator-always-on; 192 label = "Cores"; 193 }; 194 195 amp-cores { 196 /* Total current for the two cores */ 197 compatible = "arm,vexpress-amp"; 198 arm,vexpress-sysreg,func = <3 0>; 199 label = "Cores"; 200 }; 201 202 temp-dcc { 203 /* DCC internal temperature */ 204 compatible = "arm,vexpress-temp"; 205 arm,vexpress-sysreg,func = <4 0>; 206 label = "DCC"; 207 }; 208 209 power-cores { 210 /* Total power */ 211 compatible = "arm,vexpress-power"; 212 arm,vexpress-sysreg,func = <12 0>; 213 label = "Cores"; 214 }; 215 216 energy { 217 /* Total energy */ 218 compatible = "arm,vexpress-energy"; 219 arm,vexpress-sysreg,func = <13 0>; 220 label = "Cores"; 221 }; 222 }; 223 224 smb@8000000 { 225 compatible = "simple-bus"; 226 227 #address-cells = <2>; 228 #size-cells = <1>; 229 ranges = <0 0 0 0x08000000 0x04000000>, 230 <1 0 0 0x14000000 0x04000000>, 231 <2 0 0 0x18000000 0x04000000>, 232 <3 0 0 0x1c000000 0x04000000>, 233 <4 0 0 0x0c000000 0x04000000>, 234 <5 0 0 0x10000000 0x04000000>; 235 236 #interrupt-cells = <1>; 237 interrupt-map-mask = <0 0 63>; 238 interrupt-map = <0 0 0 &gic 0 0 4>, 239 <0 0 1 &gic 0 1 4>, 240 <0 0 2 &gic 0 2 4>, 241 <0 0 3 &gic 0 3 4>, 242 <0 0 4 &gic 0 4 4>, 243 <0 0 5 &gic 0 5 4>, 244 <0 0 6 &gic 0 6 4>, 245 <0 0 7 &gic 0 7 4>, 246 <0 0 8 &gic 0 8 4>, 247 <0 0 9 &gic 0 9 4>, 248 <0 0 10 &gic 0 10 4>, 249 <0 0 11 &gic 0 11 4>, 250 <0 0 12 &gic 0 12 4>, 251 <0 0 13 &gic 0 13 4>, 252 <0 0 14 &gic 0 14 4>, 253 <0 0 15 &gic 0 15 4>, 254 <0 0 16 &gic 0 16 4>, 255 <0 0 17 &gic 0 17 4>, 256 <0 0 18 &gic 0 18 4>, 257 <0 0 19 &gic 0 19 4>, 258 <0 0 20 &gic 0 20 4>, 259 <0 0 21 &gic 0 21 4>, 260 <0 0 22 &gic 0 22 4>, 261 <0 0 23 &gic 0 23 4>, 262 <0 0 24 &gic 0 24 4>, 263 <0 0 25 &gic 0 25 4>, 264 <0 0 26 &gic 0 26 4>, 265 <0 0 27 &gic 0 27 4>, 266 <0 0 28 &gic 0 28 4>, 267 <0 0 29 &gic 0 29 4>, 268 <0 0 30 &gic 0 30 4>, 269 <0 0 31 &gic 0 31 4>, 270 <0 0 32 &gic 0 32 4>, 271 <0 0 33 &gic 0 33 4>, 272 <0 0 34 &gic 0 34 4>, 273 <0 0 35 &gic 0 35 4>, 274 <0 0 36 &gic 0 36 4>, 275 <0 0 37 &gic 0 37 4>, 276 <0 0 38 &gic 0 38 4>, 277 <0 0 39 &gic 0 39 4>, 278 <0 0 40 &gic 0 40 4>, 279 <0 0 41 &gic 0 41 4>, 280 <0 0 42 &gic 0 42 4>; 281 282 /include/ "vexpress-v2m-rs1.dtsi" 283 }; 284 285 site2: hsb@40000000 { 286 compatible = "simple-bus"; 287 #address-cells = <1>; 288 #size-cells = <1>; 289 ranges = <0 0 0x40000000 0x3fef0000>; 290 #interrupt-cells = <1>; 291 interrupt-map-mask = <0 3>; 292 interrupt-map = <0 0 &gic 0 36 4>, 293 <0 1 &gic 0 37 4>, 294 <0 2 &gic 0 38 4>, 295 <0 3 &gic 0 39 4>; 296 }; 297}; 298