1/* 2 * Copyright (C) 2011 - 2014 Xilinx 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 compatible = "xlnx,zynq-7000"; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a9"; 25 device_type = "cpu"; 26 reg = <0>; 27 clocks = <&clkc 3>; 28 clock-latency = <1000>; 29 cpu0-supply = <®ulator_vccpint>; 30 operating-points = < 31 /* kHz uV */ 32 666667 1000000 33 333334 1000000 34 >; 35 }; 36 37 cpu1: cpu@1 { 38 compatible = "arm,cortex-a9"; 39 device_type = "cpu"; 40 reg = <1>; 41 clocks = <&clkc 3>; 42 }; 43 }; 44 45 fpga_full: fpga-full { 46 compatible = "fpga-region"; 47 fpga-mgr = <&devcfg>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 ranges; 51 }; 52 53 pmu@f8891000 { 54 compatible = "arm,cortex-a9-pmu"; 55 interrupts = <0 5 4>, <0 6 4>; 56 interrupt-parent = <&intc>; 57 reg = <0xf8891000 0x1000>, 58 <0xf8893000 0x1000>; 59 }; 60 61 regulator_vccpint: fixedregulator { 62 compatible = "regulator-fixed"; 63 regulator-name = "VCCPINT"; 64 regulator-min-microvolt = <1000000>; 65 regulator-max-microvolt = <1000000>; 66 regulator-boot-on; 67 regulator-always-on; 68 }; 69 70 amba: amba { 71 compatible = "simple-bus"; 72 #address-cells = <1>; 73 #size-cells = <1>; 74 interrupt-parent = <&intc>; 75 ranges; 76 77 adc: adc@f8007100 { 78 compatible = "xlnx,zynq-xadc-1.00.a"; 79 reg = <0xf8007100 0x20>; 80 interrupts = <0 7 4>; 81 interrupt-parent = <&intc>; 82 clocks = <&clkc 12>; 83 }; 84 85 can0: can@e0008000 { 86 compatible = "xlnx,zynq-can-1.0"; 87 status = "disabled"; 88 clocks = <&clkc 19>, <&clkc 36>; 89 clock-names = "can_clk", "pclk"; 90 reg = <0xe0008000 0x1000>; 91 interrupts = <0 28 4>; 92 interrupt-parent = <&intc>; 93 tx-fifo-depth = <0x40>; 94 rx-fifo-depth = <0x40>; 95 }; 96 97 can1: can@e0009000 { 98 compatible = "xlnx,zynq-can-1.0"; 99 status = "disabled"; 100 clocks = <&clkc 20>, <&clkc 37>; 101 clock-names = "can_clk", "pclk"; 102 reg = <0xe0009000 0x1000>; 103 interrupts = <0 51 4>; 104 interrupt-parent = <&intc>; 105 tx-fifo-depth = <0x40>; 106 rx-fifo-depth = <0x40>; 107 }; 108 109 gpio0: gpio@e000a000 { 110 compatible = "xlnx,zynq-gpio-1.0"; 111 #gpio-cells = <2>; 112 clocks = <&clkc 42>; 113 gpio-controller; 114 interrupt-controller; 115 #interrupt-cells = <2>; 116 interrupt-parent = <&intc>; 117 interrupts = <0 20 4>; 118 reg = <0xe000a000 0x1000>; 119 }; 120 121 i2c0: i2c@e0004000 { 122 compatible = "cdns,i2c-r1p10"; 123 status = "disabled"; 124 clocks = <&clkc 38>; 125 interrupt-parent = <&intc>; 126 interrupts = <0 25 4>; 127 reg = <0xe0004000 0x1000>; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 }; 131 132 i2c1: i2c@e0005000 { 133 compatible = "cdns,i2c-r1p10"; 134 status = "disabled"; 135 clocks = <&clkc 39>; 136 interrupt-parent = <&intc>; 137 interrupts = <0 48 4>; 138 reg = <0xe0005000 0x1000>; 139 #address-cells = <1>; 140 #size-cells = <0>; 141 }; 142 143 intc: interrupt-controller@f8f01000 { 144 compatible = "arm,cortex-a9-gic"; 145 #interrupt-cells = <3>; 146 interrupt-controller; 147 reg = <0xF8F01000 0x1000>, 148 <0xF8F00100 0x100>; 149 }; 150 151 L2: cache-controller@f8f02000 { 152 compatible = "arm,pl310-cache"; 153 reg = <0xF8F02000 0x1000>; 154 interrupts = <0 2 4>; 155 arm,data-latency = <3 2 2>; 156 arm,tag-latency = <2 2 2>; 157 cache-unified; 158 cache-level = <2>; 159 }; 160 161 mc: memory-controller@f8006000 { 162 compatible = "xlnx,zynq-ddrc-a05"; 163 reg = <0xf8006000 0x1000>; 164 }; 165 166 uart0: serial@e0000000 { 167 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 168 status = "disabled"; 169 clocks = <&clkc 23>, <&clkc 40>; 170 clock-names = "uart_clk", "pclk"; 171 reg = <0xE0000000 0x1000>; 172 interrupts = <0 27 4>; 173 }; 174 175 uart1: serial@e0001000 { 176 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 177 status = "disabled"; 178 clocks = <&clkc 24>, <&clkc 41>; 179 clock-names = "uart_clk", "pclk"; 180 reg = <0xE0001000 0x1000>; 181 interrupts = <0 50 4>; 182 }; 183 184 spi0: spi@e0006000 { 185 compatible = "xlnx,zynq-spi-r1p6"; 186 reg = <0xe0006000 0x1000>; 187 status = "disabled"; 188 interrupt-parent = <&intc>; 189 interrupts = <0 26 4>; 190 clocks = <&clkc 25>, <&clkc 34>; 191 clock-names = "ref_clk", "pclk"; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 }; 195 196 spi1: spi@e0007000 { 197 compatible = "xlnx,zynq-spi-r1p6"; 198 reg = <0xe0007000 0x1000>; 199 status = "disabled"; 200 interrupt-parent = <&intc>; 201 interrupts = <0 49 4>; 202 clocks = <&clkc 26>, <&clkc 35>; 203 clock-names = "ref_clk", "pclk"; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 }; 207 208 gem0: ethernet@e000b000 { 209 compatible = "cdns,zynq-gem", "cdns,gem"; 210 reg = <0xe000b000 0x1000>; 211 status = "disabled"; 212 interrupts = <0 22 4>; 213 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 214 clock-names = "pclk", "hclk", "tx_clk"; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 }; 218 219 gem1: ethernet@e000c000 { 220 compatible = "cdns,zynq-gem", "cdns,gem"; 221 reg = <0xe000c000 0x1000>; 222 status = "disabled"; 223 interrupts = <0 45 4>; 224 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 225 clock-names = "pclk", "hclk", "tx_clk"; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 }; 229 230 sdhci0: sdhci@e0100000 { 231 compatible = "arasan,sdhci-8.9a"; 232 status = "disabled"; 233 clock-names = "clk_xin", "clk_ahb"; 234 clocks = <&clkc 21>, <&clkc 32>; 235 interrupt-parent = <&intc>; 236 interrupts = <0 24 4>; 237 reg = <0xe0100000 0x1000>; 238 }; 239 240 sdhci1: sdhci@e0101000 { 241 compatible = "arasan,sdhci-8.9a"; 242 status = "disabled"; 243 clock-names = "clk_xin", "clk_ahb"; 244 clocks = <&clkc 22>, <&clkc 33>; 245 interrupt-parent = <&intc>; 246 interrupts = <0 47 4>; 247 reg = <0xe0101000 0x1000>; 248 }; 249 250 slcr: slcr@f8000000 { 251 #address-cells = <1>; 252 #size-cells = <1>; 253 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 254 reg = <0xF8000000 0x1000>; 255 ranges; 256 clkc: clkc@100 { 257 #clock-cells = <1>; 258 compatible = "xlnx,ps7-clkc"; 259 fclk-enable = <0>; 260 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 261 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 262 "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 263 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 264 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 265 "dma", "usb0_aper", "usb1_aper", "gem0_aper", 266 "gem1_aper", "sdio0_aper", "sdio1_aper", 267 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 268 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 269 "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 270 "dbg_trc", "dbg_apb"; 271 reg = <0x100 0x100>; 272 }; 273 274 rstc: rstc@200 { 275 compatible = "xlnx,zynq-reset"; 276 reg = <0x200 0x48>; 277 #reset-cells = <1>; 278 syscon = <&slcr>; 279 }; 280 281 pinctrl0: pinctrl@700 { 282 compatible = "xlnx,pinctrl-zynq"; 283 reg = <0x700 0x200>; 284 syscon = <&slcr>; 285 }; 286 }; 287 288 dmac_s: dmac@f8003000 { 289 compatible = "arm,pl330", "arm,primecell"; 290 reg = <0xf8003000 0x1000>; 291 interrupt-parent = <&intc>; 292 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", 293 "dma4", "dma5", "dma6", "dma7"; 294 interrupts = <0 13 4>, 295 <0 14 4>, <0 15 4>, 296 <0 16 4>, <0 17 4>, 297 <0 40 4>, <0 41 4>, 298 <0 42 4>, <0 43 4>; 299 #dma-cells = <1>; 300 #dma-channels = <8>; 301 #dma-requests = <4>; 302 clocks = <&clkc 27>; 303 clock-names = "apb_pclk"; 304 }; 305 306 devcfg: devcfg@f8007000 { 307 compatible = "xlnx,zynq-devcfg-1.0"; 308 reg = <0xf8007000 0x100>; 309 interrupt-parent = <&intc>; 310 interrupts = <0 8 4>; 311 clocks = <&clkc 12>; 312 clock-names = "ref_clk"; 313 syscon = <&slcr>; 314 }; 315 316 global_timer: timer@f8f00200 { 317 compatible = "arm,cortex-a9-global-timer"; 318 reg = <0xf8f00200 0x20>; 319 interrupts = <1 11 0x301>; 320 interrupt-parent = <&intc>; 321 clocks = <&clkc 4>; 322 }; 323 324 ttc0: timer@f8001000 { 325 interrupt-parent = <&intc>; 326 interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 327 compatible = "cdns,ttc"; 328 clocks = <&clkc 6>; 329 reg = <0xF8001000 0x1000>; 330 }; 331 332 ttc1: timer@f8002000 { 333 interrupt-parent = <&intc>; 334 interrupts = <0 37 4>, <0 38 4>, <0 39 4>; 335 compatible = "cdns,ttc"; 336 clocks = <&clkc 6>; 337 reg = <0xF8002000 0x1000>; 338 }; 339 340 scutimer: timer@f8f00600 { 341 interrupt-parent = <&intc>; 342 interrupts = <1 13 0x301>; 343 compatible = "arm,cortex-a9-twd-timer"; 344 reg = <0xf8f00600 0x20>; 345 clocks = <&clkc 4>; 346 }; 347 348 usb0: usb@e0002000 { 349 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 350 status = "disabled"; 351 clocks = <&clkc 28>; 352 interrupt-parent = <&intc>; 353 interrupts = <0 21 4>; 354 reg = <0xe0002000 0x1000>; 355 phy_type = "ulpi"; 356 }; 357 358 usb1: usb@e0003000 { 359 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 360 status = "disabled"; 361 clocks = <&clkc 29>; 362 interrupt-parent = <&intc>; 363 interrupts = <0 44 4>; 364 reg = <0xe0003000 0x1000>; 365 phy_type = "ulpi"; 366 }; 367 368 watchdog0: watchdog@f8005000 { 369 clocks = <&clkc 45>; 370 compatible = "cdns,wdt-r1p2"; 371 interrupt-parent = <&intc>; 372 interrupts = <0 9 1>; 373 reg = <0xf8005000 0x1000>; 374 timeout-sec = <10>; 375 }; 376 }; 377}; 378