1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Hisilicon Hi6220 SoC 4 * 5 * Copyright (C) 2015, Hisilicon Ltd. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/reset/hisi,hi6220-resets.h> 10#include <dt-bindings/clock/hi6220-clock.h> 11#include <dt-bindings/pinctrl/hisi.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "hisilicon,hi6220"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 psci { 21 compatible = "arm,psci-0.2"; 22 method = "smc"; 23 }; 24 25 cpus { 26 #address-cells = <2>; 27 #size-cells = <0>; 28 29 cpu-map { 30 cluster0 { 31 core0 { 32 cpu = <&cpu0>; 33 }; 34 core1 { 35 cpu = <&cpu1>; 36 }; 37 core2 { 38 cpu = <&cpu2>; 39 }; 40 core3 { 41 cpu = <&cpu3>; 42 }; 43 }; 44 cluster1 { 45 core0 { 46 cpu = <&cpu4>; 47 }; 48 core1 { 49 cpu = <&cpu5>; 50 }; 51 core2 { 52 cpu = <&cpu6>; 53 }; 54 core3 { 55 cpu = <&cpu7>; 56 }; 57 }; 58 }; 59 60 idle-states { 61 entry-method = "psci"; 62 63 CPU_SLEEP: cpu-sleep { 64 compatible = "arm,idle-state"; 65 local-timer-stop; 66 arm,psci-suspend-param = <0x0010000>; 67 entry-latency-us = <700>; 68 exit-latency-us = <250>; 69 min-residency-us = <1000>; 70 }; 71 72 CLUSTER_SLEEP: cluster-sleep { 73 compatible = "arm,idle-state"; 74 local-timer-stop; 75 arm,psci-suspend-param = <0x1010000>; 76 entry-latency-us = <1000>; 77 exit-latency-us = <700>; 78 min-residency-us = <2700>; 79 wakeup-latency-us = <1500>; 80 }; 81 }; 82 83 cpu0: cpu@0 { 84 compatible = "arm,cortex-a53", "arm,armv8"; 85 device_type = "cpu"; 86 reg = <0x0 0x0>; 87 enable-method = "psci"; 88 next-level-cache = <&CLUSTER0_L2>; 89 clocks = <&stub_clock 0>; 90 operating-points-v2 = <&cpu_opp_table>; 91 cooling-min-level = <4>; 92 cooling-max-level = <0>; 93 #cooling-cells = <2>; /* min followed by max */ 94 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 95 sched-energy-costs = <&CPU_COST &CLUSTER_COST &SYSTEM_COST>; 96 dynamic-power-coefficient = <311>; 97 capacity-dmips-mhz = <1024>; 98 }; 99 100 cpu1: cpu@1 { 101 compatible = "arm,cortex-a53", "arm,armv8"; 102 device_type = "cpu"; 103 reg = <0x0 0x1>; 104 enable-method = "psci"; 105 next-level-cache = <&CLUSTER0_L2>; 106 operating-points-v2 = <&cpu_opp_table>; 107 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 108 sched-energy-costs = <&CPU_COST &CLUSTER_COST &SYSTEM_COST>; 109 capacity-dmips-mhz = <1024>; 110 }; 111 112 cpu2: cpu@2 { 113 compatible = "arm,cortex-a53", "arm,armv8"; 114 device_type = "cpu"; 115 reg = <0x0 0x2>; 116 enable-method = "psci"; 117 next-level-cache = <&CLUSTER0_L2>; 118 operating-points-v2 = <&cpu_opp_table>; 119 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 120 capacity-dmips-mhz = <1024>; 121 }; 122 123 cpu3: cpu@3 { 124 compatible = "arm,cortex-a53", "arm,armv8"; 125 device_type = "cpu"; 126 reg = <0x0 0x3>; 127 enable-method = "psci"; 128 next-level-cache = <&CLUSTER0_L2>; 129 operating-points-v2 = <&cpu_opp_table>; 130 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 131 sched-energy-costs = <&CPU_COST &CLUSTER_COST &SYSTEM_COST>; 132 capacity-dmips-mhz = <1024>; 133 }; 134 135 cpu4: cpu@100 { 136 compatible = "arm,cortex-a53", "arm,armv8"; 137 device_type = "cpu"; 138 reg = <0x0 0x100>; 139 enable-method = "psci"; 140 next-level-cache = <&CLUSTER1_L2>; 141 operating-points-v2 = <&cpu_opp_table>; 142 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 143 capacity-dmips-mhz = <1024>; 144 }; 145 146 cpu5: cpu@101 { 147 compatible = "arm,cortex-a53", "arm,armv8"; 148 device_type = "cpu"; 149 reg = <0x0 0x101>; 150 enable-method = "psci"; 151 next-level-cache = <&CLUSTER1_L2>; 152 operating-points-v2 = <&cpu_opp_table>; 153 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 154 sched-energy-costs = <&CPU_COST &CLUSTER_COST &SYSTEM_COST>; 155 capacity-dmips-mhz = <1024>; 156 }; 157 158 cpu6: cpu@102 { 159 compatible = "arm,cortex-a53", "arm,armv8"; 160 device_type = "cpu"; 161 reg = <0x0 0x102>; 162 enable-method = "psci"; 163 next-level-cache = <&CLUSTER1_L2>; 164 operating-points-v2 = <&cpu_opp_table>; 165 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 166 sched-energy-costs = <&CPU_COST &CLUSTER_COST &SYSTEM_COST>; 167 capacity-dmips-mhz = <1024>; 168 }; 169 170 cpu7: cpu@103 { 171 compatible = "arm,cortex-a53", "arm,armv8"; 172 device_type = "cpu"; 173 reg = <0x0 0x103>; 174 enable-method = "psci"; 175 next-level-cache = <&CLUSTER1_L2>; 176 operating-points-v2 = <&cpu_opp_table>; 177 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 178 sched-energy-costs = <&CPU_COST &CLUSTER_COST &SYSTEM_COST>; 179 capacity-dmips-mhz = <1024>; 180 }; 181 182 CLUSTER0_L2: l2-cache0 { 183 compatible = "cache"; 184 }; 185 186 CLUSTER1_L2: l2-cache1 { 187 compatible = "cache"; 188 }; 189 190 energy-costs { 191 SYSTEM_COST: system-cost0 { 192 busy-cost-data = < 193 1024 0 194 >; 195 idle-cost-data = < 196 0 197 0 198 0 199 0 200 >; 201 }; 202 CLUSTER_COST: cluster-cost0 { 203 busy-cost-data = < 204 178 16 205 369 29 206 622 47 207 819 75 208 1024 112 209 >; 210 idle-cost-data = < 211 107 212 107 213 47 214 0 215 >; 216 }; 217 CPU_COST: core-cost0 { 218 busy-cost-data = < 219 178 69 220 369 125 221 622 224 222 819 367 223 1024 670 224 >; 225 idle-cost-data = < 226 15 227 15 228 0 229 0 230 >; 231 }; 232 }; 233 }; 234 235 cpu_opp_table: cpu_opp_table { 236 compatible = "operating-points-v2"; 237 opp-shared; 238 239 opp00 { 240 opp-hz = /bits/ 64 <208000000>; 241 opp-microvolt = <1040000>; 242 clock-latency-ns = <500000>; 243 }; 244 opp01 { 245 opp-hz = /bits/ 64 <432000000>; 246 opp-microvolt = <1040000>; 247 clock-latency-ns = <500000>; 248 }; 249 opp02 { 250 opp-hz = /bits/ 64 <729000000>; 251 opp-microvolt = <1090000>; 252 clock-latency-ns = <500000>; 253 }; 254 opp03 { 255 opp-hz = /bits/ 64 <960000000>; 256 opp-microvolt = <1180000>; 257 clock-latency-ns = <500000>; 258 }; 259 opp04 { 260 opp-hz = /bits/ 64 <1200000000>; 261 opp-microvolt = <1330000>; 262 clock-latency-ns = <500000>; 263 }; 264 }; 265 266 gic: interrupt-controller@f6801000 { 267 compatible = "arm,gic-400"; 268 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ 269 <0x0 0xf6802000 0 0x2000>, /* GICC */ 270 <0x0 0xf6804000 0 0x2000>, /* GICH */ 271 <0x0 0xf6806000 0 0x2000>; /* GICV */ 272 #address-cells = <0>; 273 #interrupt-cells = <3>; 274 interrupt-controller; 275 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 276 }; 277 278 timer { 279 compatible = "arm,armv8-timer"; 280 interrupt-parent = <&gic>; 281 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 282 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 283 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 284 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 285 }; 286 287 soc { 288 compatible = "simple-bus"; 289 #address-cells = <2>; 290 #size-cells = <2>; 291 ranges; 292 293 sram: sram@fff80000 { 294 compatible = "hisilicon,hi6220-sramctrl", "syscon"; 295 reg = <0x0 0xfff80000 0x0 0x12000>; 296 }; 297 298 ao_ctrl: ao_ctrl@f7800000 { 299 compatible = "hisilicon,hi6220-aoctrl", "syscon"; 300 reg = <0x0 0xf7800000 0x0 0x2000>; 301 #clock-cells = <1>; 302 }; 303 304 sys_ctrl: sys_ctrl@f7030000 { 305 compatible = "hisilicon,hi6220-sysctrl", "syscon"; 306 reg = <0x0 0xf7030000 0x0 0x2000>; 307 #clock-cells = <1>; 308 #reset-cells = <1>; 309 }; 310 311 media_ctrl: media_ctrl@f4410000 { 312 compatible = "hisilicon,hi6220-mediactrl", "syscon"; 313 reg = <0x0 0xf4410000 0x0 0x1000>; 314 #clock-cells = <1>; 315 #reset-cells = <1>; 316 }; 317 318 pm_ctrl: pm_ctrl@f7032000 { 319 compatible = "hisilicon,hi6220-pmctrl", "syscon"; 320 reg = <0x0 0xf7032000 0x0 0x1000>; 321 #clock-cells = <1>; 322 }; 323 324 acpu_sctrl: acpu_sctrl@f6504000 { 325 compatible = "hisilicon,hi6220-acpu-sctrl", "syscon"; 326 reg = <0x0 0xf6504000 0x0 0x1000>; 327 #clock-cells = <1>; 328 }; 329 330 medianoc_ade: medianoc_ade@f4520000 { 331 compatible = "syscon"; 332 reg = <0x0 0xf4520000 0x0 0x4000>; 333 }; 334 335 stub_clock: stub_clock { 336 compatible = "hisilicon,hi6220-stub-clk"; 337 hisilicon,hi6220-clk-sram = <&sram>; 338 #clock-cells = <1>; 339 mbox-names = "mbox-tx"; 340 mboxes = <&mailbox 1 0 11>; 341 }; 342 343 uart0: uart@f8015000 { /* console */ 344 compatible = "arm,pl011", "arm,primecell"; 345 reg = <0x0 0xf8015000 0x0 0x1000>; 346 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&ao_ctrl HI6220_UART0_PCLK>, 348 <&ao_ctrl HI6220_UART0_PCLK>; 349 clock-names = "uartclk", "apb_pclk"; 350 }; 351 352 uart1: uart@f7111000 { 353 compatible = "arm,pl011", "arm,primecell"; 354 reg = <0x0 0xf7111000 0x0 0x1000>; 355 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&sys_ctrl HI6220_UART1_PCLK>, 357 <&sys_ctrl HI6220_UART1_PCLK>; 358 clock-names = "uartclk", "apb_pclk"; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; 361 status = "disabled"; 362 }; 363 364 uart2: uart@f7112000 { 365 compatible = "arm,pl011", "arm,primecell"; 366 reg = <0x0 0xf7112000 0x0 0x1000>; 367 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&sys_ctrl HI6220_UART2_PCLK>, 369 <&sys_ctrl HI6220_UART2_PCLK>; 370 clock-names = "uartclk", "apb_pclk"; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 373 status = "disabled"; 374 }; 375 376 uart3: uart@f7113000 { 377 compatible = "arm,pl011", "arm,primecell"; 378 reg = <0x0 0xf7113000 0x0 0x1000>; 379 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&sys_ctrl HI6220_UART3_PCLK>, 381 <&sys_ctrl HI6220_UART3_PCLK>; 382 clock-names = "uartclk", "apb_pclk"; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 385 status = "disabled"; 386 }; 387 388 uart4: uart@f7114000 { 389 compatible = "arm,pl011", "arm,primecell"; 390 reg = <0x0 0xf7114000 0x0 0x1000>; 391 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&sys_ctrl HI6220_UART4_PCLK>, 393 <&sys_ctrl HI6220_UART4_PCLK>; 394 clock-names = "uartclk", "apb_pclk"; 395 pinctrl-names = "default"; 396 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 397 status = "disabled"; 398 }; 399 400 dma0: dma@f7370000 { 401 compatible = "hisilicon,k3-dma-1.0"; 402 reg = <0x0 0xf7370000 0x0 0x1000>; 403 #dma-cells = <1>; 404 dma-channels = <15>; 405 dma-requests = <32>; 406 interrupts = <0 84 4>; 407 clocks = <&sys_ctrl HI6220_EDMAC_ACLK>; 408 dma-no-cci; 409 dma-type = "hi6220_dma"; 410 status = "ok"; 411 }; 412 413 dual_timer0: timer@f8008000 { 414 compatible = "arm,sp804", "arm,primecell"; 415 reg = <0x0 0xf8008000 0x0 0x1000>; 416 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>, 419 <&ao_ctrl HI6220_TIMER0_PCLK>, 420 <&ao_ctrl HI6220_TIMER0_PCLK>; 421 clock-names = "timer1", "timer2", "apb_pclk"; 422 }; 423 424 rtc0: rtc@f8003000 { 425 compatible = "arm,pl031", "arm,primecell"; 426 reg = <0x0 0xf8003000 0x0 0x1000>; 427 interrupts = <0 12 4>; 428 clocks = <&ao_ctrl HI6220_RTC0_PCLK>; 429 clock-names = "apb_pclk"; 430 }; 431 432 rtc1: rtc@f8004000 { 433 compatible = "arm,pl031", "arm,primecell"; 434 reg = <0x0 0xf8004000 0x0 0x1000>; 435 interrupts = <0 8 4>; 436 clocks = <&ao_ctrl HI6220_RTC1_PCLK>; 437 clock-names = "apb_pclk"; 438 }; 439 440 pmx0: pinmux@f7010000 { 441 compatible = "pinctrl-single"; 442 reg = <0x0 0xf7010000 0x0 0x27c>; 443 #address-cells = <1>; 444 #size-cells = <1>; 445 #pinctrl-cells = <1>; 446 #gpio-range-cells = <3>; 447 pinctrl-single,register-width = <32>; 448 pinctrl-single,function-mask = <7>; 449 pinctrl-single,gpio-range = < 450 &range 80 8 MUX_M0 /* gpio 3: [0..7] */ 451 &range 88 8 MUX_M0 /* gpio 4: [0..7] */ 452 &range 96 8 MUX_M0 /* gpio 5: [0..7] */ 453 &range 104 8 MUX_M0 /* gpio 6: [0..7] */ 454 &range 112 8 MUX_M0 /* gpio 7: [0..7] */ 455 &range 120 2 MUX_M0 /* gpio 8: [0..1] */ 456 &range 2 6 MUX_M1 /* gpio 8: [2..7] */ 457 &range 8 8 MUX_M1 /* gpio 9: [0..7] */ 458 &range 0 1 MUX_M1 /* gpio 10: [0] */ 459 &range 16 7 MUX_M1 /* gpio 10: [1..7] */ 460 &range 23 3 MUX_M1 /* gpio 11: [0..2] */ 461 &range 28 5 MUX_M1 /* gpio 11: [3..7] */ 462 &range 33 3 MUX_M1 /* gpio 12: [0..2] */ 463 &range 43 5 MUX_M1 /* gpio 12: [3..7] */ 464 &range 48 8 MUX_M1 /* gpio 13: [0..7] */ 465 &range 56 8 MUX_M1 /* gpio 14: [0..7] */ 466 &range 74 6 MUX_M1 /* gpio 15: [0..5] */ 467 &range 122 1 MUX_M1 /* gpio 15: [6] */ 468 &range 126 1 MUX_M1 /* gpio 15: [7] */ 469 &range 127 8 MUX_M1 /* gpio 16: [0..7] */ 470 &range 135 8 MUX_M1 /* gpio 17: [0..7] */ 471 &range 143 8 MUX_M1 /* gpio 18: [0..7] */ 472 &range 151 8 MUX_M1 /* gpio 19: [0..7] */ 473 >; 474 range: gpio-range { 475 #pinctrl-single,gpio-range-cells = <3>; 476 }; 477 }; 478 479 pmx1: pinmux@f7010800 { 480 compatible = "pinconf-single"; 481 reg = <0x0 0xf7010800 0x0 0x28c>; 482 #address-cells = <1>; 483 #size-cells = <1>; 484 #pinctrl-cells = <1>; 485 pinctrl-single,register-width = <32>; 486 }; 487 488 pmx2: pinmux@f8001800 { 489 compatible = "pinconf-single"; 490 reg = <0x0 0xf8001800 0x0 0x78>; 491 #address-cells = <1>; 492 #size-cells = <1>; 493 #pinctrl-cells = <1>; 494 pinctrl-single,register-width = <32>; 495 }; 496 497 gpio0: gpio@f8011000 { 498 compatible = "arm,pl061", "arm,primecell"; 499 reg = <0x0 0xf8011000 0x0 0x1000>; 500 interrupts = <0 52 0x4>; 501 gpio-controller; 502 #gpio-cells = <2>; 503 interrupt-controller; 504 #interrupt-cells = <2>; 505 clocks = <&ao_ctrl 2>; 506 clock-names = "apb_pclk"; 507 }; 508 509 gpio1: gpio@f8012000 { 510 compatible = "arm,pl061", "arm,primecell"; 511 reg = <0x0 0xf8012000 0x0 0x1000>; 512 interrupts = <0 53 0x4>; 513 gpio-controller; 514 #gpio-cells = <2>; 515 interrupt-controller; 516 #interrupt-cells = <2>; 517 clocks = <&ao_ctrl 2>; 518 clock-names = "apb_pclk"; 519 }; 520 521 gpio2: gpio@f8013000 { 522 compatible = "arm,pl061", "arm,primecell"; 523 reg = <0x0 0xf8013000 0x0 0x1000>; 524 interrupts = <0 54 0x4>; 525 gpio-controller; 526 #gpio-cells = <2>; 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 clocks = <&ao_ctrl 2>; 530 clock-names = "apb_pclk"; 531 }; 532 533 gpio3: gpio@f8014000 { 534 compatible = "arm,pl061", "arm,primecell"; 535 reg = <0x0 0xf8014000 0x0 0x1000>; 536 interrupts = <0 55 0x4>; 537 gpio-controller; 538 #gpio-cells = <2>; 539 gpio-ranges = <&pmx0 0 80 8>; 540 interrupt-controller; 541 #interrupt-cells = <2>; 542 clocks = <&ao_ctrl 2>; 543 clock-names = "apb_pclk"; 544 }; 545 546 gpio4: gpio@f7020000 { 547 compatible = "arm,pl061", "arm,primecell"; 548 reg = <0x0 0xf7020000 0x0 0x1000>; 549 interrupts = <0 56 0x4>; 550 gpio-controller; 551 #gpio-cells = <2>; 552 gpio-ranges = <&pmx0 0 88 8>; 553 interrupt-controller; 554 #interrupt-cells = <2>; 555 clocks = <&ao_ctrl 2>; 556 clock-names = "apb_pclk"; 557 }; 558 559 gpio5: gpio@f7021000 { 560 compatible = "arm,pl061", "arm,primecell"; 561 reg = <0x0 0xf7021000 0x0 0x1000>; 562 interrupts = <0 57 0x4>; 563 gpio-controller; 564 #gpio-cells = <2>; 565 gpio-ranges = <&pmx0 0 96 8>; 566 interrupt-controller; 567 #interrupt-cells = <2>; 568 clocks = <&ao_ctrl 2>; 569 clock-names = "apb_pclk"; 570 }; 571 572 gpio6: gpio@f7022000 { 573 compatible = "arm,pl061", "arm,primecell"; 574 reg = <0x0 0xf7022000 0x0 0x1000>; 575 interrupts = <0 58 0x4>; 576 gpio-controller; 577 #gpio-cells = <2>; 578 gpio-ranges = <&pmx0 0 104 8>; 579 interrupt-controller; 580 #interrupt-cells = <2>; 581 clocks = <&ao_ctrl 2>; 582 clock-names = "apb_pclk"; 583 }; 584 585 gpio7: gpio@f7023000 { 586 compatible = "arm,pl061", "arm,primecell"; 587 reg = <0x0 0xf7023000 0x0 0x1000>; 588 interrupts = <0 59 0x4>; 589 gpio-controller; 590 #gpio-cells = <2>; 591 gpio-ranges = <&pmx0 0 112 8>; 592 interrupt-controller; 593 #interrupt-cells = <2>; 594 clocks = <&ao_ctrl 2>; 595 clock-names = "apb_pclk"; 596 }; 597 598 gpio8: gpio@f7024000 { 599 compatible = "arm,pl061", "arm,primecell"; 600 reg = <0x0 0xf7024000 0x0 0x1000>; 601 interrupts = <0 60 0x4>; 602 gpio-controller; 603 #gpio-cells = <2>; 604 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; 605 interrupt-controller; 606 #interrupt-cells = <2>; 607 clocks = <&ao_ctrl 2>; 608 clock-names = "apb_pclk"; 609 }; 610 611 gpio9: gpio@f7025000 { 612 compatible = "arm,pl061", "arm,primecell"; 613 reg = <0x0 0xf7025000 0x0 0x1000>; 614 interrupts = <0 61 0x4>; 615 gpio-controller; 616 #gpio-cells = <2>; 617 gpio-ranges = <&pmx0 0 8 8>; 618 interrupt-controller; 619 #interrupt-cells = <2>; 620 clocks = <&ao_ctrl 2>; 621 clock-names = "apb_pclk"; 622 }; 623 624 gpio10: gpio@f7026000 { 625 compatible = "arm,pl061", "arm,primecell"; 626 reg = <0x0 0xf7026000 0x0 0x1000>; 627 interrupts = <0 62 0x4>; 628 gpio-controller; 629 #gpio-cells = <2>; 630 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 clocks = <&ao_ctrl 2>; 634 clock-names = "apb_pclk"; 635 }; 636 637 gpio11: gpio@f7027000 { 638 compatible = "arm,pl061", "arm,primecell"; 639 reg = <0x0 0xf7027000 0x0 0x1000>; 640 interrupts = <0 63 0x4>; 641 gpio-controller; 642 #gpio-cells = <2>; 643 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 clocks = <&ao_ctrl 2>; 647 clock-names = "apb_pclk"; 648 }; 649 650 gpio12: gpio@f7028000 { 651 compatible = "arm,pl061", "arm,primecell"; 652 reg = <0x0 0xf7028000 0x0 0x1000>; 653 interrupts = <0 64 0x4>; 654 gpio-controller; 655 #gpio-cells = <2>; 656 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; 657 interrupt-controller; 658 #interrupt-cells = <2>; 659 clocks = <&ao_ctrl 2>; 660 clock-names = "apb_pclk"; 661 }; 662 663 gpio13: gpio@f7029000 { 664 compatible = "arm,pl061", "arm,primecell"; 665 reg = <0x0 0xf7029000 0x0 0x1000>; 666 interrupts = <0 65 0x4>; 667 gpio-controller; 668 #gpio-cells = <2>; 669 gpio-ranges = <&pmx0 0 48 8>; 670 interrupt-controller; 671 #interrupt-cells = <2>; 672 clocks = <&ao_ctrl 2>; 673 clock-names = "apb_pclk"; 674 }; 675 676 gpio14: gpio@f702a000 { 677 compatible = "arm,pl061", "arm,primecell"; 678 reg = <0x0 0xf702a000 0x0 0x1000>; 679 interrupts = <0 66 0x4>; 680 gpio-controller; 681 #gpio-cells = <2>; 682 gpio-ranges = <&pmx0 0 56 8>; 683 interrupt-controller; 684 #interrupt-cells = <2>; 685 clocks = <&ao_ctrl 2>; 686 clock-names = "apb_pclk"; 687 }; 688 689 gpio15: gpio@f702b000 { 690 compatible = "arm,pl061", "arm,primecell"; 691 reg = <0x0 0xf702b000 0x0 0x1000>; 692 interrupts = <0 67 0x4>; 693 gpio-controller; 694 #gpio-cells = <2>; 695 gpio-ranges = < 696 &pmx0 0 74 6 697 &pmx0 6 122 1 698 &pmx0 7 126 1 699 >; 700 interrupt-controller; 701 #interrupt-cells = <2>; 702 clocks = <&ao_ctrl 2>; 703 clock-names = "apb_pclk"; 704 }; 705 706 gpio16: gpio@f702c000 { 707 compatible = "arm,pl061", "arm,primecell"; 708 reg = <0x0 0xf702c000 0x0 0x1000>; 709 interrupts = <0 68 0x4>; 710 gpio-controller; 711 #gpio-cells = <2>; 712 gpio-ranges = <&pmx0 0 127 8>; 713 interrupt-controller; 714 #interrupt-cells = <2>; 715 clocks = <&ao_ctrl 2>; 716 clock-names = "apb_pclk"; 717 }; 718 719 gpio17: gpio@f702d000 { 720 compatible = "arm,pl061", "arm,primecell"; 721 reg = <0x0 0xf702d000 0x0 0x1000>; 722 interrupts = <0 69 0x4>; 723 gpio-controller; 724 #gpio-cells = <2>; 725 gpio-ranges = <&pmx0 0 135 8>; 726 interrupt-controller; 727 #interrupt-cells = <2>; 728 clocks = <&ao_ctrl 2>; 729 clock-names = "apb_pclk"; 730 }; 731 732 gpio18: gpio@f702e000 { 733 compatible = "arm,pl061", "arm,primecell"; 734 reg = <0x0 0xf702e000 0x0 0x1000>; 735 interrupts = <0 70 0x4>; 736 gpio-controller; 737 #gpio-cells = <2>; 738 gpio-ranges = <&pmx0 0 143 8>; 739 interrupt-controller; 740 #interrupt-cells = <2>; 741 clocks = <&ao_ctrl 2>; 742 clock-names = "apb_pclk"; 743 }; 744 745 gpio19: gpio@f702f000 { 746 compatible = "arm,pl061", "arm,primecell"; 747 reg = <0x0 0xf702f000 0x0 0x1000>; 748 interrupts = <0 71 0x4>; 749 gpio-controller; 750 #gpio-cells = <2>; 751 gpio-ranges = <&pmx0 0 151 8>; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 clocks = <&ao_ctrl 2>; 755 clock-names = "apb_pclk"; 756 }; 757 758 spi0: spi@f7106000 { 759 compatible = "arm,pl022", "arm,primecell"; 760 reg = <0x0 0xf7106000 0x0 0x1000>; 761 interrupts = <0 50 4>; 762 bus-id = <0>; 763 enable-dma = <0>; 764 clocks = <&sys_ctrl HI6220_SPI_CLK>; 765 clock-names = "apb_pclk"; 766 pinctrl-names = "default"; 767 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; 768 num-cs = <1>; 769 cs-gpios = <&gpio6 2 0>; 770 status = "disabled"; 771 }; 772 773 i2c0: i2c@f7100000 { 774 compatible = "snps,designware-i2c"; 775 reg = <0x0 0xf7100000 0x0 0x1000>; 776 interrupts = <0 44 4>; 777 clocks = <&sys_ctrl HI6220_I2C0_CLK>; 778 i2c-sda-hold-time-ns = <300>; 779 pinctrl-names = "default"; 780 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 781 status = "disabled"; 782 }; 783 784 i2c1: i2c@f7101000 { 785 compatible = "snps,designware-i2c"; 786 reg = <0x0 0xf7101000 0x0 0x1000>; 787 clocks = <&sys_ctrl HI6220_I2C1_CLK>; 788 interrupts = <0 45 4>; 789 i2c-sda-hold-time-ns = <300>; 790 pinctrl-names = "default"; 791 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 792 status = "disabled"; 793 }; 794 795 i2c2: i2c@f7102000 { 796 compatible = "snps,designware-i2c"; 797 reg = <0x0 0xf7102000 0x0 0x1000>; 798 clocks = <&sys_ctrl HI6220_I2C2_CLK>; 799 interrupts = <0 46 4>; 800 i2c-sda-hold-time-ns = <300>; 801 pinctrl-names = "default"; 802 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; 803 status = "disabled"; 804 }; 805 806 usb_phy: usbphy { 807 compatible = "hisilicon,hi6220-usb-phy"; 808 #phy-cells = <0>; 809 phy-supply = <®_5v_hub>; 810 hisilicon,peripheral-syscon = <&sys_ctrl>; 811 }; 812 813 usb: usb@f72c0000 { 814 compatible = "hisilicon,hi6220-usb"; 815 reg = <0x0 0xf72c0000 0x0 0x40000>; 816 phys = <&usb_phy>; 817 phy-names = "usb2-phy"; 818 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>; 819 clock-names = "otg"; 820 dr_mode = "otg"; 821 g-rx-fifo-size = <512>; 822 g-np-tx-fifo-size = <128>; 823 g-tx-fifo-size = <128 128 128 128 128 128 128 128 824 16 16 16 16 16 16 16>; 825 interrupts = <0 77 0x4>; 826 }; 827 828 mailbox: mailbox@f7510000 { 829 compatible = "hisilicon,hi6220-mbox"; 830 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ 831 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ 832 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 833 #mbox-cells = <3>; 834 }; 835 836 dwmmc_0: dwmmc0@f723d000 { 837 compatible = "hisilicon,hi6220-dw-mshc"; 838 reg = <0x0 0xf723d000 0x0 0x1000>; 839 interrupts = <0x0 0x48 0x4>; 840 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; 841 clock-names = "ciu", "biu"; 842 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>; 843 reset-names = "reset"; 844 pinctrl-names = "default"; 845 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func 846 &emmc_cfg_func &emmc_rst_cfg_func>; 847 }; 848 849 dwmmc_1: dwmmc1@f723e000 { 850 compatible = "hisilicon,hi6220-dw-mshc"; 851 hisilicon,peripheral-syscon = <&ao_ctrl>; 852 reg = <0x0 0xf723e000 0x0 0x1000>; 853 interrupts = <0x0 0x49 0x4>; 854 #address-cells = <0x1>; 855 #size-cells = <0x0>; 856 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; 857 clock-names = "ciu", "biu"; 858 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>; 859 reset-names = "reset"; 860 pinctrl-names = "default", "idle"; 861 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; 862 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; 863 }; 864 865 dwmmc_2: dwmmc2@f723f000 { 866 compatible = "hisilicon,hi6220-dw-mshc"; 867 reg = <0x0 0xf723f000 0x0 0x1000>; 868 interrupts = <0x0 0x4a 0x4>; 869 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; 870 clock-names = "ciu", "biu"; 871 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>; 872 reset-names = "reset"; 873 pinctrl-names = "default", "idle"; 874 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; 875 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; 876 }; 877 878 tsensor: tsensor@0,f7030700 { 879 compatible = "hisilicon,tsensor"; 880 reg = <0x0 0xf7030700 0x0 0x1000>; 881 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&sys_ctrl 22>; 883 clock-names = "thermal_clk"; 884 #thermal-sensor-cells = <1>; 885 }; 886 887 i2s0: i2s@f7118000{ 888 compatible = "hisilicon,hi6210-i2s"; 889 reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */ 890 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */ 891 clocks = <&sys_ctrl HI6220_DACODEC_PCLK>, 892 <&sys_ctrl HI6220_BBPPLL0_DIV>; 893 clock-names = "dacodec", "i2s-base"; 894 dmas = <&dma0 15 &dma0 14>; 895 dma-names = "rx", "tx"; 896 hisilicon,sysctrl-syscon = <&sys_ctrl>; 897 #sound-dai-cells = <1>; 898 }; 899 900 thermal-zones { 901 902 cls0: cls0 { 903 polling-delay = <1000>; 904 polling-delay-passive = <100>; 905 sustainable-power = <3326>; 906 907 /* sensor ID */ 908 thermal-sensors = <&tsensor 2>; 909 910 trips { 911 threshold: trip-point@0 { 912 temperature = <65000>; 913 hysteresis = <0>; 914 type = "passive"; 915 }; 916 917 target: trip-point@1 { 918 temperature = <75000>; 919 hysteresis = <0>; 920 type = "passive"; 921 }; 922 }; 923 924 cooling-maps { 925 map0 { 926 trip = <&target>; 927 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 928 }; 929 }; 930 }; 931 }; 932 933 ade: ade@f4100000 { 934 compatible = "hisilicon,hi6220-ade"; 935 reg = <0x0 0xf4100000 0x0 0x7800>; 936 reg-names = "ade_base"; 937 hisilicon,noc-syscon = <&medianoc_ade>; 938 resets = <&media_ctrl MEDIA_ADE>; 939 interrupts = <0 115 4>; /* ldi interrupt */ 940 941 clocks = <&media_ctrl HI6220_ADE_CORE>, 942 <&media_ctrl HI6220_CODEC_JPEG>, 943 <&media_ctrl HI6220_ADE_PIX_SRC>; 944 /*clock name*/ 945 clock-names = "clk_ade_core", 946 "clk_codec_jpeg", 947 "clk_ade_pix"; 948 949 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, 950 <&media_ctrl HI6220_CODEC_JPEG>; 951 assigned-clock-rates = <360000000>, <288000000>; 952 dma-coherent; 953 status = "disabled"; 954 955 port { 956 ade_out: endpoint { 957 remote-endpoint = <&dsi_in>; 958 }; 959 }; 960 }; 961 962 dsi: dsi@f4107800 { 963 compatible = "hisilicon,hi6220-dsi"; 964 reg = <0x0 0xf4107800 0x0 0x100>; 965 clocks = <&media_ctrl HI6220_DSI_PCLK>; 966 clock-names = "pclk"; 967 status = "disabled"; 968 969 ports { 970 #address-cells = <1>; 971 #size-cells = <0>; 972 973 /* 0 for input port */ 974 port@0 { 975 reg = <0>; 976 dsi_in: endpoint { 977 remote-endpoint = <&ade_out>; 978 }; 979 }; 980 }; 981 }; 982 983 debug@f6590000 { 984 compatible = "arm,coresight-cpu-debug","arm,primecell"; 985 reg = <0 0xf6590000 0 0x1000>; 986 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 987 clock-names = "apb_pclk"; 988 cpu = <&cpu0>; 989 }; 990 991 debug@f6592000 { 992 compatible = "arm,coresight-cpu-debug","arm,primecell"; 993 reg = <0 0xf6592000 0 0x1000>; 994 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 995 clock-names = "apb_pclk"; 996 cpu = <&cpu1>; 997 }; 998 999 debug@f6594000 { 1000 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1001 reg = <0 0xf6594000 0 0x1000>; 1002 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 1003 clock-names = "apb_pclk"; 1004 cpu = <&cpu2>; 1005 }; 1006 1007 debug@f6596000 { 1008 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1009 reg = <0 0xf6596000 0 0x1000>; 1010 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 1011 clock-names = "apb_pclk"; 1012 cpu = <&cpu3>; 1013 }; 1014 1015 debug@f65d0000 { 1016 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1017 reg = <0 0xf65d0000 0 0x1000>; 1018 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 1019 clock-names = "apb_pclk"; 1020 cpu = <&cpu4>; 1021 }; 1022 1023 debug@f65d2000 { 1024 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1025 reg = <0 0xf65d2000 0 0x1000>; 1026 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 1027 clock-names = "apb_pclk"; 1028 cpu = <&cpu5>; 1029 }; 1030 1031 debug@f65d4000 { 1032 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1033 reg = <0 0xf65d4000 0 0x1000>; 1034 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 1035 clock-names = "apb_pclk"; 1036 cpu = <&cpu6>; 1037 }; 1038 1039 debug@f65d6000 { 1040 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1041 reg = <0 0xf65d6000 0 0x1000>; 1042 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 1043 clock-names = "apb_pclk"; 1044 cpu = <&cpu7>; 1045 }; 1046 }; 1047}; 1048